KR20010061375A - Power-up circuit - Google Patents

Abstract

PURPOSE: A power up circuit is provided to stabilize a power up initialized operation by controlling an enable timing variation of a power up signal. CONSTITUTION: A power up circuit includes a potential sensing part(15), an external driving part(25), and an enable timing control part(35). The potential sensing part(15) senses whether an external source voltage(Vext) is higher than a fixed potential or not. The output driving part(25) is driven and controlled by an output signal(det) of the potential sensing part(15), and controls an existing of an enable of a power up signal. The enable timing control part(35) transfers an output voltage controlled according to each model to the output driving part(25), and controls an enable timing of the power up signal. At this time, the output voltage controlled according to each model plays a role as an operation control signal of the output driving part(25).

Description

Power-up Circuit

The present invention relates to a power-up circuit used for stable operation of a semiconductor memory device, and more particularly, to minimize an enable timing variation of power-up signals for each model divided according to various parameter value changes in a process. The present invention relates to a power-up circuit which aims to stabilize a power-up initialization operation by reducing the skew difference in time.

In general, after the external power supply voltage Vext is applied to the DRAM, the substrate bias voltage Vbb is negative from the ground voltage by the charge pumping operation of the substrate bias voltage generation circuit Vbb. Some time is required to reach the negative voltage.

This is because not only the substrate capacitance Cs is large but also the power supply voltage is increasing from 0V to 5V, so the oscillation frequency of the ring oscillator in the substrate bias voltage generation circuit is low, so that the current supply capability of the substrate is small. In addition, since the voltage Vcp applied to the cell plate covering the entire DRAM cell region is increased from 0V to Vcc / 2, the substrate bias voltage Vbb is also positive due to the coupling capacitance with the substrate. It rises together in the) direction and puts a burden on the substrate bias voltage generating circuit, and a large transient current can flow.

On the other hand, since a certain amount of time is required for the external power supply voltage Vext applied from the outside to rise to an operating voltage level of a predetermined potential level, the substrate bias voltage Vbb after a predetermined time passes after the voltage is applied. ) And the operation of the DRAM is reliable only after the operating voltage is stabilized.

For this reason, a signal for detecting that the substrate bias voltage (Vbb), the operating voltage, and the like has a desired level (generally called a power-up signal) is generated to generate a rasbar (/ RAS), It controls important control signals, such as the cas-ba (/ CAS) signal. The circuit used here is the power-up circuit.

FIG. 1 illustrates a configuration diagram of a power-up circuit used in the related art, and includes a potential sensing unit 10 for detecting that a potential of an external power supply voltage Vext is greater than or equal to a predetermined potential, and the potential sensing unit 10. And an output driver 20 which is driven and controlled according to the output signal det of the generator to generate the power-up signal pwr_up.

In the embodiment according to the drawing, the potential sensing unit 10 is connected in series between the external power supply voltage Vext applying terminal and the ground terminal by a node N1 to perform voltage distribution at a constant ratio according to the resistance ratio thereof. A gate of the NMOS transistor MN2 in the output driver 20, which is composed of two resistors R1 and R2 and whose potential signal of the node N1 divided by the two resistors R1 and R2 is connected to the rear end. In this case, the initialization time of the power-up signal pwr_up is determined according to whether it is turned on.

In addition, the output driver 20 is connected between the PMOS transistor MP1 having a gate connected to the ground between the external power supply voltage Vext and the node N2, and is connected between the node N2 and the ground terminal. The NMOS transistor MN2 to which the final output signal det of the potential sensing unit 10 is applied to the gate terminal and the inverter IV1 buffering the potential of the node N2 to generate a power-up signal pwr_up. ) Is configured.

FIG. 2 is a diagram illustrating a simulation result of the power-up circuit shown in FIG. 1. Hereinafter, an operation of a power-up circuit used in the related art will be described with reference to the drawing.

First, as the waveform shown in (a), the external power supply voltage Vext gradually increases in potential and is applied into the DRAM, and according to the resistance ratio of the two resistors R1 and R2 in the potential sensing unit 10. The potential of the node N1 rises with a constant ratio as shown in (b). At the same time, the PMOS transistor MP1 in the output driver 20 is also turned on because the gate terminal is held at the 'low level' by the ground terminal Vss, so that the potential of the node N2 is externally supplied. It is raised with the power supply voltage Vext, which is shown by the waveform of (c).

On the other hand, when the potential of the node N1 becomes equal to or higher than a predetermined potential level (in this case, the potential level equal to or higher than the threshold potential of the MN2 transistor), the NMOS transistor MN2 in the output driver 20 is turned on. The potential of the node N2 is dropped as shown in (c).

Accordingly, the potential of the power-up signal pwr_up, which was initially set to 'low level', rapidly increases, and eventually increases along with the potential of the external power voltage Vext shown in (a). This is shown by the waveform of (d).

However, in the case of the memory device, since the parameter characteristics of the NMOS transistor or the PMOS transistor are not constant according to the change in the process thereof, the power-up according to the prior art that generates the power-up signal pwr_up by the above operation. In the circuit, there is a problem that the enable timing of the power-up signal changes according to the parameter characteristics of the two MOS transistors MP1 and MN2 in the output driver 20.

For example, when the NMOS transistor MN2 in the output driver 20 is designed to operate quickly and the PMOS transistor MP1 operates slowly according to a parameter characteristic change (hereinafter, this case is referred to as an FS model). ), Since the current driving capability to the ground terminal Vss through the NMOS transistor MN2 is greater than the current driving capability from the external power supply voltage Vext applying terminal through the PMOS transistor MP1, As the potential of the node N2 drops to the 'low level' faster than the basic model, the power-up signal pwr_up is enabled at such a high speed.

On the other hand, when the NMOS transistor MN2 in the output driver 20 is designed to be slow and the PMOS transistor MP1 is driven fast according to a parameter characteristic change (hereinafter, this case is referred to as an 'SF model'), The current driving capability from the external power supply voltage Vext applied terminal through the PMOS transistor MP1 is greater than the current driving capability through the NMOS transistor MN2 to the ground terminal Vss, and thus the node. As the potential of (N2) drops to 'low level' more slowly than the basic model, it enables the power-up signal (pwr_up) as slowly as possible.

FIG. 3 is a signal waveform diagram showing parameter dependence of the power-up circuit shown in FIG. 1. When the parameter dependence of the power-up signal with respect to the basic model is the same as the waveform (a) shown in solid line, (When both MOS transistors MP1 and MN2 in the output driver 20 are designed to have fast driving capability) and in the case of the slow model (both MOS transistors MP1 and MN2 in the output driver 20 have both slow driving capability. The parameter dependence of the case is designed to have a skew difference within the limit tolerance, such as the waveforms of (b) and (c) shown by the narrow dotted lines shown on the left and right sides of the waveform shown by the solid line, respectively. Is enabled with.

By the way, in the case of the FS model and the SF model described above, such a wide dotted line waveform as shown in (d) and (e) of the figure is enabled with a skew difference outside the above-described limit tolerance range.

As can be seen from the figure, in the conventional power-up circuit, the enable timing of the power-up signal pwr_up varies greatly even with a slight change in the model parameter, thereby power-up between the two models (FS model and SF model). As the skew difference of the initialization time increases, a problem occurs that the initialization operation is not normally performed when the power-up signal is enabled too quickly as in the FS model, and the power-up signal is too slow as in the SF model. When enabled, there is a problem that the low power (low Vcc) characteristics are lowered.

That is, there is a problem in that stabilization of circuit operation is generally reduced as the enable timing of the power-up signal varies greatly even with a slight change in the parameter value.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to minimize the skew difference of power-up initialization time between models by minimizing the enable timing variation rate of the power-up signal according to the process parameter value change. The present invention provides a power-up circuit which is designed to reduce and stabilize circuit operation.

In order to achieve the above object, the power-up circuit according to the present invention includes a potential sensing means for detecting that the potential of the external power supply voltage is equal to or more than a predetermined potential;

Output driving means for driving control by an output signal of the potential sensing means to control whether a power-up signal is enabled;

Enabling timing adjusting means for controlling the enable timing of the power-up signal by transmitting the output voltage differentiated by the potential control according to the change of the process parameter value to the operation control signal of the output driving means; It is done.

1 is a block diagram of a conventional power-up circuit;

FIG. 2 is a simulation result diagram of the power-up circuit shown in FIG.

3 is a signal waveform diagram showing parameter dependence of the power-up circuit shown in FIG.

4 is a schematic diagram of a power-up circuit according to the present invention;

5 is a signal waveform diagram showing parameter dependence of the power-up circuit shown in FIG.

<Description of the symbols for the main parts of the drawings>

10, 15: potential detector 20, 25: output driver

35: enable timing adjuster

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a configuration diagram of a power-up circuit according to the present invention, which includes a potential sensing unit 15 for detecting that a potential of an external power supply voltage Vext is greater than or equal to a predetermined potential, and the potential sensing unit 15. An output driver 25 for controlling driving of the power-up signal pwr_up by driving the output signal det, and for each model (eg, Fast model, divided according to a process parameter value change). Enable to adjust the enable timing of the power-up signal pwr_up by transferring the output voltage Vr_p differentiated by the potential control by the FS model, the SF model, and the slow model to the operation control signal of the output driver 25. The timing adjustment part 35 is comprised.

Like the configuration of the potential sensing unit 10 in the power-up circuit shown in FIG. 1, the potential sensing unit 15 is connected in series by a node N1 between an external power supply voltage Vext applying terminal and a ground terminal. It consists of two resistors R1 and R2 which are connected and perform voltage distribution at a constant rate according to the resistance ratio.

The enable timing controller 35 is connected to the external power voltage applying terminal and each node N2 and N3 in a current mirror structure, and two PMOSs having their respective gate terminals connected to the node N3 in common. Two NMOS transistors MN2 connected in a current mirror structure between transistors MP1 and MP2 and the two nodes N2 and N3 and the ground terminals, respectively, and each gate terminal thereof is commonly connected to the node N2. And MN3).

In addition, the output driver 25 is supplied with the potential signal Vr_p of the node N3, which is the final output terminal of the enable timing controller 35, as a gate terminal, and an external power supply voltage Vext is applied to a source terminal. Connected in series between the PMOS transistor MP3 connected to the PMOS transistor MP3 and the drain terminal N4 of the PMOS transistor MP3 and the ground terminal, and the output signal det of the potential sensing unit 15 is connected to each gate terminal. ) And the two NMOS transistors MN4 and MN5 to which the potential signal of the node N2 in the enable timing adjusting unit 35 is applied, and the drain terminal potential of the PMOS transistor MP3 is buffered to provide power. The inverter IV1 which outputs the up signal pwr_up is comprised.

Hereinafter, the operation of the present invention having the above configuration will be described in detail.

First, in accordance with the potential rise of the external power supply voltage Vext, the potential sensing unit 15 has a constant ratio of the potential detection signal det due to voltage distribution by the resistance ratio of the two resistors R1 and R2. Will rise. At the same time, the potential of the node N4 in the output driver 25 also increases with the potential of the external power supply voltage Vext, but the potential difference between the gate and the source of the PMOS transistor in the inverter IV1 connected to the rear stage is increased. (Hereinafter referred to as 'Vgs') is smaller than the threshold potential, while the Vgs of the NMOS transistor is gradually increased, the potential of the power-up signal (pwr_up), the final output signal, is kept at 'low level'. Will be initialized.

After that, when the potential of the external power supply voltage Vext rises to a predetermined level or more, the potential of the output signal det of the potential sensing unit 15 causes the NMOS transistor MN4 in the output driver 25. It becomes high enough to turn on so that the potential of the node N4 is drastically lowered. Accordingly, the power-up signal pwr_up is enabled to accompany and increase along the potential of the external power voltage Vext.

The time compensation by the enable timing controller 35 solves the problem of increasing the skew difference in the enable time caused by the enable timing of the power-up signal pwr_up being greatly changed according to the parameter characteristics of each model. It is the core principle of the present invention.

Therefore, in the case of the FS model, it becomes faster than the earliest time of the limit tolerance of the enabling timing skew difference of the power-up signal, and in the case of the SF model, it becomes slower than the slowest time of the limit tolerance. Therefore, the enable timing adjustment operation of the power-up signal pwr_up by the enable timing controller 35 will be described in detail with reference to the FS model and the SF model in which the skew difference is increased beyond the allowable range.

First, in the semiconductor process, when the NMOS transistor is manufactured to have a fast driving capability and the PMOS transistor has a slow driving capability, that is, in the case of the FS model, two in the enable timing controller 35 shown in FIG. As the NMOS transistors MN2 and MN3 flow a current to the ground terminal more strongly than the two PMOS transistors MP1 and MP2, the potential of the output signal Vr_p is adjusted to a lower potential level than in the basic model.

As described above, the output signal Vr_p adjusted to the low potential is transferred to the gate terminal of the PMOS transistor MP3 in the output driver 25 in the rear stage to increase the Vgs of the transistor, and the PMOS transistor for a long time. The MP3 is turned on to increase the supply of the external power supply voltage Vext. The PMOS transistor MP3 is compared with the NMOS transistor MN4 even when the NMOS transistor MN4 in the output driver 25 is turned on due to the potential rise of the output signal det of the potential detector 15. Because of the large current supply capability, it is possible to control the potential of the node N4 to transition slowly to a 'low level', resulting in a timing at which the power-up signal pwr_up is enabled to a 'high level'. The slower you can adjust.

On the other hand, when the NMOS transistor is designed to have a relatively slow driving capability and the PMOS transistor has a fast driving capability in the semiconductor design process, that is, in the case of the SF model, the enable timing controller 35 shown in FIG. As the two PMOS transistors MP1 and MP2 in the circuit receive current from the power supply more powerfully than the two NMOS transistors MN2 and MN3, the potential of the output signal Vr_p is adjusted to a higher potential level than that of the basic model. Done.

As described above, the output signal Vr_p adjusted to the high potential is transferred to the gate terminal of the PMOS transistor MP3 in the output driver 25 at the rear stage to reduce the Vgs of the transistor, thereby increasing the PMOS transistor MP3. By reducing the conduction current of, the supply of the external power supply voltage Vext is reduced. This is because when the NMOS transistor MN4 in the output driver 25 is turned on due to the potential rise of the output signal det of the potential detector 15, the potential of the node N4 is 'high' at a higher speed. This provides a condition for transitioning to 'level', and as a result, speeds up the timing at which the power-up signal pwr_up is enabled to 'high level'.

By controlling the enable timing of the power-up signal (pwr_up), the skew difference in power-up time for each model (Fast model, FS model, SF model, Slow model) is adjusted to change within the limit tolerance. will be.

FIG. 5 is a signal waveform diagram showing the parameter dependence of the power-up circuit shown in FIG. 4, when the parameter dependence of the power-up signal with respect to the base model is the same as the waveform (a) shown in solid lines. The model shows that the power-up signal is enabled with a skew difference within the above limit tolerance as shown by the dotted line waveforms shown by the waveforms of (b) and (c). Comparing the signal waveform diagram shown in FIG. 3 with the signal waveform diagram of FIG. 3, it can be seen that the skew difference is greatly reduced from 0.5V to 0.3V.

As described above, according to the power-up circuit according to the present invention, the enable timing change of the power-up signal for each model according to the change of the parameter value in the process can be adjusted to have a skew difference within the limit tolerance. In addition, there is an excellent effect of enabling a more stable power-up initialization operation to be performed.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (3)

Potential detection means for detecting that the potential of the external power supply voltage is greater than or equal to a predetermined potential; Output driving means for driving control by an output signal of the potential sensing means to control whether a power-up signal is enabled; Enabling timing adjustment means for controlling the enable timing of the power-up signal by transferring the output voltage differentiated by the potential control according to the change of the process parameter value to the operation control signal of the output driving means; Power-up circuit. The method of claim 1, The enable timing adjusting means may include a first and second PMOS transistors having a current mirror structure between an external power supply voltage applying end and first and second nodes, each gate end of which is commonly connected to the second node. , A first and second NMOS transistors each connected in a current mirror structure between the first and second nodes and a ground terminal, and each gate terminal is commonly connected to the first node. -Up circuit. The method of claim 2, The output driving means may include a third PMOS transistor having a second node connected to a gate terminal, and an external power supply voltage applying terminal connected to a source terminal; Third and fourth NMOS transistors connected in series between a drain terminal and a ground terminal of the third PMOS transistor, and to which an output signal of the potential sensing means and a potential signal of the first node are applied to each gate terminal; , And an inverter for buffering the drain terminal potential of the third PMOS transistor to output a power-up signal.