KR100596861B1 - Internal voltage generator - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal voltage generator used in a semiconductor memory device, and in particular, adjusts a gate voltage potential level of a driving device that pulls up and pulls down an internal voltage in response to a potential change by receiving an internal voltage from an output terminal. By increasing the pull-up and pull-down driving capacity of the internal voltage significantly in proportion to the degree of change of the potential of the internal voltage, the present invention relates to an internal voltage generator for ensuring a more stable internal voltage at a high potential level at high speed. .

Description

Internal voltage generator

FIG. 1 is a circuit diagram illustrating a conventional bit line precharge voltage generator using a source following method.

FIG. 2 is a simulation result diagram showing a potential change for each node in the bit line precharge voltage generator shown in FIG.

3 is a circuit diagram illustrating a bit line precharge voltage generator according to an exemplary embodiment of the present invention.

4 is a circuit diagram illustrating another example of the driving control unit illustrated in FIG. 3.

FIG. 5 is a simulation result diagram showing a potential change for each node in the bit line precharge voltage generator shown in FIG.

6 is a current-voltage characteristic comparison diagram comparing current driving capability in a bit line precharge voltage generator according to the related art and the present invention.

<Description of Symbols for Main Parts of Drawings>

10: pull-up part 20: pull-down part

30: driving control unit 40: driving capability increasing unit

The present invention relates to an internal voltage generation device of a semiconductor memory device, and more particularly, to feedback the internal voltage generated from the output stage to improve the pull-up and pull-down driving ability according to the potential change in device design. The present invention relates to an internal voltage generator for generating an internal voltage at a more stable potential level at a higher speed.

In general, most DRAM devices use a single internal voltage such as a bit line precharge voltage (Vblp) and a cell plate voltage (Vcp) to improve product, data, and operational reliability. It is generated and used by an internal voltage generator having the same circuit structure. In the present invention, the following description will be focused on the bit line precharge voltage generator.

Therefore, the structure of the generator of the bit line precharge voltage as the internal voltage according to the present invention can be similarly applied to the internal voltage generator for generating the cell plate voltage.

In general, the bit line structure of the DRAM device uses a folded bit-line structure in which the bit lines are arranged in pairs in order to favor noise characteristics, thereby improving reliability of operation and reducing power consumption. For this purpose, 1 / 2Vdd voltage is used as the bit line precharge voltage.

Although there are various bit line precharge voltage generators for generating the 1 / 2Vdd voltage, a bit line precharge voltage generator having a source following method (source following) which is most commonly used will be shown in FIG. 1. .

1 is a circuit diagram illustrating a conventional source following method of a bit line precharge voltage generator. The bit line precharge node is connected between a power supply voltage Vcc and a ground terminal Vss. Pull-up section 10 and pull-down section 20 which pull-up and pull-down potential of N0 and pull-up control signal according to the potential change of the bit line precharge node N0, respectively. And a drive controller 30 for selectively generating a pull-down control signal to control driving of the pull-up unit 10 and the pull-down unit 20.

In the same figure, the pull-up part 10 is connected between a power supply voltage Vcc applying end and the bit line precharge node N0, and is supplied from an output node N1 of the driving control part 30. The NMOS transistor MN1 receives the pull-up driving control signal pu from the gate terminal.

The pull-down unit 20 is connected between the bit line precharge node N0 and the ground terminal Vss, and is pull-down supplied from the other output node N2 of the driving controller 30. The PMOS transistor MP1 receives the driving control signal pd from the gate terminal.

In addition, the driving controller 30 may include a PMOS transistor MP2 connected to a ground and connected between a power supply voltage Vcc and a pull-up control signal pu, and a node N1. NMOS transistor MN2 connected to the diode type, PMOS transistor MP3 connected to the NMOS transistor MN2 and diode-connected to the node N2, and the pull-down driving control signal pd. The NMOS transistor MN3 is connected between the applying terminal N2 and the ground terminal and supplied with a power supply voltage to the gate terminal.

FIG. 2 is a simulation result diagram showing potential change of each node in the bit line precharge voltage generator shown in FIG. 1, (a) represents a bit line precharge voltage Vblp, and (b) and (c) The potentials of the nodes N1 and N2 to which the pull-up and pull-down drive control signals pu and pd are applied, respectively.

As can be seen from the figure, the conventional bit line precharge voltage generator has a potential of the pull-up control signal applying terminal N1 as shown in (b), and the bit line precharge voltage shown in (a). (Vblp: 1.0V in the same figure) is applied at a constant potential (about 1.8V) higher than the MOS transistor threshold voltage (about 0.8V), as shown in (c) Similarly, the potential of the pull-down control signal applying terminal N2 is constant to a potential (about 0.2V) lower than the threshold voltage (about 0.8V) of the MOS transistor than the bit line precharge voltage (Vblp: 1.0V). By applying this, the bit line precharge voltage Vblp is controlled to be a source voltage of each of the NMOS transistor MN1 and the PMOS transistor MP1 constituting the pull-up unit 10 and the pull-down unit 20. do.

Accordingly, the gate-source potential difference Vgs of the MOS transistors MN1 and MP1 constituting the pull-up part 10 and the pull-down part 20 according to the potential change of the bit line precharge voltage Vblp. By changing, the bit line precharge voltage driving capability can be adjusted.

For example, when the potential of the bit line precharge voltage Vblp drops, the potential of the pull-up control signal applying terminal N1 is constantly maintained at a predetermined potential level (about 1.78 V). As the gate-source potential difference Vgs of the NMOS transistor MN1 in the pull-up section 10 becomes wider, the current is gradually turned on to supply current from the supply voltage Vcc to the bit line precharge node N0. Flows to raise the potential of the bit line precharge voltage Vblp.

Meanwhile, even when the potential of the bit line precharge voltage Vblp rises too high, the potential of the pull-down control signal applying terminal N2 is similarly maintained at a predetermined potential level (about 0.23V). As the gate-source potential difference Vgs of the PMOS transistor MP1 in the pull-down part 20 becomes wider, the current is gradually turned on to flow current from the bit line precharge node N0 to the ground terminal. As a result, it operates to bring down the potential of the bit line precharge voltage Vblp.

 The conventional bit line precharge voltage generator which adjusts the potential level of the bit line precharge voltage by the operation may control the driving control signals pu and pd of the pull-up unit 10 and the pull-down unit 20. Because of the reason that the potential level of the two nodes (N1, N2) to be applied is always kept constant regardless of the potential change of the bit line precharge voltage (Vblp), and is generally insensitive to the change of the bit line precharge voltage, the bit line If the potential change of the precharge voltage is weak, a problem arises in that the pull-up and pull-down driving capability of the changed bit line precharge voltage becomes insignificant.

In addition, if the size of the pull-up and pull-down transistors is large to increase the insufficient pull-up and pull-down driving capability as described above, a problem arises that the design area burden occurs, which is insufficient in another method. When the potential level of the pull-up control signal applying terminal N1 is lowered and the potential level of the pull-down control signal applying terminal N2 is increased to increase the pull-up and pull-down driving capability, the power is supplied in the stand-by situation. The current consumption is greatly increased through the pull-up and pull-down transistors MN1 and MP1 connected between the voltage Vcc applying terminal and the ground terminal Vss.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to feedback the internal voltage (bit line precharge voltage or cell plate voltage) from the output stage to the potential of the pull-up and pull-down control signal application stage. The present invention provides an internal voltage generator that increases the potential difference between the gate-source of each of the pull-up and pull-down transistors by greatly changing the potential of the bit line precharge voltage.

In order to achieve the above object, the internal voltage generator according to the present invention is connected in series between the power supply voltage supply terminal and the ground terminal through the internal voltage output terminal to pull the internal voltage potential according to pull-up and pull-down control signals, respectively. Pull-up and pull-down sections for up- and pull-down; A drive controller for selectively generating pull-up and pull-down control signals according to a potential change of an internal voltage to control driving of the pull-up unit and the pull-down unit; By receiving feedback of the internal voltage output terminal potential and selectively performing pull-up and pull-down operations according to the change of the potential, and supplying the output potential to the drive control part, the pull-up and pull-down drive capability of the drive control part is supplied. It characterized in that it comprises a drive capability increasing section for controlling to increase in accordance with the amount of potential change.

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The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram illustrating a bit line precharge voltage generator according to an exemplary embodiment of the present invention, wherein an internal voltage (bit line precharge voltage Vblp in the same figure) is applied between a power supply voltage Vcc and a ground terminal Vss. A pull-up part 10 and a pull-down part 20 connected in series via an output terminal N0 to pull-up and pull-down the internal voltage Vblp potential, respectively; By selectively generating pull-up and pull-down control signals pu and pd according to the potential change of the internal voltage Vblp, the driving of the pull-up part 10 and the pull-down part 20 is controlled. A drive controller 30; By receiving the potential of the internal voltage output terminal N0 and selectively performing pull-up and pull-down operations according to the change of the potential, the output potential is supplied to the driving controller 30, thereby providing And a driving capability increasing section 40 for increasing pull-up and pull-down driving capability in accordance with the potential change amount of the internal voltage Vblp.

Since the pull-up unit 10, the pull-down unit 20, and the driving control unit 30 shown in FIG. 1 are the same as those of the bit line precharge voltage generator shown in FIG. 1, detailed configuration and operation description are omitted. Hereinafter, the following description will proceed to the driving capability increasing unit 40 which is the core configuration of the present invention.

The driving capability increasing unit 40 is connected in series between a power supply voltage Vcc applying terminal and a ground terminal Vss, and a PMOS to which a potential of the bit line precharge voltage output terminal N0 is applied to each gate terminal. A transistor MP4 and an NMOS transistor MN4 are provided, and the connection node fb of the two MOS transistors MP4 and MN4 is connected to the two diode-type MOS transistors MN2 and MP3 in the power supply unit 30. It is configured to be connected to the connection node.

FIG. 4 is a circuit diagram showing another embodiment of the driving capability increasing unit 40 shown in FIG. 3. In the basic configuration of the driving capability increasing unit 40 shown in FIG. And further comprising a first resistance element R1 connected between the PMOS transistor MP4 as a ruler, and a second resistance element R2 connected between the NMOS transistor MN4 as the pull-down element and the ground terminal. do.

In this case, the first and second resistors R1 and R2 may be implemented as metal resistors or diodes or MOS transistors, respectively.

FIG. 5 is a simulation result showing the potential change of each node in the bit line precharge voltage generator having the above-described configuration. FIG. 5 is a bit line precharge voltage with respect to the bit line precharge voltage Vblp that changes in potential due to various external factors. The potentials of the two nodes N1 and N2 which control the pull-up and pull-down operation of the same do not maintain a constant potential level as in the prior art, but rather the pull-up and pull-up of (b) and (c). The potential of the down control nodes N1 and N2 gradually rises and decreases according to the degree of potential change of the bit line precharge voltage, and the potential rises together with the potential of the fb node shown in (a). And lowering to increase its pull-up and pull-down driving capability.

Hereinafter, the operation of the bit line precharge voltage generator according to the present invention will be described in detail with reference to the drawings.

First, when the potential of the bit line precharge voltage Vblp fed back to the driving capability increasing unit 40 is lower than a reference target value, a pull-up function in the driving capability increasing unit 40 is performed. The gate-source potential difference (Vgs) of the PMOS transistor MP4 that performs the operation becomes gradually larger and is turned on as a result, while the gate-source potential difference of the NMOS transistor MN4 that performs the pull-down function is It becomes smaller and eventually turns off.

Accordingly, while the current flowing from the power supply potential to the output node fb of the driving capability increasing unit 40 increases, the potential of the node fb is increased. At this time, the NMOS transistor MN1 in the pull-up unit 10 is increased. The potential of the node N1 connected to the gate terminal of the potential higher than the threshold potential of the diode-connected NMOS transistor MN2 in the driving control unit 30 is higher than the output node fb of the driving capability increasing unit 40. It will rise along with it. Accordingly, as the NMOS transistor MN1 constituting the pull-up unit 10 is gradually turned on more powerfully, the pull-up control of the bit line precharge voltage Vblp, which has decreased potential, is pulled up to a conventional constant potential. Compared to the technology that was used to further increase.

On the other hand, when the potential of the bit line precharge voltage Vblp fed back to the driving capability increasing unit 40 rises above a reference target value, a pull-down function is performed in the driving capability increasing unit 40. The gate-source potential difference Vgs of the NMOS transistor MN4 that performs the stepwise becomes large, and as a result, the gate-source potential difference of the PMOS transistor MP4 that performs the pull-up function gradually increases. Smaller and eventually turn off.

Therefore, as the current flowing from the output node fb of the driving capability increasing unit 40 to the ground terminal increases, the potential of the node fb is dropped, and at this time, the PMOS transistor MP1 in the pull-down unit 20 is reduced. The potential of the node N2 connected to the gate terminal of the N1 is maintained at a low potential level lower than the threshold potential of the diode-connected PMOS transistor MP3 than the output node fb of the driving capability increasing unit 40. Goed down with it. Accordingly, the PMOS transistor MP1 constituting the pull-down part 20 is turned on more strongly and pull-down control of the bit-line precharge voltage Vblp that has risen in potential is pull-down controlled to a conventional constant potential. It's going to be done a bit more than the technology.

6 is a comparison diagram of current-voltage characteristics comparing the current driving capability of the prior art and the bit line precharge voltage generator according to the present invention. The dotted line shows the result of the prior art, and the solid line shows the simulation result of the present invention. As shown in the drawings, it can be seen that the pull-up and pull-down driving capability of the bit line precharge voltage generator according to the present invention is much superior to those of the prior art.

As described above, in the bit line precharge voltage generator according to the present invention, the device is controlled to increase the pull-up and pull-down driving capability for the potential compensation according to the potential change of the feedback internal voltage. The design has a very excellent effect of ensuring a stable internal voltage at a high potential level at high speed.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (7)

A pull-up unit and a pull-down unit which are connected in series between a power supply terminal and a ground terminal through an internal voltage output terminal to pull up and pull down the internal voltage potential according to pull-up and pull-down control signals, respectively. Wow; A drive controller for selectively generating the pull-up and pull-down control signals according to a potential change of the internal voltage to control driving of the pull-up unit and the pull-down unit; The pull-up and pull-down driving capability of the drive controller is supplied by feeding back the potential of the internal voltage output terminal and selectively performing pull-up and pull-down operations according to the potential change, and supplying the output potential to the drive controller. And an driving capability increasing unit for controlling the voltage to increase according to the potential change amount of the internal voltage. The method of claim 1, And the internal voltage is a bit line precharge voltage. The method of claim 1, The internal voltage generator is characterized in that the cell plate voltage. The method of claim 1, The driving control unit includes a first NMOS transistor and a first PMOS transistor having a diode type structure between a power supply voltage applying terminal and a ground terminal, respectively, connected in series. The method of claim 4, wherein The driving capability increasing unit may include a second PMOS transistor and a second NMOS transistor in which the internal voltage is applied to each gate terminal and is connected in series between a power supply voltage applying terminal and a ground terminal; And an output terminal thereof connected to a connection node of the first NMOS transistor and the first PMOS transistor. The method of claim 5, The driving capability increasing unit includes a first resistance element connected between the power supply voltage applying stage and a second PMOS transistor; And a second resistance element connected between the second NMOS transistor and a ground terminal. The method of claim 6, And the first and second resistor elements comprise one of a metal resistor, a diode, and a MOS transistor.

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