KR20100129991A - Vbb level sensor apparatus of semiconductor memory apparatus - Google Patents

Vbb level sensor apparatus of semiconductor memory apparatus Download PDF

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Publication number
KR20100129991A
KR20100129991A KR1020090048627A KR20090048627A KR20100129991A KR 20100129991 A KR20100129991 A KR 20100129991A KR 1020090048627 A KR1020090048627 A KR 1020090048627A KR 20090048627 A KR20090048627 A KR 20090048627A KR 20100129991 A KR20100129991 A KR 20100129991A
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KR
South Korea
Prior art keywords
level
voltage
vbb
bias voltage
operating temperature
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KR1020090048627A
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Korean (ko)
Inventor
강동금
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주식회사 하이닉스반도체
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Priority to KR1020090048627A priority Critical patent/KR20100129991A/en
Publication of KR20100129991A publication Critical patent/KR20100129991A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects

Abstract

PURPOSE: A VBB level sensor apparatus of semiconductor memory apparatus is provided to improve the characteristic deterioration of a memory cell transistor according to the operation temperature variation by varying the VBB target level according to the operation temperature in order to respond to the threshold voltage of the cell transistor. CONSTITUTION: A temperature sensing part(100) outputs the temperature sensing signal having the voltage level varying according to the operation temperature variation. A bias generating unit(200) varies the level of first and second bias voltages according to the voltage level of the temperature sensing signal.

Description

Substrate bias voltage level sensing device of semiconductor memory device {VBB level Sensor Apparatus of Semiconductor Memory Apparatus}

The present invention relates to a semiconductor memory device, and more particularly, to a substrate bias voltage level sensing device of a semiconductor memory device.

Due to the high speed, high density, and low power of semiconductor memory devices, internal voltages have been used in semiconductor memory devices. The internal voltage is generated using a method of generating a reference voltage and charge pumping or down-converting the generated reference voltage. Typical internal voltages using charge pumping include boost voltage and substrate bias voltage (VBB). In addition, a representative internal voltage using down-converting or the like is a core voltage.

In general, the boosted voltage is a voltage for applying a potential higher than the external voltage VDD to the gate of the cell transistor when the cell data is accessed so that there is no loss of the cell data.

In addition, the substrate bias voltage VBB is used to increase the safety and reduce the channel leakage current by reducing the change in the threshold voltage Vt due to the body effect on the cell transistor. That is, in order to prevent loss of data stored in the cell transistor, the voltage for applying a bias voltage lower than the ground voltage VSS to the substrate of the cell transistor.

In addition, the core voltage CORE reduces the power loss of the core CORE and down-converts the external voltage VDD for stable operation of the core. It is the voltage that causes a constant potential to form against fluctuations.

The internal voltage generators for generating the internal voltages VPP, VBB, and VCORE described above are designed to operate with a constant deviation within the operating voltage range and the operating range temperature of the semiconductor memory device.

In general, in order to drive the semiconductor memory, an external voltage VDD is applied to the semiconductor memory, and the power-up signal is enabled when a predetermined potential is sufficient to operate the semiconductor memory.

At this time, when the power-up signal is enabled, the semiconductor memory device starts to generate internal power through charge pumping and down-converting.

Hereinafter, an apparatus for detecting a substrate bias voltage level of a general semiconductor memory will be described with reference to FIGS. 1 and 2.

1 is a block diagram illustrating a substrate bias voltage level sensing device according to the prior art.

Referring to FIG. 1, a conventional substrate bias voltage level sensing device includes a bias generator 10 and a VBB sensor 20.

The bias generator 10 generates a PMOS gate bias voltage VSP and an NMOS gate bias voltage VSN, which are constant gate bias voltages, as a reference voltage VREF.

The VBB sensor 20 receives the gate bias voltages VSN and VSP and generates a VBB pump enable signal VBB_PUMP_EN, and when the level of the substrate bias voltage VBB is higher than a target level, the VBB pump in Activates the enable signal VBB_PUMP_EN.

The VBB pump enable signal VBB_PUMP_EN is a signal for operating a VBB pump (not shown).

2 is a waveform diagram of a substrate bias voltage target level according to the prior art.

Referring to FIG. 2, the reference voltage VREF maintains a constant level regardless of the operating temperature. The VBB target level is a target level value of the substrate bias voltage VBB and has a dependency on the reference voltage VREF.

That is, it can be seen that the conventional VBB target level is independent of the operating temperature and has a dependency on the reference voltage VREF generating the gate bias voltage. Therefore, in order to adjust the VBB target level, the control unit may only adjust the level of the reference voltage VREF or adjust the size of the transistor in the VBB sensor 20.

In general, the substrate bias voltage VBB is used to increase the data retention time by increasing the threshold voltage of the cell transistor. However, when the threshold voltage of a cell transistor is high, a large amount of time is required to charge a cell with a desired amount of charge because a high threshold voltage must be overcome in order to write data to the cell during a write operation. need. This phenomenon becomes more severe as the temperature decreases, because the threshold voltage of the cell transistor increases as the temperature decreases.

However, as described above, the substrate bias voltage (VBB) level sensing device according to the prior art tends to maintain a constant threshold value of the VBB target level as the operating temperature decreases, thereby increasing the threshold voltage of the cell transistor. And eventually cause a tWR (time write recovery) failure.

Accordingly, an object of the present invention is to change the VBB target level according to the operating temperature so as to correspond to the threshold voltage of the cell transistor that changes according to the change in operating temperature. It is an object of the present invention to provide a substrate bias voltage level sensing device of a semiconductor memory device capable of improving the work loss.

The bias voltage sensing device of the semiconductor memory device of the present invention for achieving the above object is a temperature sensing unit for outputting a temperature sensing signal having a voltage level that is changed in accordance with a change in operating temperature by applying an external voltage, the temperature sensing signal and A VBB pump receiving a reference voltage and receiving a bias generator for varying levels of the first and second bias voltages according to the voltage level of the temperature sensing signal, and the first and second bias voltages and the substrate bias voltage; And a VBB sensor generating an enable signal and controlling whether the VBB pump enable signal is activated by changing a target level of the substrate bias voltage.

According to the present invention, when the operating temperature is low, the absolute value of the VBB target level is adjusted to be small, and when the operating temperature is high, the absolute value of the VBB target level is adjusted to be large, thereby deteriorating the characteristics of the memory cell transistor according to the change in the operating temperature. It can be improved.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram illustrating a substrate bias voltage level sensing device of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 3, the substrate bias voltage (VBB) level sensing apparatus of the present invention includes a temperature sensing unit 100, a bias generating unit 200, and a VBB sensor 300.

The temperature sensing unit 100 receives an external voltage VDD and outputs a temperature sensing signal DET_Th having a voltage level that is changed by adjusting a current sink amount according to a change in operating temperature.

The bias generator 200 receives the temperature sensing signal DET_Th and the reference voltage VREF, and adjusts the amount of current sink according to the turn-on resistance control according to the voltage level of the temperature sensing signal DET_Th. The first and second bias voltages VSN and VSP which are level gate bias voltages are generated.

The VBB sensor 300 receives the first and second bias voltages VSP and VSN to generate a VBB pump enable signal and generates a VBB pump enable signal according to a target level change of the substrate bias voltage VBB. VBB_PUMP_EN) is activated or not.

4 is a detailed circuit diagram of the temperature sensor shown in FIG. 3.

As shown in FIG. 4, the temperature sensing unit 100 includes a MOS transistor having a diode characteristic capable of adjusting the level of the temperature sensing signal DET_Th according to the amount of current sink by varying the turn-on resistance according to a temperature change. Can be.

For example, when the operating temperature is lowered, the threshold voltages of the MOS transistors N1 and N2 are increased to reduce the amount of current sink flowing to the first node A. At this time, the output voltage is output from the first node A. The level of the temperature sensing signal DET_Th is lowered.

On the contrary, when the operating temperature increases, the threshold voltage of the MOS transistor decreases to increase the amount of current sinking to the first node A. Thus, the level of the temperature sensing signal DET_Th output from the first node A is increased. Is higher than the low temperature. That is, the voltage level of the temperature detection signal DET_Th is changed according to temperature.

More specifically, the temperature sensing unit 100 includes a first PMOS transistor P1 having a gate terminal connected to a ground voltage VSS and a source terminal receiving an external voltage VDD, and a drain terminal having the first PMOS. A first NMOS transistor N1 connected to the drain terminal of the transistor P1, a gate terminal connected to the drain terminal, a drain terminal connected to a gate terminal, and the drain terminal connected to a source terminal of the first NMOS transistor N1, A second NMOS transistor N2 having a source terminal coupled to the first node A, a gate terminal receiving an external voltage VDD, a source terminal coupled to a ground voltage VSS, and a drain terminal coupled to the first node A third NMOS transistor N3 connected to the node A is provided, and the sensing signal DET_Th is output from the first node A. FIG.

FIG. 5 is a detailed circuit diagram of the bias generator illustrated in FIG. 3.

As illustrated in FIG. 5, the bias generator 200 may include an adjusting unit 210 that adjusts the degree of turning on in response to the level of the temperature sensing signal DET_Th output from the temperature sensing unit 100 and the The bias voltage generator 220 generates the first and second bias voltages VSN and VSP, which are gate bias voltages that vary according to the amount of current sink supplied from the controller 210.

More specifically, the controller 210 adjusts the amount of current applied to the bias voltage generator 220 by adjusting the degree of turn-on according to the temperature sensing signal DET_Th that varies according to the change in operating temperature.

The control unit 210 may be a MOS transistor. In the present invention, the gate terminal uses the PMOS transistor P2 whose turn-on degree is controlled by receiving the temperature sensing signal DET_Th.

Next, the bias voltage generator 220 includes third to fifth PMOS transistors P3, P4 and P5 and fourth to sixth NMOS transistors N4, N5 and N6.

The bias voltage generator 220 receives a reference voltage VREF, and according to the amount of sink current applied from the controller 210, the first bias voltage VSN and the gate of the PMOS transistor are gate bias voltages of the NMOS transistor. A second bias voltage VSP, which is a bias voltage, is generated.

More specifically, when the operating temperature is lowered, the degree of turn-on of the second PMOS transistor P2 to which the temperature sensing signal DET_Th of the low voltage level output from the temperature sensing unit 100 is applied is increased. The amount of current sinking in the node B becomes relatively small. The turn-on degree of the sixth NMOS transistor N6 to which the voltage of the second node node B is applied is lowered, and the turn-on degree of the fifth PMOS transistor P5 is smaller due to a higher threshold voltage as the temperature decreases. As the amount of current sinking of the sixth NMOS transistor N6 decreases, the third node node C has a higher 'high' level.

Therefore, the first bias voltage VSN output from the second node node B is output at the 'low' level, and the second bias voltage VSP output from the third node node C is at the 'high' level. Is output.

On the contrary, when the operating temperature increases, the degree of turn-on of the second PMOS transistor P2 to which the temperature sensing signal DET_Th of the high voltage level output from the temperature sensing unit 100 is applied decreases, thereby decreasing the second node. The amount of current sink in B) becomes relatively large.

Therefore, the turn-on degree of the sixth NMOS transistor N6 to which the voltage of the second node node B is applied increases, and the turn-on degree of the fifth PMOS transistor P5 decreases as the temperature increases. Gets bigger As the amount of current sinking of the sixth NMOS transistor N6 increases, the third node node C has a lower 'low' level.

Therefore, the level of the first bias voltage VSN output from the second node node B is output at a 'high' level, and the level of the second bias voltage VSP output from the third node node C is Output is at the 'low' level.

Hereinafter, a detailed circuit configuration of the bias generator 200 will be described.

The bias generator 200 has a gate terminal applied with a temperature sensing signal DET_Th, a source terminal applied with an external voltage VDD, and a source terminal applied with an external voltage VDD. A third PMOS transistor P3 connected to the drain terminal of the second PMOS transistor P2 and a gate terminal of the gate terminal to the gate terminal of the third PMOS transistor P3. The terminal receives the external voltage VDD, the drain terminal receives the fourth PMOS transistor P4 connected to the second node B, the gate terminal receives the reference voltage VREF, and the drain terminal receives the third voltage. A fourth NMOS transistor N4 connected to the drain terminal of the PMOS transistor P3, a source terminal connected to the ground voltage VSS, a drain terminal connected to the second node node B, and a gate terminal connected to the second node. (node B) and the source terminal is connected to the ground voltage (VSS) 5 NMOS transistor N5, the gate terminal is connected to the drain terminal, the source terminal is applied with an external voltage (VDD), the drain terminal is connected to the third node (node C), the fifth PMOS transistor (P5), the gate terminal is A sixth NMOS transistor N6 connected to a gate terminal of the fifth NMOS transistor N5, a drain terminal connected to the third node C, and a source terminal connected to a ground voltage VSS; The second node node B is configured to output a first bias voltage VSN, which is an NMOS gate bias voltage, and to output a second bias voltage VSP, which is a PMOS gate bias voltage, at the third node. .

6 is a waveform diagram of a substrate bias voltage target level according to an embodiment of the present invention.

As shown in FIG. 6, when the operating temperature decreases, the level of the second bias voltage VSP input to the VBB sensor 300 increases, and the level of the first bias voltage VSN decreases to decrease the VBB target. The absolute value of the level is lowered. On the contrary, when the temperature increases, the level of the second bias voltage VSP, which is the gate bias voltage of the PMOS transistor in the VBB sensor 300, is lowered, and the level of the first bias voltage VSN, which is the gate bias voltage of the NMOS transistor, is raised. This increases the absolute value of the VBB target level.

As a result, the absolute value of the VBB target level decreases when the operating temperature decreases, thereby increasing the VBB level (absolute value decrease) at low temperature. Therefore, when the operating temperature is low, the threshold voltage increase of the transistor can be attenuated to some extent to prevent tWR failing.

FIG. 7 is an exemplary diagram illustrating a circuit diagram of the VBB sensor illustrated in FIG. 1.

As shown in FIG. 7, the VBB sensor 300 has a level of the substrate bias voltage VBB according to the level change of the first and second bias voltages VSP and VSN output from the bias generator 200. Is sensed to set the VBB target level differently according to the level change of the substrate bias voltage VBB, thereby determining whether the VBB pump enable signal VBB_PUMP_EN is activated.

The VBB sensor 300 includes sixth to eighth PMOS transistors P6 to P8, a seventh NMOS transistor N7, and an eighth NMOS transistor N8.

Hereinafter, the operation and configuration of the VBB sensor 300 will be described in more detail.

When the operating temperature decreases, the second bias voltage applied to the gate of the sixth PMOS transistor P6 at a constant voltage level becomes smaller as the absolute value of the VBB target level decreases as the threshold voltage of the transistor increases. Increase the VSP).

At this time, since the turn-on degree of the eighth NMOS transistor N8 decreases, the voltage level of the fourth node node D requires a voltage lower than the existing level. Therefore, the voltage level of the fifth node node E may be output at a 'high' level to activate the VBB pump enable signal VBB_PUMP_EN output from the sixth node node F.

On the contrary, when the operating temperature is higher than the low temperature, the second bias voltage VSP applied to the gate of the sixth PMOS transistor P6 is increased by increasing the absolute value of the VBB target level according to the change according to the threshold voltage drop of the transistor. By lowering the voltage level of the fourth node (node D) is output to the 'low' level. In this case, the VBB pump enable signal VBB_PUMP_EN output from the sixth node F may be deactivated.

More specifically, a sixth PMOS transistor P6 having a gate terminal applied with the second bias voltage VSP, a source terminal receiving an external voltage VDD, and a drain terminal connected with a fourth node node D, A seventh NMOS transistor N7 having a gate terminal connected to the ground voltage VSS, a drain terminal connected to the fourth node node D, and a source terminal receiving a substrate bias voltage VBB, and a gate terminal connected to the ground voltage VSS. A seventh PMOS transistor P7 is applied with a second bias voltage VSP, a source terminal is applied with an external voltage VDD, a drain terminal is connected to a fifth node node E, and a gate terminal is the fourth node. an eighth NMOS transistor N8 connected to a node D, a source terminal connected to a ground voltage VSS, a drain terminal connected to a fifth node E, and a gate terminal connected to the fifth node E), the source terminal receives the external voltage (VDD), the drain terminal is connected to the sixth node (node F) Is an eighth PMOS transistor P8, a ninth NMOS transistor N9 having a gate terminal connected to the fifth node node E, a drain terminal connected to the sixth node F, and a gate terminal thereof The first bias voltage VSN is applied, the source terminal is connected to the ground voltage VSS, and the drain terminal includes a tenth NMOS transistor N10 connected to the source terminal of the ninth NMOS transistor N9.

Accordingly, the present invention provides a temperature sensing unit 100 for generating a temperature sensing signal whose voltage level is changed according to a change in operating temperature, and a current sink amount adjusted according to the voltage level change of the temperature sensing signal DET_Th. By using the bias generator 200 generating the first and second bias voltages VSN and VSP, the absolute value of the VBB target level according to the change in operating temperature may be varied.

That is, when the operating temperature is high, the absolute value of the VBB target level is increased, and when the operating temperature is low, the magnitude of the absolute value of the VBB target level is decreased, thereby decreasing the increase of the threshold voltage of the transistor to some extent when the operating temperature is decreased. You can do it. As a result, the tWR can be prevented from occurring when the operating temperature is lowered and the leakage current of the transistor can be cut off.

As such, those skilled in the art will appreciate that the present invention can be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

1 is a block diagram showing a substrate bias voltage level sensing device according to the prior art;

2 is a waveform diagram of a substrate bias voltage target level according to the prior art;

3 is a block diagram illustrating a substrate bias voltage level sensing device of a semiconductor memory device according to an embodiment of the present invention;

4 is a detailed circuit diagram of a temperature sensing unit shown in FIG. 3;

5 is a detailed circuit diagram of the bias generator shown in FIG. 3;

6 is a waveform diagram of a substrate bias voltage target level according to an embodiment of the present invention, and

FIG. 7 is an exemplary diagram illustrating a circuit diagram of the substrate bias voltage sensor illustrated in FIG. 3.

<Detailed Description of Main Drawing Codes>

100: temperature sensing unit 200: bias generating unit

300: VBB sensor

Claims (8)

A temperature sensing unit configured to receive an external voltage and output a temperature sensing signal having a voltage level that varies according to a change in operating temperature; A bias generator configured to receive the temperature sensing signal and a reference voltage and vary the levels of the first and second bias voltages according to the voltage level of the temperature sensing signal; And A VBB sensor configured to receive the first and second bias voltages and the substrate bias voltage to generate a VBB pump enable signal, and to control whether to activate the VBB pump enable signal by changing a target level of the substrate bias voltage; A substrate bias voltage level sensing device of a semiconductor memory device. The method of claim 1, The bias generation unit, An adjusting unit configured to adjust the amount of current sink by adjusting a turn-on resistance by receiving the temperature sensing signal; And And a bias voltage generator configured to vary the levels of the first and second bias voltages according to the amount of current sink supplied from the controller and the operating temperature. . The method of claim 1, The temperature sensing unit, A first PMOS transistor having a gate terminal connected to a ground voltage and a source terminal receiving an external voltage; A first NMOS transistor having a gate terminal and a drain terminal connected thereto, and the drain terminal connected to a drain terminal of the first PMOS transistor; A second NMOS transistor having a gate terminal connected to a drain terminal, a drain terminal connected to a source terminal of the first NMOS transistor, and a source terminal connected to a first node; And A third NMOS transistor having a gate terminal applied with an external voltage, a source terminal connected with a ground voltage, and a drain terminal connected with the first node; wherein the temperature sensing signal is generated at the first node. A substrate bias voltage level sensing device of a semiconductor memory device. The method of claim 1, The temperature sensing unit outputs a temperature sensing signal of a voltage level that decreases when the operating temperature decreases, and outputs a temperature sensing signal of a voltage level that rises when the operating temperature increases. Level sensing device. The method of claim 2, The bias generation unit may lower the level of the first bias voltage when the operating temperature decreases and increase the level of the first bias voltage when the operating temperature increases. Sensing device. The method of claim 2, The bias generation unit may increase the level of the second bias voltage when the operating temperature decreases and decrease the level of the second bias voltage when the operating temperature increases. Sensing device. The method of claim 1, And the VBB sensor varies the target level of the substrate bias voltage according to the level change of the first and second bias voltages. The method of claim 7, wherein The VBB sensor, And lowering the substrate bias voltage target level when the operating temperature increases, and raising the substrate bias voltage target level when the operating temperature decreases.
KR1020090048627A 2009-06-02 2009-06-02 Vbb level sensor apparatus of semiconductor memory apparatus KR20100129991A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107085447B (en) * 2016-02-16 2022-02-01 中芯国际集成电路制造(上海)有限公司 Pump body structure for multi-time program memory and electronic device
EP4102505A4 (en) * 2020-08-27 2023-10-04 Changxin Memory Technologies, Inc. Memory adjustment method and adjustment system, and semiconductor device
US11886721B2 (en) 2020-08-27 2024-01-30 Changxin Memory Technologies, Inc. Method and system for adjusting memory, and semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107085447B (en) * 2016-02-16 2022-02-01 中芯国际集成电路制造(上海)有限公司 Pump body structure for multi-time program memory and electronic device
EP4102505A4 (en) * 2020-08-27 2023-10-04 Changxin Memory Technologies, Inc. Memory adjustment method and adjustment system, and semiconductor device
US11886721B2 (en) 2020-08-27 2024-01-30 Changxin Memory Technologies, Inc. Method and system for adjusting memory, and semiconductor device
US11928357B2 (en) 2020-08-27 2024-03-12 Changxin Memory Technologies, Inc. Method and system for adjusting memory, and semiconductor device

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