KR100650371B1 - Voltage generator - Google Patents

Abstract

A voltage generator is provided to minimize a standby current and an operation current and to stably drive a bit line precharge voltage or a cell plate voltage at a low power supply voltage state, by controlling the turn-on time and turn-off operation time of a voltage driving part of a final stage to be equal. A core voltage control unit(10) generates a bias voltage by using a reference voltage having a 1/2 core voltage level, and generates a pull-up/pull-down driving signal by generating a first gate voltage higher than the reference voltage by a threshold voltage, and a second gate voltage lower than the reference voltage by the threshold voltage. A voltage driving part(110) is selectively pull-up/pull-down driven according to the pull-up/pull-down driving signal to generate a bit line precharge voltage. A driving control part(100) increases the voltage level of the pull-up driving signal when the bit line precharge voltage level increases, and decreases the voltage level of the pull-down driving signal when the bit line precharge voltage level decreases, and thus controls the turn-on time and turn-off driving time of the voltage driving part to be equal.

Description

Voltage generator

1 is a circuit diagram of a conventional voltage generator.

2 is a voltage waveform diagram of a conventional voltage generator.

3 is a circuit diagram of a voltage generator according to the present invention.

4 is another embodiment of a voltage generating device according to the present invention;

5 is a voltage waveform diagram of a voltage generator according to the present invention.

6 and 7 show further embodiments of the voltage generating device according to the present invention.

8 is an operation timing diagram according to the embodiment of the present seven;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generator, and in particular, a technique for minimizing standby current and operating current while stably driving a bitline precharge voltage or a cell plate voltage in a low power supply state.

Semiconductor memory devices often have low driveability due to conditions for process changes. In this case, the driving ability of the voltage is small, which causes a large change in the internal voltage, causing malfunction of the semiconductor memory device.

In addition, as the semiconductor memory device is highly integrated, the process change becomes more severe. As the core voltage decreases, the driving ability of the bit line precharge voltage Vblp and the cell plate voltage Vcp used in the semiconductor memory device is reduced.

1 is a circuit diagram of a conventional bit line precharge voltage Vblp generator.

The conventional voltage generator includes a core voltage control means 10 and a voltage driver 20. The core voltage control means 10 includes a core voltage generator 11, a bias voltage generator 12, and a gate voltage generator 13.

Here, the core voltage generator 11 generates a 1/2 core voltage (1/2 x VCORE) serving as a reference voltage of the bit line precharge voltage Vblp or the cell plate voltage VCP. The core voltage generator 11 includes PMOS transistors P1 and P2 connected in series between a core voltage VCORE applying terminal and a ground voltage terminal and resistors R1 and R2. Therefore, a voltage divider using a self bias diode resistor and a line resistor is implemented to generate a reference voltage ref.

In this case, when the power supply voltage is applied from the outside, the power potential is generated using the voltage divider as shown in FIG. 1, but when the power supply voltage is generated internally, the reference voltage ref may be generated through the reference potential generator of another device. have.

The bias voltage generator 12 generates bias voltages pbias and nbias using the reference voltage ref. The bias voltage generator 12 includes PMOS transistors P3 to P6 and NMOS transistors N1 to N6. Here, the PMOS transistor P3 and the NMOS transistors N1 and N3 are connected in series between the core voltage VCORE applying terminal and the ground voltage terminal to allow a constant current to flow to the ground voltage VSS applying terminal. A reference voltage ref is applied to the PMOS transistor P3 through the gate terminal, and the gate terminal and the drain terminal are commonly connected to the NMOS transistors N1 and N3.

In addition, the PMOS transistor P4 and the NMOS transistors N2 and N4 are connected in series between the core voltage VCORE applying terminal and the ground voltage terminal to form a current mirror structure, and allow a constant current to flow through the core voltage VCORE applying terminal. In addition, the PMOS transistor P4 has a gate terminal and a drain terminal connected in common, and the NMOS transistor N2 has a common terminal connected with the NMOS transistor N1, and the NMOS transistor N4 has a common terminal connected with the NMOS transistor N3, and the NMOS transistor N2, The same current flows through N4.

In addition, the PMOS transistor P5 is connected between the core voltage VCORE applying terminal and the NMOS transistor N7 to form a current mirror structure in which the gate terminal is commonly connected to the PMOS transistor P4. The PMOS transistor P6 is connected between the core voltage VCORE applying stage and the NMOS transistor N8 to apply a bias voltage pbias through the gate terminal. In addition, the NMOS transistor N5 is connected between the ground voltage terminal and the PMOS transistor P7 so that the bias voltage nbias is applied through the gate terminal. The NMOS transistor N6 is connected between the ground voltage terminal and the PMOS transistor P8 so that the bias voltage nbias is applied through the gate terminal.

The gate voltage generator 13 includes NMOS transistors N7 and N8 through which the gate voltage ngate is commonly applied through the gate terminal, and PMOS transistors P7 and P8 through which the gate voltage pgate is commonly applied through the gate terminal. To achieve. The gate voltage generator 13 generates a gate voltage ngate that is a potential higher than the reference voltage ref by the threshold voltage of the NMOS transistor N7, and a gate voltage pgate that is a potential lower than the reference voltage ref by the threshold voltage of the PMOS transistor P7.

In addition, the voltage driver 20 includes a PMOS transistor P9 and an NMOS transistor N9. The PMOS transistor P9 and the NMOS transistor N9 are connected in series between the core voltage VCORE terminal and the ground voltage terminal, and pull-up / pull-down drive signals pdrv and ndrv are applied through the respective gate terminals, and the bit line precharge voltage VBLP is provided through the common drain terminal. Is output.

An operation process of a conventional voltage generator having such a configuration will be described below with reference to the voltage waveform diagram of FIG. 2.

First, the PMOS transistor P6 operates with a turn-on resistor near the threshold voltage to allow a constant current to flow. Therefore, the turn-on resistance is set large because it always operates. In addition, the NMOS transistor N8 operates rapidly in the form of a source follower as the level of the bit line precharge voltage VBLP changes.

If the bit line precharge voltage VBLP is lowered, the value of the gate voltage ngate of the NMOS transistor N8 and the bit line precharge voltage VBLP as a source become large. As a result, the current flowing through the NMOS transistor N8 flows quickly, thereby lowering the voltage level of the pull-up driving signal pdrv. Therefore, the PMOS transistor P9 is turned on to raise the level of the bit line precharge voltage VBLP.

In addition, the NMOS transistor N6 operates with a turn-on resistor near the threshold voltage to allow a constant current to flow. Therefore, the turn-on resistance is set large because it always operates. Since the PMOS transistor P8 operates in the form of a source follower as the level of the bit line precharge voltage VBLP changes, the PMOS transistor P8 operates quickly.

If the bit line precharge voltage VBLP is increased, the value of the gate voltage pgate of the PMOS transistor P8 and the bit line precharge voltage VBLP as a source is increased. As a result, the current flowing through the PMOS transistor P8 flows quickly, thereby increasing the voltage level of the pull-down driving signal ndrv. Thus, the NMOS transistor N9 is turned on to reduce the level of the bit line precharge voltage VBLP.

However, such a conventional voltage generator is to prevent the driving capability from being reduced when the internal power supply potential is low, and applies a slim low threshold voltage to the voltage driver 20 to increase the driving capability of the final stage. PMOS transistor P9 and NMOS transistor N9 are provided. In this case, however, the operating characteristics at the time of active and read / write are improved, while the off leakage current flows in the precharge state.

That is, when the threshold voltage of the PMOS transistor P9 is slightly lowered from the target value, the pre-charge, that is, the standby current is generated by the large off leakage current. This results in non-compliance, especially in low power or mobile products where standby current is a key issue.

Therefore, when the threshold voltages of the PMOS transistor P9 and the NMOS transistor N9 are lowered to secure the operating area of the final driver stage, the driving capability characteristics can be improved, but there is a problem that causes a huge loss in terms of standby current.

In addition, when the bit line precharge voltage VBLP is not stable or is operated in the standby mode, the PMOS transistor P8 operates in the form of a source follower so that the timing of turning on the voltage driver 20 is faster. As a result, only a minimum current is supplied to reduce the standby current, thereby slowing down the time when the voltage driver 20 is turned off.

Accordingly, there is a problem in that a time for turning on / off the final driver stage is mismatched so that the PMOS transistor P8 and the NMOS transistor N9 are turned on at the same time, so that a direct current may occur.

In this case, in addition to the standby current, a direct current path is formed in the operation mode as shown in FIG. 2, so that a ringing current is generated in the standby mode and the operation mode, thereby adversely affecting the chip driving capability.

The present invention has been made to solve the above problems, and in particular, by using a PMOS transistor and an NMOS transistor having a low threshold voltage in the driver stage, by controlling the turn-on / turn-off operation time of the voltage driver of the final stage in the same manner The objective is to minimize the standby current (IDD2P) and the operating current while driving the bit line precharge voltage or cell plate voltage stably under low power supply.

In order to achieve the above object, the voltage generator of the present invention generates a bias voltage using a reference voltage having a 1/2 core voltage level, and the threshold is higher than the reference voltage and the first gate voltage higher than the reference voltage. Core voltage control means for generating a pull-up / pull-down driving signal by generating a second gate voltage as low as the voltage; A voltage driver configured to selectively pull up / pull down according to a pull up / pull down driving signal to generate a bit line precharge voltage; And increasing the voltage level of the pull-up driving signal when the bit line precharge voltage level rises, and decreasing the voltage level of the pull-down driving signal when the bit line precharge voltage level decreases to equalize the turn-on / turn-off driving time of the voltage driver. It characterized in that it comprises a drive control unit for controlling.

In addition, the present invention generates a bias voltage using a reference voltage having a 1/2 core voltage level, and generates a first gate voltage higher by a threshold voltage than the reference voltage and a second gate voltage lower by a threshold voltage than the reference voltage. Core voltage control means for generating a pull-up / pull-down drive signal; A voltage driver configured to selectively pull up / pull down according to a pull up / pull down driving signal to generate a bit line precharge voltage; And an output controller configured to selectively control a bulk bias voltage level of the voltage driver according to a state of an active signal activated in the active operation mode.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 is a circuit diagram of a voltage generator according to the present invention.

The present invention includes a core voltage control means 10, a drive control unit 100 and the voltage driver 110. Here, since the configuration of the core voltage control means 10 is the same as the conventional core voltage control means 10 will be described with the same reference numerals, description of the detailed configuration and operation thereof will be omitted.

In detail, the driving controller 100 includes PMOS transistors P10 to P12 and NMOS transistors N10 to N12. The PMOS transistor P10 is connected between the core voltage VCORE applying terminal and the NMOS transistor N10 so that the gate terminal is commonly connected to the PMOS transistor P11. The PMOS transistor P11 is connected between the core voltage VCORE applying terminal and the output node A so that the gate terminal is commonly connected to the PMOS transistor P10.

The NMOS transistor N10 is connected between the PMOS transistor P10 and the output terminal of the bit line precharge voltage VBLP to receive a gate voltage ngate through the gate terminal. The PMOS transistor P12 is connected between the NMOS transistor N11 and the output terminal of the bit line precharge voltage VBLP so that the gate voltage pgate is applied through the gate terminal.

In addition, the NMOS transistor N11 is connected between the ground voltage VSS applying terminal and the PMOS transistor P12 so that the gate terminal is commonly connected to the NMOS transistor N12. In addition, the NMOS transistor N12 is connected between the ground voltage VSS applying end and the output node (B) so that the gate terminal is commonly connected to the NMOS transistor N11.

The voltage driver 110 includes a PMOS transistor P13 and an NMOS transistor N13. The PMOS transistor P13 and the NMOS transistor N13 are connected in series between the core voltage VCORE terminal and the ground voltage VSS terminal, and pull-up / pull-down driving signals pdrv and ndrv are applied through the respective gate terminals, and bit line precharge is performed through the common drain terminal. The voltage VBLP is output.

Referring to the operation of the present invention having such a configuration as follows.

First, the bias voltage pbias is a level signal near the threshold voltage Vt of the core voltage VCORE-PMOS transistor P6. The bias voltage pbias supplies a constant gate voltage to the PMOS transistor P6 to allow a constant current to flow. Further, the bias voltage nbias is a level signal near the threshold voltage Vt of the ground voltage VSS + NMOS transistor N6. This bias voltage nbias supplies a constant gate voltage to the NMOS transistor N6 to allow a constant current to flow.

The NMOS transistor N8 operates as the bit line precharge voltage VBLP changes as a source using the bit line precharge voltage VBLP as a source. The PMOS transistor P8 operates quickly as the bit line precharge voltage VBLP changes with the bit line precharge voltage VBLP as a source. That is, both the NMOS transistor N8 and the PMOS transistor P8, which are source follower structures, operate quickly according to the level change of the bit line precharge voltage VBLP to turn on / off the PMOS transistors P13 and NMOS transistor N13.

However, constant current flows in the NMOS transistor N8 and the PMOS transistor P8 so that it takes a long time to turn off the final output stage PMOS transistor P13 and NMOS transistor N13.

Accordingly, in the present invention, when the bit line precharge voltage VBLP rises, the gate source voltage vgs of the PMOS transistor P8 becomes large. Accordingly, the voltage level of the pull-down driving signal ndrv is increased to turn on the NMOS transistor N13 to decrease the level of the elevated bit line precharge voltage VBLP.

At this time, the gate source voltage vgs of the NMOS transistor N10, which is the source follower structure, becomes small, and the node ap becomes the threshold voltage Vt level of the core voltage VCORE-NMOS transistor N10. The gate voltage levels of the PMOS transistors P10 and P11 through which a constant current flows according to the voltage of the node ap are controlled to rapidly raise the voltage level of the node A to the core voltage VCORE level so that the current path is not formed.

In addition, the PMOS transistor P12, which is a source follower structure, is turned on faster, resulting in an increase in the voltage level of the node ac. The NMOS transistors N11 and N12 are turned on according to the voltage of the node an to reduce the voltage level of the node B so that no current path is formed.

On the other hand, when the bit line precharge voltage VBLP decreases, the gate source voltage vgs of the NMOS transistor N8 becomes large. Accordingly, the voltage level of the pull-up driving signal pdrv is decreased to turn on the PMOS transistor P13 to raise the level of the reduced bit line precharge voltage VBLP.

At this time, the gate source voltage vgs of the PMOS transistor P12, which is the source follower structure, becomes small, and the node an becomes the threshold voltage Vt level of the ground voltage VSS + PMOS transistor P10. Accordingly, the gate voltage levels of the NMOS transistors N11 and N12 through which a constant current flows according to the voltage of the node an are controlled to quickly reduce the voltage level of the node B to the ground voltage VSS level so that the current path is not formed.

In addition, the NMOS transistor N10, which is a source follower structure, is turned on faster, resulting in a decrease in the voltage level at node ap. The PMOS transistors P10 and P11 are turned on according to the voltage of the node ap to raise the voltage level of the node A so that the current path is not formed.

4 is another embodiment of a voltage generator according to the present invention.

The present invention includes a core voltage control means 10, a drive control unit 200 and the voltage driver 210. Here, since the configuration of the core voltage control means 10 is the same as the conventional core voltage control means 10 will be described with the same reference numerals, description of the detailed configuration and operation thereof will be omitted.

In detail, the driving controller 200 includes PMOS transistors P14 to P17, NMOS transistors N14 to N17, and resistors R3 and R4. The PMOS transistor P14 is connected between the core voltage VCORE applying terminal and the NMOS transistor N14 so that the gate terminal is commonly connected to the PMOS transistor P15. The PMOS transistor P15 is connected between the core voltage VCORE applying terminal and the low R3 so that the gate terminal is commonly connected to the PMOS transistor P14.

The NMOS transistor N14 is connected between the PMOS transistor P14 and the output terminal of the bit line precharge voltage VBLP so that the gate voltage ngate is applied through the gate terminal. Resistor R3 is connected between PMOS transistor P15 and ground voltage VSS. The NMOS transistor N15 is connected between the node D and the ground voltage VSS applying end, and a gate terminal thereof is connected between the resistor R3.

In addition, the PMOS transistor P16 is connected between the NMOS transistor N16 and the output terminal of the bit line precharge voltage VBLP so that the gate voltage pgate is applied through the gate terminal. The PMOS transistor P17 is connected between the core voltage VCORE applying terminal and the node C so that the gate terminal is connected to the resistor R4. Resistor R4 is connected between core voltage VCORE applied stage and NMOS transistor N17.

In addition, the NMOS transistor N16 is connected between the ground voltage VSS applying terminal and the PMOS transistor P16 so that the gate terminal is commonly connected to the NMOS transistor N17. The NMOS transistor N17 is connected between the ground voltage VSS applying terminal and the resistor R4 so that the gate terminal is commonly connected to the NMOS transistor N16.

In addition, the voltage driver 210 includes a PMOS transistor P18 and an NMOS transistor N18. PMOS transistor P18 and NMOS transistor N18 are connected in series between core voltage VCORE terminal and ground voltage VSS terminal, and pull-up / pull-down driving signals pdrv and ndrv are applied through each gate terminal and bit line precharge through common drain terminal. The voltage VBLP is output.

Referring to the operation of the present invention having such a configuration as follows.

First, when the bit line precharge voltage VBLP rises, the gate source voltage vgs of the PMOS transistor P8 becomes large. Accordingly, the voltage level of the pull-down driving signal ndrv is increased to turn on the NMOS transistor N18 to decrease the level of the elevated bit line precharge voltage VBLP.

At this time, the PMOS transistor P16, which is the source follower structure, is quickly turned on to increase the voltage level of the node bn. The NNOS transistors N16 and N17 are turned on according to the voltage level of the node bn to turn on the PMOS transistor P17. Accordingly, the voltage level of the node C rises rapidly to the core voltage VCORE level so that no current path is formed.

In addition, the NMOS transistor N14, which is a source follower structure, is kept turned off because the gate source voltage vgs becomes small. At this time, the NMOS transistor N14 increases the voltage level of the node bp through a slight bootstrapping action. Accordingly, the PMOS transistors P14 and P15 are kept in the off state to turn off the NMOS transistor N15 so that the current path is interrupted.

On the other hand, when the bit line precharge voltage VBLP decreases, the gate source voltage vgs of the NMOS transistor N8 becomes large. Accordingly, the voltage level of the pull-up driving signal pdrv is decreased to turn on the PMOS transistor P18 to raise the level of the reduced bit line precharge voltage VBLP.

At this time, the gate source voltage vgs of the PMOS transistor P16, which is a source follower structure, becomes small, and a voltage drop occurs at the node bn. Accordingly, the NMOS transistors N16 and N17 are turned on to increase the gate voltage of the PMOS transistor P17, thereby increasing the voltage level of the node C. Accordingly, the current path is not formed through the node C regardless of the voltage level of the bit line precharge voltage VBLP.

In addition, the NMOS transistor N14, which is the source follower structure, is turned on faster, resulting in a reduced voltage level at the node bp. The PMOS transistors P14 and P15 are turned on according to the voltage of the node bp to increase the gate voltage of the NMOS transistor N15. Accordingly, the voltage level of the node D is reduced to the ground voltage VSS level so that no current path is formed.

5 is a voltage waveform diagram of the present invention according to the embodiment of FIGS. 3 and 4. As shown in the voltage waveform diagram of FIG. 5, the current path is not formed between the bit line precharge voltage VBLP, the pull-up driving signal pdrv, and the pull-down driving signal ndrv regardless of whether it is in a standby state or an operation mode state. To improve the driving ability of the chip.

6 is another embodiment of a voltage generating device according to the present invention.

The present invention includes a core voltage control means 10, the drive control unit 300 and the voltage driver 310. Here, since the configuration of the core voltage control means 10 is the same as the conventional core voltage control means 10 will be described with the same reference numerals, description of the detailed configuration and operation thereof will be omitted.

In detail, the driving controller 300 includes an NMOS transistor N19 and a PMOS transistor P19. Here, the NMOS transistor N19 and the PMOS transistor P19 are connected in series between the core voltage VCORE supply terminal and the ground voltage VSS supply terminal, so that gate voltages ngate and pgate are applied through respective gate terminals, and non-line precharge voltages are provided through the common drain terminal. VBLP is output.

In addition, the voltage driver 310 includes a PMOS transistor P20 and an NMOS transistor N20. PMOS transistor P20 and NMOS transistor N20 are connected in series between core voltage VCORE terminal and ground voltage VSS terminal, and pull-up / pull-down drive signals pdrv and ndrv are applied through each gate terminal and bit line precharge through common drain terminal. The voltage VBLP is output.

The present invention having such a configuration uses an NMOS transistor N19 having a gate voltage ngate as an input and a bit line precharge voltage VBLP as a source, and a PMOS transistor P19 having a gate voltage pgate as a source and a bit line precharge voltage VBLP as a source. By blocking the direct current path through it to improve the driving capability of the voltage driver 310.

7 is yet another embodiment of a voltage generator according to the present invention.

The present invention includes a core voltage control means 10, the voltage driver 410 and the output control unit 410. Here, since the configuration of the core voltage control means 10 is the same as the conventional core voltage control means 10 will be described with the same reference numerals, description of the detailed configuration and operation thereof will be omitted.

The voltage driver 410 includes a PMOS transistor P21 and an NMOS transistor N21. The PMOS transistor P21 and the NMOS transistor N21 are connected in series between the core voltage VCORE terminal and the ground voltage VSS terminal, and pull-up / pull-down driving signals pdrv and ndrv are applied through the respective gate terminals, and bit line precharge is performed through the common drain terminal. The voltage VBLP is output.

In addition, the output control unit 410 includes transmission gates T1 to T4. Here, the transfer gate T1 outputs the core voltage VCORE to the bulk of the PMOS transistor P21 in accordance with the state of the control signals aa and bb. Then, the transfer gate T2 outputs the power supply voltage VDD to the bulk of the PMOS transistor P21 in accordance with the state of the control signals aa and bb.

Then, the transfer gate T3 outputs the ground voltage VSS to the bulk of the NMOS transistor N21 in accordance with the state of the control signals aa and bb. Then, the transfer gate T4 outputs the back bias voltage VBB to the bulk of the NMOS transistor N21 in accordance with the state of the control signals aa and bb.

Here, the control signal aa is a signal in which the active signal act is inverted by the inverter IV1, and the control signal bb is a signal in which the control signal aa is inverted by the inverter IV2. The control signals aa are applied to the transfer gates T1 and T3 through the PMOS gate, and the control signal bb is applied through the NMOS gate. In addition, the control signals bb are applied to the transfer gates T2 and T4 through the PMOS gate and the control signal aa is applied through the NMOS gate.

An operation process of the present invention having such a configuration will be described below with reference to the operation timing diagram of FIG. 8.

First, when the active signal act is activated in the active operation mode, the control signal aa becomes low and the control signal bb becomes high. Accordingly, the transfer gates T1 and T3 are turned on to apply the core voltage VCORE to the bulk of the PMOS transistor P21, and the ground voltage VSS to the bulk of the NMOS transistor N21. Therefore, the threshold voltages of the PMOS transistor P21 and the NMOS transistor N21 are lowered in the active operation mode, thereby improving the driving capability.

On the other hand, when the active signal act is deactivated in the standby mode other than the active operation mode, the control signal aa becomes high and the control signal bb becomes low. Accordingly, the transfer gates T2 and T4 are turned on to apply the power supply voltage VDD to the bulk of the PMOS transistor P21 and the back bias voltage VBB to the bulk of the NMOS transistor N21. Therefore, in the standby mode, the threshold voltages of the PMOS transistor P21 and the NMOS transistor N21 are increased to block the leakage current path.

That is, the present invention controls the bulk bias of the PMOS transistor P21 to which the core voltage VCORE is applied as a source, and takes self-biasing to lower the threshold voltage Vt when active. In the standby mode, the back bias voltage VBB is applied to the NMOS transistor N21 of the voltage driver 400 to reduce the leakage current, that is, increase the threshold voltage Vt.

As described above, the present invention can minimize the standby current IDD2P and the operating current while stably driving the bit line precharge voltage or the cell plate voltage in a low power supply state with a low core voltage level.

In addition, the present invention provides an effect of improving the reliability of the chip by controlling the threshold voltage of the voltage driver to increase the driving capability in the active mode and to block the path of leakage current in the standby mode.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (23)

A bias voltage is generated using a reference voltage having a 1/2 core voltage level, and a pull-up / pull-down is generated by generating a first gate voltage higher by the threshold voltage than the reference voltage and a second gate voltage lower by the threshold voltage than the reference voltage. Core voltage control means for generating a drive signal; A voltage driver configured to selectively pull up / pull down according to the pull up / pull down driving signal to generate a bit line precharge voltage; And When the bit line precharge voltage level rises, the voltage level of the pull-up driving signal is increased, and when the bit line precharge voltage level decreases, the voltage level of the pull-down drive signal is decreased to turn on / turn off driving of the voltage driver. And a drive controller for controlling the time equally. The method of claim 1, wherein the voltage driver A pull-down driving unit driven according to a voltage level of the pull-down driving signal when the bit line precharge voltage level rises to pull down the bit line precharge voltage level; And And a pull-up driving unit driven according to the voltage level of the pull-up driving signal when the bit line precharge voltage level decreases to pull up the bit line precharge voltage level. The method of claim 1 or 2, wherein the drive control unit A first driving device configured to supply the bit line precharge voltage to a pull-up node according to the first gate voltage level; A first driver configured to supply a core voltage to an application node of the pull-up driving signal according to the voltage level of the pull-up node; A second driving device supplying the bit line precharge voltage to a pull-down node according to the second gate voltage level; And And a second driver configured to supply a ground voltage to an application node of the pull-down driving signal according to the voltage level of the pull-down node. 4. The first driving device of claim 3, wherein the first driving device comprises a first NMOS transistor connected between the pull-up node and an output node of the bit line precharge voltage to which the first gate voltage is applied through a gate terminal. Voltage generator. The method of claim 3, wherein the first driving unit And a first PMOS transistor and a second PMOS transistor connected between an application node of the core voltage, an output node of the first driving device, and an output node of the bit line precharge voltage, respectively, and a gate terminal of which is commonly connected to the pull-up node. Voltage generator. 4. The second driving device of claim 3, wherein the second driving device comprises a third PMOS transistor connected to an output node between the pull-down node and the bit line precharge voltage and to which the second gate voltage is applied through a gate terminal. Voltage generator. The method of claim 3, wherein the second driving unit And a second NMOS transistor and a third NMOS transistor connected between a ground voltage terminal and an output node of the second driving device and the bit line precharge voltage, respectively, and a gate terminal of which is commonly connected to the pull-down node. The method of claim 1 or 2, wherein the drive control unit A third driving element configured to supply the bit line precharge voltage to a pull-up node according to the first gate voltage level; A third driver supplying a core voltage according to the voltage level of the pull-up node; A fourth driver supplying a ground voltage to the node to which the pull-down driving signal is applied according to the output of the third driver; A fourth driving device configured to supply the bit line precharge voltage to a pull-down node according to the second gate voltage level; A fifth driver supplying a ground voltage according to the voltage level of the pull-down node; And And a sixth driver configured to supply a core voltage to an application node of the pull-up driving signal according to the output of the fifth driver. 10. The transistor of claim 8, wherein the third driving device comprises a fourth NMOS transistor connected between the pull-up node and an output node of the bit line precharge voltage to which the first gate voltage is applied through a gate terminal. Voltage generator. The method of claim 8, wherein the third driving unit And a fourth PMOS transistor and a fifth PMOS transistor connected between the node for applying the core voltage, the third driver, and the fourth driver, respectively, and a gate terminal of which is commonly connected to the pull-up node. The method of claim 8, wherein the fourth driving unit A first resistor connected between the output terminal of the third driver and a ground voltage terminal; And And a fifth NMOS transistor connected between an application node of the pull-down driving signal and the ground voltage terminal, and a gate terminal of which is connected to the first resistor. 10. The method of claim 8, wherein the fourth driving device comprises a fifth PMOS transistor connected between the pull-up node and the output node of the bit line precharge voltage to apply the second gate voltage through a gate terminal. Voltage generator. The method of claim 8, wherein the fifth driving unit And a sixth NMOS transistor and a seventh NMOS transistor connected between a ground voltage terminal, the fourth driving device, and the fifth driving unit, respectively, and a gate terminal of which is commonly connected to the pull-down node. The method of claim 8, wherein the sixth drive unit A second resistor connected between an output terminal of the fifth driver and a core voltage application terminal; And And a sixth PMOS transistor connected between an application node of the pull-up driving signal and the core voltage application terminal and having a gate terminal connected to the second resistor. The method of claim 1 or 2, wherein the drive control unit A fifth driving device connected in series between a core voltage applying terminal and a ground voltage terminal to which the first gate voltage and the second gate voltage are applied through respective gate terminals, and the bit line precharge voltage is applied through a common drain terminal; And a sixth driving device. The voltage generating device of claim 15, wherein the fifth driving device comprises an eighth NMOS transistor. 16. The voltage generating device of claim 15, wherein the sixth driving device comprises a seventh PMOS transistor. A bias voltage is generated using a reference voltage having a 1/2 core voltage level, and a pull-up / pull-down is generated by generating a first gate voltage higher by the threshold voltage than the reference voltage and a second gate voltage lower by the threshold voltage than the reference voltage. Core voltage control means for generating a drive signal; A voltage driver configured to selectively pull up / pull down according to the pull up / pull down driving signal to generate a bit line precharge voltage; And And an output controller configured to selectively control a bulk bias voltage level of the voltage driver according to a state of an active signal activated in an active operation mode. The method of claim 18, wherein the voltage driver A pull-down driving unit driven according to a voltage level of the pull-down driving signal when the bit line precharge voltage level rises to pull down the bit line precharge voltage level; And And a pull-up driving unit driven according to the voltage level of the pull-up driving signal when the bit line precharge voltage level decreases to pull up the bit line precharge voltage level. The method of claim 19, wherein the output control unit And controlling the bulk bias voltage level of the pull-up driver to a self bias level in the active operation mode, and increasing the bulk bias voltage level in the standby mode. The method of claim 20, wherein the output control unit A first transfer gate configured to supply a core voltage to the bulk of the pull-up driver when the active signal is activated; And And a second transfer gate configured to supply a power supply voltage to the bulk of the pull-up driving unit when the active signal is inactivated. The method of claim 19, wherein the output control unit And reducing the bulk bias voltage level of the pull-down driver in the active operation mode and increasing the bulk bias voltage level in the standby mode. The method of claim 22, wherein the output control unit A third transfer gate configured to supply a ground voltage to the bulk of the pull-down driving unit when the active signal is activated; And And a fourth transfer gate configured to supply a back bias voltage to the bulk of the pull-down driver when the active signal is inactivated.

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