JP2012109018A - Voltage generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably drive bit line pre-charge voltage or cell plate voltage in a low power supply voltage state and to minimize standby current IDD2P and operation current.SOLUTION: A voltage generator of a semiconductor memory element includes: bias signal generation means that uses reference voltage on a half level of power supply voltage to generate bias signals of different levels; drive signal generation means that generates a pull-down drive signal in response to a voltage level at an output end; voltage drive means that drives the output end in response to the drive signal; drive signal generation means that generates a pull-up drive signal/pull-down drive signal according to the voltage level at the output end; a pull-up PMOS transistor/pull-down NMOS transistor that pull-up drives/pull-down drives the output end in response to the pull-up drive signal/pull-down drive signal; first multiplexing means; and second multiplexing means.

Description

  The present invention relates to a voltage generator, and more particularly, to a technique for stably driving a bit line precharge voltage or a cell plate voltage in a low power supply voltage state and minimizing standby current and operating current.

  In many cases, the semiconductor memory device has a low driving capability depending on a process change. In such a case, since the voltage driving capability is weak, a large change is caused in the internal voltage, causing an error in the semiconductor memory device.

  Further, as the semiconductor memory device is highly integrated, the change in the process gradually increases, so that the core voltage gradually decreases, and the driving capability of the bit line precharge voltage VBLP and the cell plate voltage VCP used in the semiconductor memory device also increases. It will be reduced.

  FIG. 1 is a circuit diagram of a conventional bit line precharge voltage VBLP generator.

  The conventional voltage generator includes a core voltage control unit 10 and a voltage driving unit 20. The core voltage control means 10 includes a core voltage generator 11, a bias voltage generator 12, and a gate voltage generator 13.

  Here, the core voltage generator 11 generates a ½ core voltage (½ × VCORE) which is a reference voltage of the bit line precharge voltage VBLP or the cell plate voltage VCP. The core voltage generator 11 includes PMOS transistors P1 and P2 and resistors R1 and R2 connected in series between the application terminal of the core voltage VCORE and the ground voltage stage. Accordingly, the voltage divider using the self-biased diode resistance and the line resistance is realized to generate the reference voltage REF.

  At this time, when the power supply voltage is applied from the outside, the power supply potential is generated using a voltage divider as shown in FIG. 1, but when the power supply voltage is generated internally, the reference potential generating unit of another device is The reference voltage REF can be generated via

  The bias voltage generator 12 generates the bias voltages PBIAS and NBIAS using the reference voltage REF. The bias voltage generator 12 includes PMOS transistors P3 to P6 and NMOS transistors N1 to N6. Here, the PMOS transistor P3 and the NMOS transistors N1 and N3 are connected in series between the application terminal of the core voltage VCORE and the ground voltage stage so that a constant current flows to the application terminal of the ground voltage VSS. A reference voltage REF is applied to the PMOS transistor P3 via the gate terminal, and the gate terminals and drain terminals of the NMOS transistors N1 and N3 are connected in common.

  The PMOS transistor P4 and the NMOS transistors N2 and N4 are connected in series between the core voltage VCORE application terminal and the ground voltage stage so as to have a current mirror structure so that a constant current flows to the core voltage VCORE application terminal. The PMOS transistor P4 commonly connects the gate terminal and the drain terminal, the NMOS transistor N2 commonly connects the NMOS transistor N1 and the gate terminal, and the NMOS transistor N4 commonly connects the NMOS transistor N3 and the gate terminal. Thus, the same current flows through the NMOS transistors N2 and N4.

  The PMOS transistor P5 is connected between the application terminal of the core voltage VCORE and the NMOS transistor N7, and has a gate terminal commonly connected to the PMOS transistor P4 to form a current mirror structure. The PMOS transistor P6 is connected between the application terminal of the core voltage VCORE and the NMOS transistor N8, and the bias voltage PBIAS is applied through the gate terminal. The NMOS transistor N5 is connected between the ground voltage stage and the PMOS transistor P7, and a bias voltage NBIAS is applied through the gate terminal. The NMOS transistor N6 is connected between the ground voltage stage and the PMOS transistor P8, and a bias voltage NBIAS is applied via a gate terminal.

  The gate voltage generator 13 includes NMOS transistors N7 and N8 to which a gate voltage NGATE is commonly applied via a gate terminal, and PMOS transistors P7 and P8 to which a gate voltage PGATE is commonly applied via a gate terminal. It has a current mirror structure. The gate voltage generator 13 generates a potential phosphorus gate voltage NGATE that is higher than the reference voltage REF by the threshold voltage of the NMOS transistor N7, and a gate voltage PGATE that is lower than the reference voltage REF by the threshold voltage of the PMOS transistor P7. .

  The voltage driving means 20 includes a PMOS transistor P9 and an NMOS transistor N9. The PMOS transistor P9 and the NMOS transistor N9 are connected in series between the application terminal of the core voltage VCORE and the ground voltage stage, and the pull-up drive signal PDRV and the pull-down drive signal NDRV are applied through the respective gate terminals, and the common drain terminal The bit line precharge voltage VBLP is output via

  The operation process of the conventional voltage generator having such a configuration will be described with reference to the voltage timing chart of FIG.

  First, the PMOS transistor P6 is operated by a turn-on resistance around the threshold voltage so that a constant current flows. Therefore, since it always operates, the turn-on resistance is set large. Since the NMOS transistor N8 operates in a source follower configuration as the level of the bit line precharge voltage VBLP changes, the NMOS transistor N8 operates faster.

If the bit line precharge voltage VBLP is lowered, the values of the gate voltage NGATE of the NMOS transistor N8 and the bit line precharge voltage VBLP as the source are increased. Therefore, the current flowing through the NMOS transistor N8 flows faster, and the voltage level of the pull-up drive signal PDRV is lowered. Accordingly, the PMOS transistor P9 is turned on to raise the level of the bit line precharge voltage VBLP.
The NMOS transistor N6 operates with a turn-on resistance around the threshold voltage so that a constant current flows. Therefore, since it always operates, the turn-on resistance is set large. Since the PMOS transistor P8 operates in a source follower configuration as the level of the bit line precharge voltage VBLP changes, it operates faster.

  If the bit line precharge voltage VBLP increases, the values of the gate voltage PGATE of the PMOS transistor P8 and the source phosphorus bit line precharge voltage VBLP increase. Therefore, the current flowing through the PMOS transistor P8 flows quickly, and the voltage level of the pull-down drive signal NDRV increases. Accordingly, the NMOS transistor N9 is turned on to reduce the level of the bit line precharge voltage VBLP.

  However, such a conventional voltage generator is designed to prevent the driving capability from being reduced when the internal power supply potential is low. Low) includes a PMOS transistor P9 having a threshold voltage and an NMOS transistor N9. However, in such a case, the operating characteristics during active and reading / writing are improved, but there is a problem that a large amount of off-leakage current flows in the precharged state.

  That is, when the threshold voltage of the PMOS transistor P9 becomes slightly lower than the target value, a precharge, that is, a standby current is generated due to a large amount of off-leakage current. Therefore, it can cause results that do not meet specifications, and can cause fatal errors, especially in low power or mobile products where standby current is an important requirement.

  Accordingly, when the threshold voltage of the PMOS transistor P9 and the NMOS transistor N9 is lowered in order to secure the operation region of the final driver end, the driving capability characteristic can be improved, but a large loss is caused in terms of standby current. There's a problem.

  In the standby mode, if the bit line precharge voltage VBLP is not stable or starts to operate, the PMOS transistor P8 operates in a source follower form. In order to reduce the standby current, the time point when the voltage driving means 20 is turned off by supplying only a minimum current is delayed.

  Therefore, there is a case in which the time for turning on / off the final driver end is mismatched, and the PMOS transistor P8 and the NMOS transistor N9 are turned on at the same time, so that a direct current can be generated.

  In such a case, not only the standby current but also a direct current path is formed as shown in FIG. 2 in the operation operation, and a signal (ringing) current is generated in the standby mode and the operation mode. There is a problem of adversely affecting.

JP 2002-056688

  The present invention has been made to solve the above-described problems, and its object is to use a PMOS transistor and an NMOS transistor having a low threshold voltage at the driver end to turn on the voltage driving means at the final end. / The turn-off operation time is controlled to be the same, the bit line precharge voltage or the cell plate voltage is stably driven in the low power supply voltage state, and the standby current IDD2P and the operation current can be minimized. There is in doing so.

  To achieve the above object, the present invention generates a first bias signal, a second bias signal, a third bias signal, and a fourth bias signal having different levels by using a reference voltage having a half level of the power supply voltage. Bias signal generating means (the first bias signal is higher by a predetermined level than the reference voltage, and the second bias signal is lower by a predetermined level than the reference voltage), and the first A bias and a third bias signal are applied to generate the pull-up driving signal in response to a voltage level of the output terminal-half voltage terminal-, and the sixth bias signal and the fourth bias signal are applied to the output terminal. Drive signal generating means for generating the pull-down drive signal in response to a voltage level, and responding to the pull-up drive signal and the pull-down drive signal In response to the voltage driving means for pulling up / down driving the output terminal, the first bias signal and the second bias signal, and the voltage level of the output terminal, the voltage level of the output terminal is higher than the reference voltage And an auxiliary drive control means for deactivating the pull-up drive signal and deactivating the pull-down drive signal in a section where the voltage level of the output terminal is lower than the reference voltage.

According to another aspect of the present invention, there is provided bias signal generating means for generating first to fourth bias signals having different levels using a reference voltage having a half level of a power supply voltage (the first bias signal is The second bias signal is higher than the reference voltage by a predetermined level, and the second bias signal is lower by the predetermined level than the reference voltage. The first and third bias signals are applied to the output terminal (half The pull-up driving signal is generated in response to the voltage level at the voltage terminal, and the pull-down driving signal is generated in response to the voltage level at the output terminal by applying the sixth bias and the fourth bias signal. Signal generating means;
In response to the pull-up driving signal and the pull-down driving signal, voltage driving means for pull-up / pull-down driving the output terminal, in response to the first bias and second bias signals, and the voltage level of the output terminal. The output terminal is supplementally pulled up in a section where the voltage level of the output terminal is lower than the reference voltage, and the output terminal is supplementally pulled down in a section where the voltage level of the output terminal is higher than the reference voltage. And auxiliary drive means.

  Still another aspect of the present invention provides bias signal generating means for generating first to fourth bias signals having different levels using a reference voltage having a half level of a power supply voltage (the first bias signal is the reference voltage). The second bias signal is higher by a predetermined level than the voltage, and the second bias signal is lower than the predetermined level by the reference voltage), and the first and third bias signals are applied to the output terminal ( The pull-up drive signal is generated in response to the voltage level of the half voltage terminal, and the pull-down drive signal is generated in response to the voltage level of the output terminal by applying the sixth bias and the fourth bias signal. Drive signal generating means; a pull-up PMOS transistor for pull-up driving the output terminal in response to the pull-up drive signal; A pull-down NMOS transistor that pulls down the output terminal in response to a drive signal, and a substrate bias voltage of the pull-up PMOS transistor in response to an active signal is selectively applied as the power supply voltage or a voltage higher than the power supply voltage. And a second multiplexing means for selectively applying a ground voltage or a voltage lower than the ground voltage as a substrate bias voltage of the pull-down NMOS transistor in response to the active signal. Features.

  That is, the first invention uses a reference voltage having a half level of the power supply voltage and generates a first bias signal, a second bias signal, a third bias signal, and a fourth bias signal having different levels. A signal generating means (the first bias signal is higher than the reference voltage by a predetermined level, and the second bias signal is lower than the predetermined level by the reference voltage), the first bias and A third bias signal is applied to generate a pull-up driving signal in response to a voltage level at the output terminal (half voltage terminal), and the sixth bias signal and the fourth bias signal are applied to the voltage level at the output terminal. Drive signal generating means for generating a pull-down drive signal in response; and the output terminal in response to the pull-up drive signal and the pull-down drive signal In response to voltage drive means for pull-up / pull-down drive, the first bias signal and the second bias signal, and the voltage level of the output terminal, the pull-up drive is performed in a section where the voltage level of the output terminal is higher than the reference voltage. A voltage generator for a semiconductor memory device, comprising: auxiliary drive control means for deactivating a signal and deactivating the pull-down drive signal in a section where the voltage level of the output terminal is lower than the reference voltage. provide.

  As a second invention, according to the first invention, the voltage driving means has a source connected to a power supply voltage terminal, a drain connected to the output terminal, and a pull-up using the pull-up driving signal as a gate input. A voltage generator for a semiconductor memory device, comprising: a PMOS transistor; and a pull-down NMOS transistor having a source connected to a ground voltage terminal, a drain connected to the output terminal, and a gate input of the pull-down drive signal. I will provide a.

  As a third invention, according to the second invention, the drive signal generating means is connected between the power supply voltage terminal and the pull-up drive signal terminal, and the third bias signal (PMOS is applied from the power supply voltage). A first PMOS transistor having a gate voltage as a gate input, and a first NMOS transistor connected between the pull-up drive signal terminal and the output terminal and having the first bias signal as a gate input And a second NMOS transistor connected between the ground voltage terminal and the pull-down drive signal terminal, and having the gate input of the fourth bias signal-the level of which the NMOS threshold voltage is higher than the ground voltage- A second PMOS transistor connected between the pull-down drive signal terminal and the output terminal and having the second bias signal as a gate input; To provide a voltage generator of a semiconductor memory device, characterized in that the.

  As a fourth invention, according to the third invention, the auxiliary drive control means includes a third NMOS transistor having a source connected to the output terminal and the gate input of the first bias signal, and a power supply voltage terminal. A third PMOS transistor having a source connected, a gate and a drain commonly connected to a drain of the third NMOS transistor, a source connected to the power supply voltage end, a drain connected to the pull-up drive signal end, and a third PMOS A fourth PMOS transistor having a gate connected to the drain of the transistor; a fifth PMOS transistor having a source connected to the output terminal; the second bias signal as a gate input; and a source connected to the ground voltage terminal; A fourth transistor in which the gate and drain are commonly connected to the drain of the 5 PMOS transistor A semiconductor comprising: a MOS transistor; and a fifth NMOS transistor having a source connected to the ground voltage terminal, a drain connected to the pull-down drive signal terminal, and a gate connected to the drain of the fourth NMOS transistor. A voltage generator for a memory device is provided.

  As a fifth invention, according to the third invention, the auxiliary drive control means includes a third NMOS transistor having a source connected to the output terminal and the gate input of the first bias signal, and a power supply voltage terminal. A third PMOS transistor having a source connected, a gate and a drain commonly connected to the drain of the third NMOS transistor, and a fourth PMOS transistor having a source connected to the power supply voltage terminal and a gate connected to the drain of the third PMOS transistor; A first resistor connected between the drain of the fourth PMOS transistor and the ground voltage terminal; a source connected to the ground voltage terminal; a drain connected to the pull-down drive signal terminal; and the fourth PMOS transistor. A fourth NMOS transistor having a gate connected to the drain of the first NMOS transistor; A source connected to the power terminal, a fifth PMOS transistor having the second bias signal as a gate input, a source connected to the ground voltage terminal, and a gate and a drain connected in common to the drain of the fifth PMOS transistor; A fifth NMOS transistor, a sixth NMOS transistor having a source connected to the ground voltage terminal and a gate connected to a drain of the fifth NMOS transistor; a second NMOS transistor connected between the power supply voltage terminal and the drain of the sixth NMOS transistor; A semiconductor comprising: a resistor; and a sixth PMOS transistor having a source connected to the power supply voltage terminal, a drain connected to the pull-up drive signal terminal, and a gate connected to the drain of the sixth NMOS transistor. A voltage generator for a memory device is provided.

  As a fifth invention, according to the third invention, the auxiliary drive control means includes a third NMOS transistor having a source connected to the output terminal and the gate input of the first bias signal, and a power supply voltage terminal. A third PMOS transistor having a source connected, a gate and a drain commonly connected to the drain of the third NMOS transistor, and a fourth PMOS transistor having a source connected to the power supply voltage terminal and a gate connected to the drain of the third PMOS transistor; A first resistor connected between the drain of the fourth PMOS transistor and the ground voltage terminal; a source connected to the ground voltage terminal; a drain connected to the pull-down drive signal terminal; and the fourth PMOS transistor. A fourth NMOS transistor having a gate connected to the drain of the first NMOS transistor; A source connected to the power terminal, a fifth PMOS transistor having the second bias signal as a gate input, a source connected to the ground voltage terminal, and a gate and a drain connected in common to the drain of the fifth PMOS transistor; A fifth NMOS transistor, a sixth NMOS transistor having a source connected to the ground voltage terminal and a gate connected to a drain of the fifth NMOS transistor; a second NMOS transistor connected between the power supply voltage terminal and the drain of the sixth NMOS transistor; A semiconductor comprising: a resistor; and a sixth PMOS transistor having a source connected to the power supply voltage terminal, a drain connected to the pull-up drive signal terminal, and a gate connected to the drain of the sixth NMOS transistor. A voltage generator for a memory device is provided.

  As a sixth invention, according to the fourth invention or the fifth invention, the first bias signal is higher than the reference voltage by an NMOS threshold voltage, and the second bias signal is PMOS than the reference voltage. A voltage generator for a semiconductor memory device, characterized in that a threshold voltage is at a low level.

  According to a seventh invention, there is provided a voltage generator for a semiconductor memory element according to the fourth invention or the sixth invention, wherein the power supply voltage is a core voltage.

  As an eighth aspect of the invention, bias signal generation for generating a fifth bias signal, a sixth bias signal, a seventh bias signal, and an eighth bias signal having different levels using a reference voltage having a half level of the power supply voltage Means (the fifth bias signal is higher by a predetermined level than the reference voltage, and the sixth bias signal is lower by a predetermined level than the reference voltage), the fifth bias and the seventh A bias signal is applied to respond to the voltage level of the output terminal (half voltage terminal) to generate a pull-up drive signal, and the sixth and eighth bias signals are applied to respond to the voltage level of the output terminal. Drive signal generating means for generating a pull-down drive signal, and pulling up the output terminal in response to the pull-up drive signal and the pull-down drive signal. In response to the voltage driving means for pull-down driving, the fifth bias signal and the sixth bias signal, and the voltage level of the output terminal, the output terminal is assisted in a section where the voltage level of the output terminal is lower than the reference voltage. A voltage generating device for a semiconductor memory device, comprising: an auxiliary driving means that pulls up the output terminal and auxiliary pulls down the output terminal in a section where the voltage level of the output terminal is higher than the reference voltage I will provide a.

  A ninth invention relates to the eighth invention, wherein the voltage driving means has a source connected to a power supply voltage terminal, a drain connected to the output terminal, and a pull-up using the pull-up driving signal as a gate input. A voltage generator for a semiconductor memory device, comprising: a PMOS transistor; and a pull-down NMOS transistor having a source connected to a ground voltage terminal, a drain connected to the output terminal, and a gate input of the pull-down drive signal. I will provide a.

  As a tenth invention, according to the ninth invention, the drive signal generating means is connected between the power supply voltage terminal and the pull-up drive signal terminal, and the seventh bias signal (PMOS is applied from the power supply voltage). A sixth PMPS transistor having a gate input as a gate input and a sixth NMPS transistor connected between the pull-up drive signal end and the output end and having the fifth bias signal as a gate input And a seventh NMPS transistor connected between the ground voltage terminal and the pull-down drive signal terminal, and having the eighth bias signal (a level of the NMOS threshold voltage is higher than the ground voltage) as a gate input; A seventh PMPS transistor connected between the pull-down drive signal terminal and the output terminal and having the sixth bias signal as a gate input; To provide a voltage generator of a semiconductor memory device, characterized in that the.

  An eleventh invention is according to the tenth invention, wherein the auxiliary drive means has a source connected to the output terminal, a drain connected to the power supply voltage terminal, and the fifth bias signal as a gate input. A semiconductor memory device comprising: an eighth NMPS transistor; and an eighth PMPS transistor having a source connected to the output terminal, a drain connected to the ground voltage terminal, and the gate input of the sixth bias signal. A voltage generator is provided.

  The twelfth invention is according to the eleventh invention, wherein the fifth bias signal is higher than the reference voltage by an NMOS threshold voltage, and the sixth bias signal is a PMOS threshold voltage higher than the reference voltage. A voltage generating device for a semiconductor memory device is provided, wherein the voltage level is low.

  According to a thirteenth invention, there is provided a voltage generator for a semiconductor memory element according to the twelfth invention, wherein the power supply voltage is a core voltage.

  According to a fourteenth aspect of the invention, a bias signal for generating a ninth bias signal, a tenth bias signal, an eleventh bias signal, and a twelfth bias signal having different levels from each other using a reference voltage having a half level of the power supply voltage. Generating means (the ninth bias signal is higher by a predetermined level than the reference voltage, and the tenth bias signal is lower by a predetermined level than the reference voltage), and the ninth bias And the eleventh bias signal is applied to generate the pull-up driving signal in response to the voltage level of the output terminal (half voltage terminal), and the tenth and twelfth bias signals are applied to the voltage of the output terminal. Drive signal generating means for generating the pull-down drive signal in response to a level; and pulling up the output terminal in response to the pull-up drive signal. A pull-up PMOS transistor for pull-up driving, a pull-down NMOS transistor for pull-down driving the output terminal in response to the pull-down driving signal, and a power source voltage or the substrate bias voltage of the pull-up PMOS transistor in response to an active signal. First multiplexing means for selectively applying a voltage higher than a power supply voltage; and a first multiplexing means for selectively applying a ground voltage or a voltage lower than the ground voltage as a substrate bias voltage of the pull-down NMOS transistor in response to the active signal. A voltage generator for a semiconductor memory device, comprising: 2 multiplexing means.

  According to a fifteenth aspect, in accordance with the fourteenth aspect, the power supply voltage is a core voltage, and the output terminal is a bit line precharge voltage terminal. Providing equipment.

  As a sixteenth invention, according to the fifteenth invention, the first multiplexing means is controlled by the active signal and its inverted signal, and outputs the core voltage in the active period, A voltage generator for a semiconductor memory device, comprising: a second transmission gate that outputs an external power supply voltage in a standby period under the control of the active signal and its inverted signal.

  As a seventeenth invention, according to the sixteenth invention, the second multiplexing means is controlled by the active signal and its inverted signal, and outputs a ground voltage in the active period; And a fourth transmission gate for outputting a back bias voltage in a standby period, controlled by the active signal and its inverted signal, and a semiconductor memory device voltage generator.

  According to an eighteenth aspect of the invention, a bias signal for generating a first bias signal, a second bias signal, a third bias signal, and a fourth bias signal having different levels by using a reference voltage having a half level of the power supply voltage. Generating means (the first bias signal is higher by a predetermined level than the reference voltage, and the second bias signal is lower by a predetermined level than the reference voltage), the first bias and the first bias A 3 bias signal is applied to respond to the voltage level of the output terminal (half voltage terminal) to generate a pull-up drive signal, and the sixth and fourth bias signals are applied to respond to the voltage level of the output terminal. Driving signal generating means for generating a pull-down driving signal, and pulling up the output terminal in response to the pull-up driving signal and the pull-down driving signal. In response to the voltage driving means for driving up / down, the first bias signal and the second bias signal, and the voltage level of the output terminal, the output terminal is controlled in a section where the voltage level of the output terminal is lower than the reference voltage. A voltage generation of a semiconductor memory device, comprising: auxiliary driving means for auxiliary pull-up driving and auxiliary pull-down driving of the output terminal in a section where the voltage level of the output terminal is higher than the reference voltage Providing equipment.

  The nineteenth invention relates to the eighth invention, wherein the voltage driving means has a source connected to a power supply voltage terminal, a drain connected to the output terminal, and a pull-up driving signal as a gate input. A voltage generation of a semiconductor memory device, comprising: an up PMOS transistor; and a pull-down NMOS transistor having a source connected to a ground voltage terminal, a drain connected to the output terminal, and a gate input of the pull-down driving signal. Providing equipment.

  According to a twentieth aspect of the present invention, in accordance with the ninth aspect of the invention, the drive signal generating means is connected between the power supply voltage terminal and the pull-up drive signal terminal, and the third bias signal (PMOS from the power supply voltage) is connected. A first PMOS transistor whose gate input is a threshold voltage) and a first NMOS which is connected between the pull-up drive signal terminal and the output terminal and uses the first bias signal as a gate input A second NMOS transistor connected between the ground voltage terminal and the pull-down drive signal terminal and having the fourth bias signal (a level of the NMOS threshold voltage higher than the ground voltage) as a gate input; A second PMOS transistor connected between the pull-down drive signal terminal and the output terminal and having the second bias signal as a gate input; To provide a voltage generator of a semiconductor memory device characterized by was e.

  A twenty-first invention relates to the tenth invention, wherein the auxiliary driving means has a source connected to the output terminal, a drain connected to the power supply voltage terminal, and the first bias signal as a gate input. And a third PMOS transistor having a source connected to the output terminal, a drain connected to the ground voltage terminal, and a gate input of the second bias signal. A voltage generator is provided.

  According to a twenty-second invention, according to the eleventh invention, the first bias signal is higher than the reference voltage by an NMOS threshold voltage, and the second bias signal is a PMOS threshold higher than the reference voltage. A voltage generator for a semiconductor memory device, characterized in that the voltage is at a low level.

  According to a twenty-third aspect of the present invention, there is provided a voltage generator for a semiconductor memory element according to the twelfth aspect of the present invention, wherein the power supply voltage is a core voltage.

  According to a twenty-fourth aspect of the invention, a bias for generating a first bias signal, a second bias signal, a third bias signal, and a fourth bias signal having different levels using a reference voltage having a half level of the power supply voltage is provided. Signal generating means (the first bias signal is higher by a predetermined level than the reference voltage, and the second bias signal is lower by a predetermined level than the reference voltage), the first A bias and a third bias signal are applied to generate the pull-up driving signal in response to a voltage level of an output terminal (half voltage terminal), and the sixth bias and the fourth bias signal are applied to the output terminal. Drive signal generating means for generating the pull-down drive signal in response to a voltage level, and pull-up driving the output terminal in response to the pull-up drive signal A pull-up PMOS transistor, a pull-down NMOS transistor that pulls down the output terminal in response to the pull-down drive signal, and a substrate bias voltage of the pull-up PMOS transistor that is higher in response to an active signal than the power supply voltage or the power supply voltage First multiplexing means for selectively applying a voltage, and second multiplexing means for selectively applying a ground voltage or a voltage lower than the ground voltage as a substrate bias voltage of the pull-down NMOS transistor in response to the active signal A voltage generator for a semiconductor memory element, comprising:

  According to the present invention, the bit line precharge voltage or the cell plate voltage can be stably driven in the low power supply voltage state with a low core voltage level, and the standby current IDD2P and the operating current can be minimized. effective.

  In addition, the present invention controls the threshold voltage of the voltage driving means to increase the driving capability when active, and to cut off the leakage current path during standby mode to improve chip reliability. There is an effect of making it possible.

It is a circuit diagram regarding the conventional voltage generator. It is a voltage timing chart regarding the conventional voltage generator. It is a circuit diagram regarding the voltage generator which concerns on this invention. It is other embodiment of the voltage generator which concerns on this invention. It is a voltage timing chart which shows the voltage generator which concerns on this invention. It is further another embodiment of the voltage generator which concerns on this invention. It is further another embodiment of the voltage generator which concerns on this invention. FIG. 8 is an operation timing chart according to the embodiment of FIG. 7.

  Hereinafter, a most preferred embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 3 is a circuit diagram relating to a voltage generator according to the present invention.

  The present invention includes a core voltage control means 10, a drive control means 100, and a voltage drive means 110. Here, since the configuration of the core voltage control means 10 is the same as that of the conventional core voltage control means 10, it will be described with the same reference numerals and a detailed description of the configuration and operation thereof will be omitted. However, for a clear understanding of the present invention, the core voltage control means 10 is divided into a bias signal generation means and a drive signal generation means, although not shown. The bias signal generation means is for generating four bias signals (PBIAS, NGATE, PGATE, NBIAS), and the drive signal generation means is for generating a pull-up drive signal PDRV and a pull-down drive signal NDRV. It is.

  Explaining its detailed configuration, the drive control means 100 includes PMOS transistors P10 to P12 and NMOS transistors N10 to N12. The PMOS transistor P10 is connected between the application terminal of the core voltage VCORE and the NMOS transistor N10, and has a gate terminal commonly connected to the PMOS transistor P11. The PMOS transistor P11 is connected between the application terminal of the core voltage VCORE and the output node A, and has a gate terminal commonly connected to the PMOS transistor P10.

  The NMOS transistor N10 is connected between the PMOS transistor P10 and the output terminal of the bit line precharge voltage VBLP, and the gate voltage NGATE is applied via the gate terminal. The PMOS transistor P12 is connected between the NMOS transistor N11 and the output terminal of the bit line precharge voltage VBLP, and the gate voltage PGATE is applied through the gate terminal.

  The NMOS transistor N11 is connected between the application terminal of the ground voltage VSS and the PMOS transistor P12, and has a gate terminal commonly connected to the NMOS transistor N12. The NMOS transistor N12 is connected between the application terminal of the ground voltage VSS and the output node B, and has a gate terminal commonly connected to the NMOS transistor N11.

  The voltage driving means 110 includes a PMOS transistor P13 and an NMOS transistor N13. The PMOS transistor P13 and the NMOS transistor N13 are connected in series between the core voltage VCORE application terminal and the ground voltage VSS application terminal, and the pull-up drive signal PDRV and the pull-down drive signal NDRV are applied through the respective gate terminals. The bit line precharge voltage VBLP is output through the common drain terminal.

  The operation process of the present invention having such a configuration will be described as follows. First, the bias voltage PBIAS is a level signal around the threshold voltage VT of the core voltage VCORE-PMOS transistor P6. Such a bias voltage PBIAS supplies a constant gate voltage to the PMOS transistor P6 so that a constant current flows. The bias voltage NBIAS is a level signal around the ground voltage VSS + the threshold voltage VT of the NMOS transistor N6. Such a bias voltage NBIAS supplies a constant gate voltage to the NMOS transistor N6 so that a constant current flows.

  The NMOS transistor N8 operates with the bit line precharge voltage VBLP as a source and as the bit line precharge voltage VBLP changes. The PMOS transistor P8 operates with the bit line precharge voltage VBLP as a source, and operates faster as the bit line precharge voltage VBLP changes. That is, the NMOS transistor N8 and the PMOS transistor P8 having the source follower structure are all operated quickly by changing the level of the bit line precharge voltage VBLP, thereby turning on and off the PMOS transistor P13 and the NMOS transistor N13.

  However, a constant current always flows through the NMOS transistor N8 and the PMOS transistor P8, and it takes a long time to turn off the PMOS transistor P13 and the NMOS transistor N13 at the final output terminal.

  Accordingly, the present invention increases the gate-source voltage of the PMOS transistor P8 when the bit line precharge voltage VBLP increases. Accordingly, the voltage level of the pull-down drive signal NDRV rises, and the NMOS transistor N13 is turned on to reduce the level of the raised bit line precharge voltage VBLP.

  At this time, the gate source voltage VGS of the NMOS transistor N10 having the source follower structure decreases, and the node AP becomes the threshold voltage VT level of the core voltage VCORE-NMOS transistor N10. Then, by controlling the gate voltage level of the PMOS transistors P10 and P11 through which a constant current flows by the voltage of the node AP and rapidly increasing the voltage level of the node A to the core voltage VCORE level, a current path is not formed. To do.

  In addition, the PMOS transistor P12 having the source follower structure is turned on more quickly, and the voltage level of the node AC rises. Then, the NMOS transistors N11 and N12 are turned on by the voltage of the node AN, and the voltage level of the node B is reduced, so that no current path is formed.

  On the other hand, when the bit line precharge voltage VBLP decreases, the gate source voltage VGS of the NMOS transistor N8 increases. Accordingly, the voltage level of the pull-up drive signal PDRV is reduced, and the PMOS transistor P13 is turned on to raise the level of the reduced bit line precharge voltage VBLP.

  At this time, the gate source voltage VGS of the PMOS transistor P12 having the source follower structure is decreased, and the node AN becomes the ground voltage VSS + the threshold voltage VT level of the PMOS transistor P10. In response to this, the gate voltage level of the NMOS transistors N11 and N12 through which a constant current flows is controlled by the voltage of the node AN, and the voltage level of the node B is rapidly reduced to the ground voltage VSS level, thereby the current path is changed. Avoid formation.

  Further, the NMOS transistor N10 having the source follower structure is turned on more quickly, and the voltage level of the node AP is reduced. Then, the PMOS transistors P10 and P11 are turned on by the voltage of the node AP, and the voltage level of the node AP is raised so that no current path is formed.

FIG. 4 shows another embodiment of the voltage generator according to the present invention.
The present invention includes a core voltage control means 10, a drive control means 200, and a voltage drive means 210. Here, since the configuration of the core voltage control means 10 is the same as that of the conventional core voltage control means 10, it will be described with the same reference numerals, and detailed description of the configuration and operation will be omitted. However, for a clear understanding of the present invention, the core voltage control means 10 is divided into a bias generation means signal generation means and a drive signal generation means, although not shown. The bias signal generation means is for generating four bias signals (PBIAS, NGATE, PGATE, NBIAS), and the drive signal generation means is for generating a pull-up drive signal PDRV and a pull-down drive signal NDRV. It is.

  Explaining its detailed configuration, the drive control means 200 includes PMOS transistors P14 to P17, NMOS transistors N14 to N17, and resistors R3 and R4. The PMOS transistor P14 is connected between the application terminal of the core voltage VCORE and the NMOS transistor N14, and has a gate terminal commonly connected to the PMOS transistor P15. The PMOS transistor P15 is connected between the application terminal of the core voltage VCORE and the resistor R3, and has a gate terminal commonly connected to the PMOS transistor P14.

  The NMOS transistor N14 is connected between the PMOS transistor P14 and the output terminal of the bit line precharge voltage VBLP, and the gate voltage NGATE is applied through the gate terminal. The resistor R3 is connected between the PMOS transistor P15 and the ground voltage VSS application terminal. The NMOS transistor N15 is connected between the node D and the ground voltage VSS application terminal, and has a gate terminal connected to the resistor R3.

  The PMOS transistor P16 is connected between the NMOS transistor N16 and the output terminal of the bit line precharge voltage VBLP, and is applied with the gate voltage PGATE via the gate terminal. The PMOS transistor P17 is connected between the application terminal of the core voltage VCORE and the node C, and the gate terminal is connected to the resistor R4. The resistor R4 is connected between the application terminal of the core voltage VCORE and the NMOS transistor N17.

  The NMOS transistor N16 is connected between the application terminal of the ground voltage VSS and the PMOS transistor P16, and has a gate terminal commonly connected to the NMOS transistor N17. The NMOS transistor N17 is connected between the application terminal of the ground voltage VSS and the resistor R4, and has a gate terminal commonly connected to the NMOS transistor N16.

  The voltage driver 210 includes a PMOS transistor P18 and an NMOS transistor N18. The PMOS transistor P18 and the NMOS transistor N18 are connected in series between the application terminal of the core voltage VCORE and the application terminal of the ground voltage VSS, and the pull-up drive signal PDRV and the pull-down drive signal NDRV are applied via the respective gate terminals. A bit line precharge voltage VBLP is output via the drain terminal.

  The operation process of the present invention having such a configuration will be described as follows. The four bias signals (PBIAS, NGATE, PGATE, NBIAS) have different voltage levels. In particular, the bias signal NGATE is higher than the reference voltage by a predetermined level, and the bias signal PGATE Is lower than the reference voltage by a predetermined level.

First, when the bit line precharge voltage VBLP increases, the gate source voltage VGS of the PMOS transistor P8 increases. Accordingly, the voltage level of the pull-down drive signal NDRV is increased, and the NMOS transistor N18 is turned on to reduce the level of the increased bit line precharge voltage VBLP.
At this time, the PMOS transistor P16 having the source follower structure is quickly turned on, and the voltage level of the node BN increases. Then, according to the voltage level of the node BN, the NMOS transistors N16 and N17 are turned on, and the PMOS transistor P17 is turned on. In response to this, the voltage level of node C rises rapidly to the core voltage VCORE level so that no current path is formed.

  In addition, the NMOS transistor N14 having the source follower structure maintains the turn-off state because the gate-source voltage VGS is lowered. At this time, the NMOS transistor N14 increases the voltage level of the node BP through a weak bootstrap action. In response to this, the PMOS transistors P14 and P15 are maintained in a turn-off state, and the current path is cut off by controlling the NMOS transistor N15 to be turned off.

  On the other hand, when the bit line precharge voltage VBLP decreases, the gate source voltage VGS of the NMOS transistor N8 increases. Accordingly, the voltage level of the pull-up drive signal PDRV is reduced, and the PMOS transistor P18 is turned on to raise the level of the reduced bit line precharge voltage VBLP.

  At this time, the gate-source voltage VGS of the PMOS transistor P16 having the source follower structure decreases, and a voltage drop occurs at the node BN. In response to this, the NMOS transistors N16 and N17 are turned on, and the gate voltage of the PMOS transistor P17 rises, so that the voltage level of the node C rises. Accordingly, a current path is prevented from being formed via node C regardless of the voltage level of bit line precharge voltage VBLP.

  Further, the NMOS transistor N14 having the source follower structure is turned on more rapidly, and the voltage level of the node BP is reduced. Then, the PMOS transistors P14 and P15 are turned on by the voltage of the node BP, and the gate voltage of the NMOS transistor N15 increases. In response to this, the voltage level of node D is reduced to the ground voltage VSS level so that a current path is not formed.

  FIG. 5 is a voltage timing chart of the present invention according to the embodiment of FIGS. In the present invention, as shown in the voltage timing chart of FIG. 5, the current between the bit line precharge voltage VBLP, the pull-up drive signal PDRV, and the pull-down drive signal NDRV regardless of whether it is in the standby state or the operation mode state. Since no path is formed, the driving ability of the chip can be improved.

  FIG. 6 is still another embodiment of the voltage generator according to the present invention. The present invention includes a core voltage control means 10, a drive control means 300 and a voltage drive means 310. Here, since the configuration of the core voltage control means 10 is the same as that of the conventional core voltage control means 10, it will be described with the same reference numerals, and the detailed configuration and operation thereof will be omitted.

  However, for a clear understanding of the present invention, the core voltage control means 10 is divided into a bias signal generation means and a drive signal generation means, although not shown. The bias signal generation means is for generating four bias signals (PBIAS, NGATE, PGATE, NBIAS), and the drive signal generation means is for generating a pull-up drive signal PDRV and a pull-down drive signal NDRV. It is. The four bias signals (PBIAS, NGATE, PGATE, NBIAS) have different voltage levels. In particular, the bias signal NGATE is higher than the reference voltage by a predetermined level, and the bias signal PGATE Is lower than the reference voltage by a predetermined level.

  Explaining its detailed configuration, the drive control means 300 includes an NMOS transistor N19 and a PMOS transistor P19. Here, the NMOS transistor N19 and the PMOS transistor P19 are connected in series between the application terminal of the core voltage VCORE and the application terminal of the ground voltage VSS, and the gate voltages NGATE and PGATE are applied through the respective gate terminals, and the common drain terminal. The bit line precharge voltage VBLP is output via

  The voltage driving means 310 includes a PMOS transistor P20 and an NMOS transistor N20. The PMOS transistor P20 and the NMOS transistor N20 are connected in series between the core voltage VCORE application terminal and the ground voltage VSS application terminal, and the pull-up drive signal PDRV and the pull-down drive signal NDRV are applied through the respective gate terminals. The bit line precharge voltage VBLP is output through the drain terminal.

  The present invention having such a configuration includes an NMOS transistor N19 having the gate voltage NGATE as an input and the bit line precharge voltage VBLP as a source, and a PMOS having the gate voltage PGATE as an input and the bit line precharge voltage VBLP as a source. The direct current path is interrupted via the transistor P19 so that the driving capability of the voltage driving means 310 can be improved.

  FIG. 7 is still another embodiment of the voltage generator according to the present invention. The present invention includes a core voltage control unit 10, a voltage driving unit 400, and an output control unit 410. Here, since the configuration of the core voltage control means 10 is the same as that of the conventional core voltage control means 10, it will be described with the same reference numerals, and detailed description of the configuration and operation thereof will be omitted.

  However, for a clear understanding of the present invention, the core voltage control means 10 is divided into a bias signal generation means and a drive signal generation means, although not shown. The bias signal generation means is for generating four bias signals (PBIAS, NGATE, PGATE, NBIAS), and the drive signal generation means is for generating a pull-up drive signal PDRV and a pull-down drive signal NDRV. It is. The four bias signals (PBIAS, NGATE, PGATE, NBIAS) have different voltage levels. In particular, the bias signal NGATE is higher than the reference voltage by a predetermined level, and the bias signal PGATE Is lower than the reference voltage by a predetermined level.

  The voltage driving unit 400 includes a PMOS transistor P21 and an NMOS transistor N21. The PMOS transistor P21 and the NMOS transistor N21 are connected in series between the application terminal of the core voltage VCORE and the application terminal of the ground voltage VSS, and the pull-up drive signal PDRV and the pull-down drive signal NDRV are applied via the respective gate terminals. The bit line precharge voltage VBLP is output through the drain terminal.

  Further, the output control means 410 includes transmission gates T1 to T4. Here, the transmission gate T1 outputs the core voltage VCORE to the bulk of the PMOS transistor P21 in accordance with the states of the control signals AA and BB. Then, the transmission gate T2 outputs the power supply voltage VDD to the bulk of the PMOS transistor P21 according to the states of the control signals AA and BB.

  Then, the transmission gate T3 outputs the ground voltage VSS to the bulk of the NMOS transistor N21 according to the states of the control signals AA and BB. The transmission gate T4 outputs the back bias voltage VBB to the bulk of the NMOS transistor N21 according to the states of the control signals AA and BB.

  Here, the control signal AA is a signal obtained by inverting the active signal ACT by the inverter IV1, and the control signal BB is a signal obtained by inverting the control signal AA by the inverter IV2. The control signals AA are applied to the transmission gates T1 and T3 through the PMOS gate, and the control signal BB is applied through the NMOS gate. Further, the control signals BB are applied to the transmission gates T2 and T4 through the PMOS gate, and the control signal AA is applied through the NMOS gate.

  The operation process of the present invention having such a configuration will be described with reference to the operation timing chart of FIG. First, in the active operation mode, when the active signal ACT becomes active, the control signal AA becomes low and the control signal BB becomes high. In response to this, the transmission gates T1 and T3 are turned on, the core voltage VCORE is applied to the bulk of the PMOS transistor P21, and the ground voltage VSS is applied to the bulk of the NMOS transistor N21. Therefore, the threshold voltages of the PMOS transistor P21 and the NMOS transistor N21 are lowered during the active operation mode, so that the driving capability can be improved.

  On the other hand, in the standby mode other than the active operation mode, when the active signal ACT becomes inactive, the control signal AA becomes high and the control signal BB becomes low. In response to this, the transmission gates T2 and T4 are turned on, the power supply voltage VDD is applied to the bulk of the PMOS transistor P21, and the back bias voltage VBB is applied to the bulk of the NMOS transistor N21. Accordingly, in the standby mode, the threshold voltage of the PMOS transistor P21 and the NMOS transistor N21 is increased to block the leakage current path.

  That is, the present invention controls the bulk bias of the PMOS transistor P21 to which the core voltage VCORE is applied to the source, and performs the self-bias in order to reduce the threshold voltage VT when active. In the standby mode, the back bias voltage VBB is applied to the NMOS transistor N21 of the voltage driver 400 in order to reduce the leakage current, that is, to increase the threshold voltage VT.

  The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the scope of the technical idea according to the present invention, and these are also within the technical scope of the present invention. Belonging to.

10 Core voltage control means 100 Drive control means 110 Voltage drive means

Claims (4)

Bias signal generating means for generating a ninth bias signal, a tenth bias signal, an eleventh bias signal, and a twelfth bias signal having different levels using a reference voltage having a half level of the power supply voltage (the ninth bias signal) Is higher by a predetermined level than the reference voltage, and the tenth bias signal is lower than a predetermined level by the reference voltage).
The ninth bias signal and the eleventh bias signal are applied to generate the pull-up driving signal in response to a voltage level at an output terminal (half voltage terminal), and the tenth bias signal and the twelfth bias signal are applied to the pull-up driving signal. Drive signal generating means for generating the pull-down drive signal in response to the voltage level of the output end;
A pull-up PMOS transistor for pull-up driving the output terminal in response to the pull-up drive signal;
A pull-down NMOS transistor for pull-down driving the output terminal in response to the pull-down drive signal;
First multiplexing means for selectively applying the power supply voltage or a voltage higher than the power supply voltage as a substrate bias voltage of the pull-up PMOS transistor in response to an active signal;
And a second multiplexing means for selectively applying a ground voltage or a voltage lower than the ground voltage as a substrate bias voltage of the pull-down NMOS transistor in response to the active signal. Generator.   2. The voltage generation apparatus for a semiconductor memory device according to claim 1, wherein the power supply voltage is a core voltage, and the output terminal is a bit line precharge voltage terminal. The first multiplexing means comprises:
A first transmission gate controlled by the active signal and its inverted signal and outputting the core voltage in an active period;
3. The voltage generation apparatus for a semiconductor memory device according to claim 2, further comprising a second transmission gate controlled by the active signal and its inverted signal and outputting an external power supply voltage in a standby period. The second multiplexing means comprises:
A third transmission gate controlled by the active signal and its inverted signal to output the ground voltage in an active period;
4. The voltage generation device for a semiconductor memory device according to claim 3, further comprising a fourth transmission gate controlled by the active signal and an inverted signal thereof to output a back bias voltage in a standby period.

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