KR970023423A - Word line driving method of semiconductor memory device - Google Patents

Word line driving method of semiconductor memory device Download PDF

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Publication number
KR970023423A
KR970023423A KR1019950038739A KR19950038739A KR970023423A KR 970023423 A KR970023423 A KR 970023423A KR 1019950038739 A KR1019950038739 A KR 1019950038739A KR 19950038739 A KR19950038739 A KR 19950038739A KR 970023423 A KR970023423 A KR 970023423A
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KR
South Korea
Prior art keywords
low address
low
address buffer
word line
memory device
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KR1019950038739A
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Korean (ko)
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KR0172396B1 (en
Inventor
유제환
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김광호
삼성전자 주식회사
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Priority to KR1019950038739A priority Critical patent/KR0172396B1/en
Publication of KR970023423A publication Critical patent/KR970023423A/en
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Publication of KR0172396B1 publication Critical patent/KR0172396B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 워드라인의 인에이블싯점을 빠르게 하므로써 고속의 액세스동작을 실행하는 반도체 메모리장치의 워드라인 인에이블방법에 관한 것이다.The present invention relates to a word line enable method of a semiconductor memory device which executes a high speed access operation by accelerating the enable line of a word line.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

스탠바이전류증가없이 로우어드레스버퍼의 인에이블시점을 빠르게 하여 고속의 액세스동작을 실행하는 반도체 메모리장치를 구현하는 것이 본 발명의 해결과제이다.It is a task of the present invention to implement a semiconductor memory device which executes a high-speed access operation by accelerating the low address buffer enable time without increasing the standby current.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

외부어드레스입력에 응답하여 소정의 워드라인을 지정하는 로우어드레스신호를 출력하는 로우어드레스버퍼와, 상기 로우어드레스버퍼의 출력단과 접속되어 상기 제1로우어드레스버퍼의 출력을 디코딩하는 출력하는 로우프리디코더와, 상기 로우프리디코더의 출력신호를 디코딩하여 소정의 워드라인을 인에이블시키는 로우디코더를 구비하며, 스탠바이상태와 상기 로우어드레스버퍼의 동작상태를 외부신호들의 특정조합으로 구분하고, 로우어드레스 스트로브신호가 액티브되기 이전에 로우어드레스버퍼를 동작시켜 고속의 액세스동작을 수행하게 된다.A low address buffer for outputting a low address signal specifying a predetermined word line in response to an external address input, a low predecoder for outputting the output of the first low address buffer connected to an output terminal of the low address buffer; And a low decoder for enabling a predetermined word line by decoding the output signal of the low predecoder, and classifying a standby state and an operation state of the low address buffer into a specific combination of external signals, and a low address strobe signal The low address buffer is operated prior to being activated to perform a high speed access operation.

4. 발명의 중요한 용도4. Important uses of the invention

스탠바이전류증가없이 고속동작하는 반도체 메모리장치.A semiconductor memory device that operates at high speed without increasing standby current.

Description

반도체 메모리장치의 워드라인 구동방법Word line driving method of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 실시예에 따른 워드라인 인에이블과정을 보여주는 블럭도,3 is a block diagram showing a word line enabling process according to an embodiment of the present invention;

제4도는 제3도에 따른 동작타이밍도,4 is an operation timing diagram according to FIG.

제5도는 제3도를 구성하는 로우디코더의 상세회로도.5 is a detailed circuit diagram of a low decoder constituting FIG.

Claims (3)

반도체 메모리장치의 워드라인 인에이블방법에 있어서, 외부어드레스입력에 응답하여 소정의 워드라인을 지정하는 로우어드레스신호를 출력하는 로우어드레스버퍼와, 상기 로우어드레스버퍼의 출력단과 접속되어 상기 제1로우어드레스 버퍼의 출력을 디코딩하는 출력하는 로우프리디코더와, 상기 로우프리디코더의 출력신호를 디코딩하여 소정의 워드라인을 인에이블시키는 로우디코더를 구비하며, 스탠바이상태와 상기 로우어드레스버퍼의 동작상태를 외부신호들의 특정조합으로 구분하고, 로우어드레스 스트로브신호가 액티브되기 이전에 로우어드레스버퍼를 동작시켜 고속의 액세스동작을 수행함을 특징으로 하는 반도체 메모리장치의 워드라인 인에이블방법.A word line enable method of a semiconductor memory device, comprising: a low address buffer for outputting a low address signal for designating a predetermined word line in response to an external address input, and a first low address connected to an output terminal of the low address buffer; A low predecoder for decoding the output of the buffer and a low decoder for enabling a predetermined word line by decoding the output signal of the low predecoder, and a standby state and an operation state of the low address buffer. And a high-speed access operation by operating the low address buffer before the low address strobe signal is activated, the word line enabling method of the semiconductor memory device. 제1항에 있어서, 상기 외부신호들이 로우어드레스 스트로브신호, 컬럼어드레스 스트로브신호 및 라이트 제어신호임을 특징으로 하는 반도체 메모리장치의 워드라인 인에이블방법.The method of claim 1, wherein the external signals are a low address strobe signal, a column address strobe signal, and a write control signal. 반도체 메모리장치의 로우어드레스버퍼 제어방법에 있어서, 스탠바이상태와 로우어드레스버퍼의 인에이블상태를 외부신호들의 조합으로 구분하고, 로우어드레스 스트로브신호가 액티브되기 전에 로우어드레스버퍼가 동작하며, 상기 로우어드레스 스트로브신호가 액티브 상태로 되는 것을 감지하거나 상기 외부신호들의 조합을 감지하여 일정 시간후에 상기 로우어드레스버퍼의 출력인 로우어드레스신호를 래치한 뒤 상기 로우어드레스버퍼를 디스에이블시키는 것을 특징으로 반도체 메모리장치의 로우어드레스버퍼 제어방법.In a low address buffer control method of a semiconductor memory device, a standby state and an enable state of a low address buffer are classified into a combination of external signals, and a low address buffer is operated before a low address strobe signal is activated. Detecting a signal to become active or detecting a combination of the external signals to latch a low address signal, which is an output of the low address buffer, and then disable the low address buffer after a predetermined time Address buffer control method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950038739A 1995-10-31 1995-10-31 Wordline driving method of semiconductor memory devicei KR0172396B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950038739A KR0172396B1 (en) 1995-10-31 1995-10-31 Wordline driving method of semiconductor memory devicei

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KR970023423A true KR970023423A (en) 1997-05-30
KR0172396B1 KR0172396B1 (en) 1999-03-30

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Publication number Priority date Publication date Assignee Title
JP2000048567A (en) * 1998-05-22 2000-02-18 Mitsubishi Electric Corp Synchronous semiconductor memory
KR100318439B1 (en) * 1999-06-30 2001-12-24 박종섭 Memory device and method for improving word line access time

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