KR950008456B1 - Data output buffer enable signal generator of semiconductor memory device - Google Patents

Abstract

The device solves problems which arise in controlling independently the time that selected lead data reaches data-output buffer and the time that data-output buffer operates after the output enable signal is enabled. The device comprises a column start signal generating unit which generate column start signal with low address strobe signal, a sense enable signal generator which generates sense enable signal by the output of column address detector, a column address strobe signal buffer which buffers the column address strobe signal, the first synchronizing unit which synchronizes the starting point of the buffered address strobe signal with the column start signal, a delay chain unit which delays the sense enable signal, and the second synchronizing unit which synchronizes the starting point of the buffered column address strobe signal with the delayed sense enable signals.

Description

Data Output Buffer Enable Signal Generator for Semiconductor Memory Devices

1 is a block diagram of a conventional column read cycle.

2 is a block diagram of a column read cycle in accordance with the present invention.

3 is a timing diagram of a signal when a column address set-up time t _ASC is 0 ns in a conventional circuit.

4 is a timing diagram of each signal when the column address set-up time t _ASC is 0 ns in the circuit of the present invention.

5 is a circuit diagram illustrating an embodiment of a data output buffer enable signal generator of the present invention.

* Explanation of symbols for main parts of the drawings

1: column address buffer 3: address transition detector

5: preconditioning signal generator 7: data busline preconditioning circuit

9: Sense Enable Signal Generator 11: Column Address Predecoder

13: Y-decoder 15: Databus line

17: data bus sense amplifier 19: read data driver

21: CAS buffer 23,30: output enable signal generator

25: Data output buffer 40: Time delay gate chain.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer enable signal generator of a semiconductor memory device. In particular, the present invention detects a change in a column address when reading data of a cell, thereby outputting data. A data output buffer enable signal generator for generating a data output buffer enable signal to enable a buffer to operate.

Dynamic Random Access Memory (hereinafter referred to as DRAM) devices are memory devices capable of reading or writing data. The word lines selected by Row Addres are selected. And a Y-decoder selected by a column address read or write data of a specific memory cell.

In general, a read cycle in a DRAM starts when a low address strobe signal RAS is enabled, and when a specific word line is selected by a combination of low addresses, data of the selected word line is bit line sensed. The data is transmitted to the bit line sense amplifier, and the data transmitted to the bit line sense amplifier is reselected by the combination of the column addresses, and the selected data is output to the data output buffer.

Referring to the general column read cycle, as shown in the block diagram of FIG. 1, the conventional column read operation receives the column address A _N coming into the external pin through the column address buffer 1, and each column address buffer ( An address transition detection signal ATDi is output by connecting an address transition detector 3 capable of detecting an address transition every 1), and the output ATDi signal is a data bus line free for determining the state of a data bus line. The precondition signal generator 5, which is the input signal of the condition circuit 7, enters the precondition signal? PC, and the? PC signal controls the data bus line precondition circuit 7.

In addition, the output of the column address buffer 1 outputs a specific column address information signal Yi through the column address predecoder 11 and the Y-decoder 13, and the data sensed by the bit line sense amplifier (not shown) Selected by the above Yi signal, it is transferred to the data bus line 15 DB / DB connected to the data bus sense amplifier 17.

The above? PC signal enters to the input of the sense enable signal generator 9 for outputting a signal for controlling the operation of the data bus sense amplifier 17 for amplifying the data transmitted to the data bus line 15 and outputs the? Signal. When the output data bus sense amplifier enable signal? SE is enabled and data is amplified by the bus sense amplifier 17 and transferred to the DBO line, a read data driver 19 reads on the DBO line. Transfer data to RD / RD line.

The data transferred to the RD / RD line is the signal CAS1 buffered and output from the CAS buffer 21 by the column address strobe signal CAS inputted to an external pin, and the column start signal controlled by the low address strobe signal RAS. When is input, when the øOE signal output from the output enable signal generator 23 is enabled, the data output buffer 25 is operated to be output to the external data output pin.

In the above conventional column read cycle, the output enable signal? QE controlling the data output buffer 25 is immediately enabled by the buffered CAS1 signal when the column address strobe signal CAS is enabled, so that after the column address input is applied. When the column address set-up time, which is the time until the CAS signal is input, is 0 ns, the valid lead data selected by the new column address in which the øOE signal enabled by the CAS signal is valid is valid. By enabling the data output buffer 25 even before it reaches the RD / RD line, there is a risk of undesired data being output. In this case, not only does it take a long time to output valid data, but also the data output buffer. To drive pull-ip / pull-down transistors, which are the off-chip driver stages of (25). However, there is a lot of power consumption, and when the transition from invalid data (Valid Data) to valid data (Valid Data), it causes problems such as noise on the data output pin.

Therefore, in the present invention, the above-described problem may be generated because the time at which the read data selected by the column address reaches the data output buffer and the time at which the output enable signal? OE is enabled to operate the data output buffer independently are mutually controlled. The purpose is to design a circuit to remove the circuit.

In the present invention, as shown in FIG. 2, not only the sense enable signal? SE controlled by the ATDi signal generated when the column address transitions is used to control the operation of the data bus sense amplifier, but also the output enable signal of the data output buffer. After the valid data read using the input signal of the generator 30 is amplified by the data bus sense amplifier 17 and transferred to the RD / RD line, the time that the? OE signal is enabled to operate the data output buffer 25 is achieved. By adjusting, the possibility of invalid data being output is eliminated. (The operation of the other circuit is as described with reference to the circuit block diagram shown in FIG. 1).

By controlling the signals related to the column read paths with the block structure of the circuit shown in FIG. 2, it is possible to adjust the data output buffer enable signal øOE to be enabled after the effective lead data is always transmitted to the RD / RD line. Therefore, the memory device operates stably because power consumption due to invalid lead data and data output time delay to an external data output pin can be reduced, and noise generated at the data output pin can be eliminated.

3 is a timing diagram showing an operation time of each signal generated in the conventional column read cycle circuit structure shown in FIG. 1 in consideration of an operation sequence and a control relationship between the signals.

4 is a timing diagram showing an operation time of each signal generated in the column read cycle circuit structure of the present invention shown in FIG. 2 in consideration of an operation sequence and a control relationship between the signals.

As shown in Fig. 4, since the? OE signal is controlled by the ATDi signal outputted by detecting the column address transition, the operation time is always adjusted to enable after the effective lead data reaches the RD / RD line.

5 is a circuit diagram showing an embodiment of the data output buffer enable signal generator, in which the input time of the? SE signal is adjusted by the length of the time delay gate chain 40, and the CAS buffer output signals CAS1 and CAS2 are Even when quickly enabled, the øOE signal is enabled when the VD node, which is the output terminal of the time delay gate chain 40 adjusted in consideration of the time that the read data reaches the data output buffer, is enabled high. (In Fig. 5, the EW signal, which is an early write signal, is always low when data is read, and the? CS signal is a column start signal.)

In detail, the time delay gate chain 40 includes four inverters GI1 to GI4, two capacitors C1 and C2, and two NAND gates GN1 and GN2. Generates a pulse at the beginning of (SE) and delays the pulse signal for a certain time. The delay time gate chain 40 outputs the delayed pulse signal.

One inverter GI5 and three NAND gates GN3 to GN5 function to match the start of the CAS1 signal from the CAS buffer with the start of the delayed pulse signal from the time delay gate chain 40. .

The two inverters GI6 and GI7 and one NAND gate GN6 have the column start signal (/ øCS only) when the early write signal maintains high logic and the / CAS2 signal from the CAS buffer maintains high logic. ) Is printed.

In addition, two NAND gates GN7 and GN8 and one inverter GI8 serve to match the start time of the CAS1 signal from the CAS buffer with the output signal of the NAND gate GN6.

Finally, one inverter GI9 and one NAND gate GM9 selectively apply the output signal from the inverter GI8 to the data output buffer according to the logic state of the output signal from the inverter GI5. . As a result, the output signal of the inverter GI9 is used as the data output buffer enable signal? OE.

As described above, the present invention can accurately match the driving time of the data output buffer with the output time of the read data by the sense enable signal even when the column start signal is enabled in advance. For this reason, the present invention provides an advantage of preventing the malfunction of the data output buffer and the malfunction of the semiconductor memory device.

Claims (1)

A column start signal generator for generating a column start signal using the row address strobe signal, a sense enable signal generator for generating a sense enable signal by the output of the column address transition detector, and a low active column address strobe signal. A semiconductor memory device having a column address strobe signal buffer for buffering and a data output buffer for buffering read data to be output to the outside, wherein the start point of the buffered column address strobe signal from the column address strobe signal buffer is provided. A first synchronous means for matching with the column start signal, a delay chain for delaying the sense enable signal for a predetermined time, and a starting point of the buffered column address strobe signal from the column address strobe signal buffer. A second synchronization means for matching the delayed sense enable signal from a delay chain, and an output signal of the first synchronization means to be transmitted to the data output buffer by an output signal of the second synchronization means to output the data. A data output buffer enable signal generator, comprising: switching means for selectively driving a buffer.