JPS5755598A - Memory integrated circuit - Google Patents

Memory integrated circuit

Info

Publication number
JPS5755598A
JPS5755598A JP55129688A JP12968880A JPS5755598A JP S5755598 A JPS5755598 A JP S5755598A JP 55129688 A JP55129688 A JP 55129688A JP 12968880 A JP12968880 A JP 12968880A JP S5755598 A JPS5755598 A JP S5755598A
Authority
JP
Japan
Prior art keywords
circuit
test
circuits
terminal
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55129688A
Other languages
Japanese (ja)
Inventor
Toru Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55129688A priority Critical patent/JPS5755598A/en
Publication of JPS5755598A publication Critical patent/JPS5755598A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing

Abstract

PURPOSE:To increase the easiness of test for the attachment unit itself of a memory integrated circuit, by installing the memory integrated circuit that possesses a self-diagnosing function plus its function starting terminal and a display terminal for the result of diagnosis. CONSTITUTION:A certain test alogorism is generated by a control circuit 201 connected to a receiving terminal 200 of diagnosis start signal. A test address generating circuit 204, a test pattern generating circuit 202 and a timing generating circuit 206 are connected to the control circuit 200. Then the output of each of the circuits 204, 202 and 206 can be swithced with the input during the normal reading/ writing action to be supplied to memory circuits 107-109. The read outputs of the circuits 107-119 are compared 203 with the output of the circuit 202; and the result of this comparison is supplied to the terminal 206.
JP55129688A 1980-09-18 1980-09-18 Memory integrated circuit Pending JPS5755598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55129688A JPS5755598A (en) 1980-09-18 1980-09-18 Memory integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55129688A JPS5755598A (en) 1980-09-18 1980-09-18 Memory integrated circuit

Publications (1)

Publication Number Publication Date
JPS5755598A true JPS5755598A (en) 1982-04-02

Family

ID=15015721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55129688A Pending JPS5755598A (en) 1980-09-18 1980-09-18 Memory integrated circuit

Country Status (1)

Country Link
JP (1) JPS5755598A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6064842U (en) * 1983-10-13 1985-05-08 村川　驍 Dust collection suction port in printing paper dust collection devices such as offset rotary printing machines
JPS60126755A (en) * 1983-12-13 1985-07-06 Fujitsu Denso Ltd Ram check system
JPS60245275A (en) * 1984-05-18 1985-12-05 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Memory array chip
JPS6214398A (en) * 1985-07-12 1987-01-22 Fujitsu Ltd Semiconductor memory device
JPS6238600A (en) * 1985-08-14 1987-02-19 Fujitsu Ltd Semiconductor memory device
JPS62239400A (en) * 1986-04-08 1987-10-20 Nec Corp Random access memory
JPS634500A (en) * 1986-06-24 1988-01-09 Nec Corp Ram device with test circuit
JPS6325749A (en) * 1986-07-18 1988-02-03 Nec Corp Semiconductor storage element
US6782498B2 (en) 2000-01-13 2004-08-24 Renesas Technology Corp. Semiconductor memory device allowing mounting of built-in self test circuit without addition of interface specification

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6064842U (en) * 1983-10-13 1985-05-08 村川　驍 Dust collection suction port in printing paper dust collection devices such as offset rotary printing machines
JPS60126755A (en) * 1983-12-13 1985-07-06 Fujitsu Denso Ltd Ram check system
JPS60245275A (en) * 1984-05-18 1985-12-05 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Memory array chip
JPH0411960B2 (en) * 1984-05-18 1992-03-03 Intaanashonaru Bijinesu Mashiinzu Corp
JPS6214398A (en) * 1985-07-12 1987-01-22 Fujitsu Ltd Semiconductor memory device
JPS6238600A (en) * 1985-08-14 1987-02-19 Fujitsu Ltd Semiconductor memory device
JPS62239400A (en) * 1986-04-08 1987-10-20 Nec Corp Random access memory
JPS634500A (en) * 1986-06-24 1988-01-09 Nec Corp Ram device with test circuit
JPS6325749A (en) * 1986-07-18 1988-02-03 Nec Corp Semiconductor storage element
US6782498B2 (en) 2000-01-13 2004-08-24 Renesas Technology Corp. Semiconductor memory device allowing mounting of built-in self test circuit without addition of interface specification

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