JPS6325749A - Semiconductor storage element - Google Patents

Abstract

PURPOSE:To perform a diagnosis at a time for each storage element and to shorten the time needed for diagnoses by setting a diagnosing circuit into a semiconductor memory element. CONSTITUTION:The input terminals 2-0-2-17 of an address group are connected to the address parts a0-a17 of a memory cell 1 via the selection circuits 3-0-3-17. When a diagnosis mode request signal 12 is turned on, various control signals are generated by a diagnosis mode timing generating circuit 13. Then a diagnosis mode is set and the cell 1 is tested. The read output of the cell 1 is connected to a read output terminal 8 and also compared with write data on a selection circuit 6 via an exclusive NOR circuit 9 in a diagnosis mode. When no coincidence is obtained from said comparison, the result of comparison is stored in an error flip-flop 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory element used in an information processing device.

(Prior Art) Conventionally, this type of semiconductor memory element does not have a diagnostic function in the element itself, and all terminals to which address signal groups, write data groups, and read/f write designation signals are input, and which output read data are used. I'm just thinking about the configuration that I have.

To ensure this, the information processing device had a diagnostic function within the device and was diagnosing the memory element.

(Problems to be Solved by the Invention) By the way, with recent rapid technological advances, the number of memory valleys 1 has increased significantly, and the storage capacity of devices has accordingly increased dramatically. Therefore, diagnosing the entire situation through sequential self-diagnosis as in the past requires a long diagnosis time, and system operation is often complicated.

An object of the present invention is to provide a
, Does the memory element itself have a diagnostic function? It is an object of the present invention to provide a semiconductor memory element that can reduce the time required for diagnosis by allowing diagnosis to be executed simultaneously for all memory elements.

(Problem?al-Means for solving) Said purpose? In order to achieve this, the semiconductor memory device according to the present invention has an address signal group, a write data group, and a write designation signal. When a diagnostic mode request is received in a semiconductor memory element that stores write data in a memory cell in response to a diagnostic mode request and reads data stored in the memory cell in response to an address signal group and a read designation signal, Address counter clock, write test pattern designation signal read or write designation signal and error f protruding clock? A diagnostic mode timing generation circuit that generates at each timing, an address counter for generating a diagnostic address that generates a diagnostic address signal '(Il-) by inputting the address counter clock, and a diagnostic that generates diagnostic data based on the write test pattern designation signal. a data generation circuit; a first switching circuit that switches the address signal group to an 8-analysis address signal when receiving the diagnostic mode; and a second switching circuit that switches the write data group to all diagnostic data when the diagnostic mode is received. and a third switching circuit that switches the read/write designation signal to a read/write designation signal output from a diagnostic mode timing generation circuit when the diagnostic mode is activated; ,
The device is constructed by providing an output data comparison circuit that compares the information with the bladder extraction diagnostic data, and a flip-flop that stores an error detected by the read data comparison circuit.

Next, the present invention will be explained with reference to all the drawings.

FIG. 1 is a block diagram showing the entire concept of a semiconductor memory element according to the present invention. A diagnostic address, a generation address counter 4, a diagnostic data generation circuit 5, a data comparison circuit 9, a diagnostic mode timing generation circuit 13, an error 7 lip-frog 10, a switching circuit 3, 6 and 1? are provided around the memory cell 1.
is installed. Control signal (diagnostic mode Hosui signal) 1
2, when the mode is set to diagnosis mode, address break 2, shaving data #7, and output/write designation signal 21 are sent from the host device.
is the diagnostic address by switching circuits 3.6 and 14,
The signals are switched to diagnostic data and read/write signals, respectively, and a complete diagnosis of the memory element 1 is executed. The read data from the memory 1 is outputted to the outside at the terminal 8, but the read data and diagnostic data are compared in the data comparison circuit 9, and if an error is detected as a result, it is stored in the error flip-flop 10. The information is reported to a higher-level device (not shown) via all terminals 11.

In addition, an initialization signal generation circuit is installed in the memory element when power is turned on, and F! If the tlJ control signal is generated, diagnosis can be performed each time the power is turned on.

(Example) Next, an example will be described using FIG. 2 and the following drawings.

FIG. 2 shows the implementation of a semiconductor memory device according to the present invention! FIG.

FIG. 2 shows the case of a 256 word×1 bit memory element.

Input terminals 2-0 to 2-17 at address 92 are far and near circuit 3
Address section aO of memory cell 1 via -0 to 3-17
Connected to a17. When the diagnostic mode request signal 12 turns ON, the diagnostic mode timing generation circuit 13 generates q! R types of control signals are generated and serve as diagnostic nodes to test the memory cell 1.

Address counter 4 supplies a diagnostic address to memory cell l.

The write data at the time of diagnosis uses the least significant bit information of the address counter, and two types of diagnosis patterns can be used by selecting the polarity of the data with the selection circuit 5-2.

The switching circuit 6 selects normal write data and diagnostic data from the outside, and its output is led to the stored data input 'FAD in' of the memory cell.

The readout output Dout of the memory cell is the readout terminal 8.
, and when in the 1 diagnosis mode, the scan data of the selection circuit 6 is compared and verified by the exclusive NOR circuit 9, and if they do not match, the result is stored in the error flip-flop 10.

The information is reported to the outside via the terminal 11'.

Next, the operation of this embodiment will be explained using time chart 1 shown in FIG.

In FIG. 3, when the diagnostic mode request signal 12 is turned ON, the diagnostic mode 14 is generated by the diagnostic mode timing generation circuit 13. In the case of this embodiment, the diagnostic mode signal 14 is automatically turned off internally when one diagnostic cycle is completed.
becomes.

The diagnostic mode timing generation circuit 13 has a control clock 2.
0 is given, and the address counter clock 17 and error detection clock 18 are generated based on this clock.

The output signal of the address counter 4 outputs a combination from address O@ to address N (in the case of a non-embodiment, addresses 262 and 143e).

Bladder extraction/writing designation 15 in diagnostic mode is also generated by the diagnostic mode generation circuit 13, and first from address O to address N! Input (subcycle 1), and then output from address 00 to address N (subcycle 2). At this time, the write data uses all the information in the least significant bit of the address, so 0.1, 2, etc.・・・・・・0 for each N address
, 1 , 0°...1 data is subcycle 1
The 10th data is read out in subcycle 2, and the address least significant bit information is compared with the read data.

Furthermore, in subcycle 3, the reverse polarity of the least significant bit of the address is selected for the write data, and similarly, in subcycle/L
/4 is compared.

In the unlikely event that data comparison does not match and an error is discovered, error 7 lip-flop 10 is set and reported to the host device.

FIGS. 4 and 5 are diagrams for explaining the configuration and operation when automatic diagnosis is performed when the power is turned on.

Figure 4 episode'#! r is an integrating circuit 20. Schmitt circuit 2
It is composed of 113 flip-flops 22, 23, 24 and a gate 25, and is incorporated into a memory device. When the power supply of the device is turned on, the logic circuit voltage Vcc rises.

The integrating circuit 21 consisting of a resistor R and a capacitor C completely integrates this, resulting in a rise as shown in FIG. 5 (21). When this integral output is input to the Schmitt circuit, its output B has a timing as shown in FIG. 5 (22). When this is differentiated through the shift flip-flops 23, 24 and 25, the control signal F(26) is generated only immediately after the power is turned on.
is obtained. Here, the signal E input to each flip-flop 23, 24 and 25 is the same as the control clock 20 of FIG.

The pulse width of the control signal F can be changed by changing the number of shift flip-flops.

The control signal F serves as the diagnosis request signal 12 in FIGS. 1 to 3, and is not required at the terminal, so that the memory element can be automatically diagnosed when the power is turned on.

(Effects of the Invention) As described above, the semiconductor memory element according to the present invention has a configuration in which a circuit for performing diagnosis is provided inside.

Therefore, in an information processing device that utilizes all of the semiconductor memory elements, there is no need to install a separate diagnostic function circuit gold film inside the information processing device (diagnosis can be performed simultaneously within each memory element, so diagnosis can be performed in a short time). It has the effect of being executable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of a semiconductor memory element according to the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart for explaining the operation of FIG. 2.
FIG. 4 is a circuit diagram of a power-on initialization signal generated as a diagnosis request signal, and FIG. 5 is a time chart for explaining the operation of FIG. 4. l...Memory cell 2...Address group 3.6.
19...Switching circuit 5...Diagnostic data generation circuit 7...Storage data group 8.11...Terminal 9...
・Data comparison circuit 10...Error flip-flop 12...Control signal (diagnosis mode request signal) 13...
Diagnostic mode timing generation circuit 14...Diagnostic mode signal 15...View/write designation signal 16...Write test pattern designation signal 17...Address counter clock 18...Error detection clock Patent applicant Japan Representative of Denki Co., Ltd. Patent attorney Jusai Inoro Figure 1 Figure 22

Claims (2)

[Claims] (1) Upon receiving the address signal group, the write data group, and the write designation signal, store the write data in the memory cell,
In a semiconductor memory device that reads stored data from a memory cell in response to an address signal group and a read designation signal, when a diagnostic mode request is received, the diagnostic mode is output, and an address counter clock and a write test pattern designation signal are used to designate read or write. a diagnostic mode timing generation circuit that generates a signal and an error detection clock at respective timings; a diagnostic address generation address counter that generates a diagnostic address signal by inputting the address counter clock; and a diagnostic mode timing generation circuit that generates a diagnostic address signal by inputting the address counter clock; a first switching circuit that switches the address signal group to a diagnostic address signal when receiving the diagnostic mode; and a second switching circuit that switches the write data group to diagnostic data when receiving the diagnostic mode. a circuit, a third switching circuit that switches the read/write designation signal to a read/write designation signal output by a diagnostic mode timing generation circuit when receiving the diagnostic mode, and stores the diagnostic data in the memory cell; 1. A semiconductor memory element comprising: a read data comparison circuit for comparing read diagnostic data; and a flip-flop for storing an error detected by the read data comparison circuit. (2) The semiconductor memory device according to claim 1, wherein the signal for requesting diagnosis is generated when power is turned on.