JP2007122853A - Semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a test method by which defect of a memory core of a semiconductor memory such as an SRAM can be tested in a short time. <P>SOLUTION: A test circuit 2 is connected to a memory core integrated unit 1 of SRAM. When the memory core integrated unit 1 is to be tested, a TEST start signal is set to high level. At the time, any one side of line out of a bit line BL or an inverted bit line BL_ of the memory core integrated unit 1 is used for writing data and data is set. The other bit line is used for reading data, the written data is inverted and set in the normal operation. It is decided that the memory core is normal by confirming that data set to the bit line BL and data set to the inverted bit line BL_ are inverted each other by EOR 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory such as an SRAM.

  Conventionally, when a semiconductor memory such as an SRAM (Static Random Access Memory) is manufactured and shipped, a write / read test is performed on a memory core, which is a portion that stores binary information of “0, 1” in the SRAM.

  In the write / read test to the memory core, first, a test pattern is created to determine which data is to be written to which memory core. Subsequently, the address of the memory core to which writing is performed is set in the writing mode. When an address is designated, a specific word line, bit line and anti-bit line corresponding to the address are selected, and data determined by a test pattern is written to the designated memory core.

When the writing is completed, the setting is changed to the reading mode, the address of the memory core that performed the writing is specified, and the written data is read. If the written data and the read data match, it is determined that the memory core is normally writing / reading. If the data does not match, it is determined that an abnormality has occurred in the memory core. . Note that Patent Documents 1 to 4 are known as prior art references relating to the present application.
Japanese Patent No. 3348632 JP 04-344399 A JP 2001-023400 A Japanese Patent Laid-Open No. 2001-210095

  In the SRAM, the memory core occupies most of the elements, and most of the defects also occur in the memory core. Therefore, a test method capable of inspecting the memory core for a short time is desirable. However, in the conventional write / read test, it is necessary to operate the peripheral circuit of the memory core and perform the series of write / read operations as described above even during the test of the memory core.

  In order to perform this series of operations, it takes time corresponding to several clocks at the operating frequency of the SRAM. In particular, when testing SRAM memory cores where LSI logic is deeply embedded, there are many peripheral circuits that need to be moved at the same time. Need to create. For this reason, there is a problem that it takes time to create a test pattern.

  The present invention has been made in view of the above circumstances, and an object thereof is to realize a semiconductor memory capable of inspecting a memory core for a defect in a short time in a semiconductor memory such as an SRAM.

  The present invention has been made to solve the above problems, and the invention according to claim 1 provides a plurality of memory cores, a plurality of word lines designating row addresses of the memory cores, and the row addresses. In the semiconductor memory, comprising: a row address designating means for designating and selecting the word line; and a double bit line to which data to be written to the memory core is added and data of the memory core is read out. The word line is designated by a designation means, a first logic level is added to one of the double bit lines, and the other data of the double bit line is data corresponding to the first logic level A determination procedure is performed to determine whether or not, and then the second logic level data is added to one of the double bit lines, and the other data of the double bit line is set to the second logic level. Perform a determination procedure whether the data to respond, a semiconductor memory which is characterized in that a test circuit is performed for all the word lines of the above operation.

  According to a second aspect of the present invention, there are provided a plurality of memory cores, a plurality of word lines for designating a row address of the memory core, and a row address designating unit for designating the row address and selecting the word line. And a double bit line from which data to be written to the memory core is added and data of the memory core is read out, and includes a word line designating circuit for designating the word line, the word line The word line is designated by a designation circuit, a first logic level is added to one of the double bit lines, and the other data of the double bit line is data corresponding to the first logic level A determination procedure is performed to determine whether or not, and then the second logic level data is added to one of the double bit lines, and the other data of the double bit line is set to the second logic level. A semiconductor memory is provided with a test circuit for performing a determination procedure for determining whether or not the data is corresponding data and performing the above-described operation for all word lines.

  Further, the invention according to claim 3 is the invention according to claim 1 or claim 2, wherein the determination procedure of the test circuit performs an exclusive OR operation on both data of the double bit line, The determination is performed based on the result of the exclusive OR operation.

  According to the present invention, when testing the memory core of the SRAM, since it is a method of directly writing and reading data to the bit line in the memory core, it is not necessary to operate the peripheral circuit. In addition, the procedure for writing to and reading from the memory core can be performed in a time corresponding to one clock at the operating frequency of the SRAM, and the time required for the test can be shortened.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the SRAM according to the embodiment of the present invention. In FIG. 1, a memory core integration unit 1 is an integration of 1-bit memory cores. The test circuit 2 is a circuit used when testing the SRAM.

  The address signal bus 30 is an input bus for an address of one memory core in the memory core integrated unit 1. The output data bus 31 is an output bus for data held in the memory core integrated unit 1. The input data bus 32 is an input bus for data to be written to the memory core integrated unit 1. The column decoder 33 decodes the lower 3 bits of the address data input from the address signal bus 30. The row decoder 34 (row address designating means) decodes the upper 5 bits of data input from the address signal bus 30.

  The column selector 35 writes the data input from the input data bus 32 to the memory core of the column decoded by the column decoder 33, and holds it in the memory core of the column decoded by the column decoder 33. Data to be read out and output to the output data bus 31. In addition, D in the figure is D-FF (Delayed Flip-Flop).

  FIG. 2 is a block diagram showing a 1-bit configuration of the memory core. In FIG. 2, a MOSFET 12 and a MOSFET 13 switch whether to perform a write (or read) operation to the memory core. The MOSFET 101, the MOSFET 102, the MOSFET 111, and the MOSFET 112 are responsible for the operation of holding 1-bit information.

  Here, MOSFET 101 and MOSFET 102 have a NOT circuit configuration, and similarly, MOSFET 111 and MOSFET 112 have a NOT circuit configuration. Therefore, in the following, one bit of the memory core is simplified and displayed as shown in FIG.

  The double bit lines, that is, the bit line BL and the anti-bit line BL_ are selected by column data, and data is set during write and read operations. The word line W is selected by row data, and a signal for switching ON / OFF of the MOSFET 12 and the MOSFET 13 flows therethrough. A 1-bit memory core is selected by a bit line BL, an anti-bit line BL_, and a word line W.

  Next, the operation of the above-described embodiment will be described with reference to FIGS. First, a write operation to the SRAM will be described. At the time of writing, address data indicating the address of the memory core to be written, input data to be written, a write permission signal (WEN signal) indicating whether writing is permitted, and a chip selection signal (CSN) designating the SRAM to be written. Signal) is input to the SRAM.

  The address data is represented by row data of upper 5 bits and column data of lower 3 bits. The column data is decoded by the column decoder 33 and output to the column selection unit, and the row data is decoded by the row decoder 34 and output to the memory core integration unit 1.

  The input data to be written is 8-bit data, and is output to the column selector 35 when the WEN signal and the CSN signal are at the low level. The column selection unit 35 selects the double bit line, the bit line BL, and the anti-bit line BL_ from the column data input from the column decoder 33, and writes the data to be written according to the input data to the double bit line, the bit line BL, and the anti-bit line. Set to BL_.

  Here, data in which logics are inverted to each other is set to the bit line BL and the anti-bit line BL_. For example, when 1 is written to the memory core, High is set to the bit line BL and Low is set to the anti-bit line BL_. Conversely, when 0 is written to the memory core, Low is set to the bit line BL and High is set to the anti-bit line BL_.

  In the memory core integrated unit 1, the word line specified by the input row data becomes High, and the MOSFET 12 and the MOSFET 13 of FIG. 2 connected to the word line are turned ON. At this time, the data set in the bit line BL and the counter bit line BL_ is output to the X point and the Y point.

  For example, when the bit line BL is set high and the anti-bit line BL_ is set low, the MOSFET 111 and the MOSFET 102 are turned on, the MOSFET 112 and the MOSFET 101 are turned off, and the X point is held high and the Y point is held low. When the writing is completed, the word line W changes from High to Low, and the MOSFET 12 and the MOSFET 13 are turned off.

Subsequently, a read operation from the SRAM will be described. At the time of reading, address data indicating the address of the memory core to be read, and whether to output for reading (OEN signal) are input to the SRAM. Also in the read operation, the bit line BL, the anti-bit line BL_, and the word line W are designated in the memory core integrated unit 1 from the address data as in the write operation, and the designated word line W is set to High. .

  When the designated word line W is set to High, the MOSFET 12 and the MOSFET 13 in FIG. 2 are turned on, and the data set at the X point and the Y point are output to the bit line BL and the bit line BL_, respectively.

  For example, when High is set at the X point and Low is set at the Y point, after the word line W becomes High, the bit line BL is set High and the anti-bit line BL_ is set Low. The column selection unit 35 reads the data set in the bit line BL and the anti-bit line BL_, and outputs the data to the output data bus 31 when the OEN signal is Low.

  The write and read operations during the normal operation of the SRAM have been described in detail above. Next, the procedure for testing the SRAM will be described with reference to FIGS. When testing the SRAM, a high level signal is input as a TEST signal (test switching signal) from an external device (not shown) to the test circuit 2.

  When the TEST signal becomes High, the MOSFET 20 and the MOSFET 21 in FIG. 4 are turned ON, and the test input signal test_in is input from the test circuit 2 to the bit line BL or the anti-bit line BL_ of the memory core integrated unit 1. The test input signal test_in is generated by a D-FF (Delayed Flip-Flop) 24 in the test circuit 2.

  At the same time, the connection between the memory core integration unit 1 and the column selection unit 35 is disconnected, and writing and reading operations via the column selection unit 35 are prohibited. Hereinafter, the selection of the address (word line W) of the memory core to which the test writing is performed from the test circuit 2 may be input from the outside via the row decoder 34 from the address signal bus 30, and will be described later. You may select in 5 circuits. Hereinafter, a test performed by selecting a word line using the circuit of FIG. 5 will be described.

  A procedure for generating the test input signal test_in input to the bit line BL or the anti-bit line BL_ from the test circuit 2 will be described with reference to the circuit diagram of FIG. In FIG. 5, the clock CK used in the SRAM is divided by ½ by a D-FF (Delayed Flip-Flop) 24 in the test circuit 2 to become a test input signal test_in. The test input signal test_in is output from the switch circuit 25 only to either the point A or the point B in FIG.

  On the other hand, the clock CK is input to the counter 341 of the test circuit 2, the most significant bit Qm of the output of the counter 341 is output to the switch circuit 25, and the second bit Q1 to the bit immediately before the most significant bit are the decoder. To 342. Note that the number of output bits of the counter is determined by the number of word lines W of the memory core integrated unit 1.

  The decoder 342 receives data from the counter 341 and outputs the data to the word lines W0, W1,... Of the memory core integrated unit 1 (word line designating circuit). Here, as for the output of the decoder 342, when the output of the counter 341 is 0 (clock CK is counted once) and 1 (clock CK is counted twice), W0 is High and the rest is Low. Is 2 (clock CK is counted 3 times) and 3 (clock CK is counted 4 times), W1 is High and the rest is Low. Thereafter, each time the counter 341 counts the clock CK twice, the word line that becomes High changes one by one.

  FIG. 6 is a diagram showing a circuit configuration of the switch circuit 25 of FIG. In FIG. 6, when Qm (S) of the output of the counter 341 is Low, the MOSFET 251 and the MOSFET 252 are ON, the MOSFET 253 and the MOSFET 254 are OFF, and the test input signal test_in is a point A in FIG. 4 (that is, the bit line BL). Is output.

  On the other hand, when Qm (S) of the output of the counter 341 is High, the MOSFET 251 and the MOSFET 252 are OFF, the MOSFET 253 and the MOSFET 254 are ON, and the test input signal test_in is to the point B in FIG. 4 (that is, the anti-bit line BL_). Is output.

  FIG. 7 is a timing chart of each signal flowing in the SRAM. 7A shows a clock CK, and FIG. 7B shows a test input signal test_in generated by dividing the clock CK by 1/2 by a D-FF (Delayed Flip-Flop) 24. The test input signal test_in passes through the switch circuit 25 and is output to the bit line BL or the anti-bit line BL_.

  When the test input signal test_in is output to the bit line BL via the MOSFET 20 (S is Low), the test is applied to the memory core connected to the word line W that is High at the output of the decoder 342 in FIG. Input signal test_in is output.

  When the output of the counter 341 in FIG. 5 is 0 to 1 (all Q1 to Qm-1 are Low), the word line W0 is High, that is, the MOSFET 12 and the MOSFET 13 in FIG. 4 are ON, and Qm (S) is Low. The test input signal test_in is output to the point A in FIG. 4, and the NOT circuit 10 inverts the logic of the test input signal test_in and transparently outputs it to the anti-bit line BL_. An output signal to the anti-bit line BL_ is a test output signal test_out shown in FIG. Here, the bit line BL is used for writing, and the anti-bit line BL_ is used for reading.

  The test input signal test_in (at this time point A in FIG. 4) and the test output signal test_out (at this time point B in FIG. 4) are the values of EOR (Exclusive OR, exclusive OR operation) 22 in FIG. Each is input to two input terminals. The output of the EOR 22 is (d) in FIG. When the output of the EOR 22 is detected by the D-FF 23 at the rising edge of the inverted clock CK_ (that is, the falling edge of the clock CK), the output TO of the D-FF 23 becomes High as shown in FIG.

  If there is a defect in the memory core and the test output signal test_out is not a signal obtained by inverting the logic of the test input signal test_in, the output TO of the D-FF 23 is Low, so that the defect can be detected. When the output of the counter 341 is 4 to 5, the word line W1 becomes High, and the next memory core failure can be detected. Thereafter, the test is performed in accordance with the counting up of the counter 341.

  As shown in FIG. 7, in the first cycle of the clock CK, the operation of writing High as the test input signal test_in from the bit line BL to the memory core of the word line W0 becomes a test of the memory of the word line W0 This is a test of the operation of writing Low as the test input signal test_in to the core. The test of the word line W1 is performed in the third and fourth cycles of the clock CK, and thereafter, the test is performed on all the word lines W in two cycles of the clock CK.

  When the test on all the word lines W is completed, the most significant bit Qm of the counter 341 in FIG. 5 becomes High, and thereafter, the test input signal test_in is output from the point B in FIG. 4 to the counter bit line BL_. . The test output signal test_out is point A in FIG. Similar to the test input from the bit line BL described above, the test is performed on each word line W in two cycles of the clock CK.

In the above, the test method was demonstrated regarding the memory core for 1 row. Similarly, memory cores in other columns can be tested.
FIG. 8 schematically shows an overall circuit diagram of the memory core integrated unit 1 and the test circuit 2. The memory core integration unit 1 includes a plurality of memory cores.

  A common test input signal test_in generated by the D-FF 24 of the test circuit 2 shown in FIG. 5 is supplied in parallel to a plurality of columns of memory cores. A switch circuit (switch circuit 25 shown in FIG. 5) for switching the input destination of the test input signal test_in between the bit line BL and the counter bit line BL_, and a circuit for detecting a test result (in FIG. 4) EOR22 and D-FF23) shown are provided for each column of memory cores.

  Further, switches (MOSFETs 20 and 21 shown in FIG. 4) for connecting the test circuit 2 and the memory core integrated unit 1 by the TEST signal are also provided for each column of the memory cores. Note that a switch circuit that disconnects the connection between the column selection unit 35 and the memory core integrated unit 1 by the TEST signal is included in the column selection unit 35.

  Further, the memory core integrated unit 1 is provided with a switch 800 that switches the connection destination of the word line W between the row decoder 34 and the decoder 342 of the test circuit 2 according to the TEST signal. The switch 800 connects the word line W and the row decoder 34 when the TEST signal is Low, and connects the word line W and the decoder 342 of the test circuit 2 when the TEST signal is High.

  Further, the test result output TO of each column of the memory core is supplied to the AND circuit 100. The AND circuit 100 takes a logical product of the test result outputs TO of all the columns and generates a test result output TOT for all the memory core columns. If the test result output TOT is always high, it is determined that the SRAM is normal. If the test result output TOT is low even once, it is determined that the SRAM is defective.

  In the present embodiment, a test for writing and reading both High and Low data is performed on all memory cores without operating peripheral circuits such as the column selection unit 35. Further, since the test signal used during the test is automatically generated from the clock CK, it is not necessary for the tester to prepare the test signal. Furthermore, since the operation of writing and reading one data to one memory core is completed in one clock, the test can be completed in a short time.

  As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included. For example, the word line selection at the time of the test may be input from the address signal bus 30 of FIG. 1 without using the decoder 342 of FIG. Further, the AND circuit 100 for outputting test results collected for all the columns of the memory core may be omitted, and the test results for each column may be output separately.

  The present invention is suitable for use in a semiconductor memory such as an SRAM.

1 is a block diagram showing a configuration of an SRAM according to an embodiment of the present invention. It is a block diagram showing a configuration of a 1-bit memory core. It is the block diagram which simplified and showed the memory core of 1 bit. FIG. 2 is a configuration diagram illustrating configurations of a memory core integrated unit 1 and a test circuit 2 in FIG. 1. FIG. 5 is a circuit diagram showing a circuit for generating an output signal to the bit line BL and the anti-bit line BL_ of FIG. FIG. 6 is a circuit diagram illustrating a circuit configuration of a switch circuit 25 in FIG. 5. It is a timing chart of each signal which flows in SRAM. 2 is an overall circuit diagram of a memory core integrated unit 1 and a test circuit 2. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory core integrated part, 2 ... Test circuit, 22 ... EOR, 23 * 24 ... D-FF, 25 ... Switch circuit, 33 ... Column decoder, 34 ... Row decoder (row address designation means), 35 ... Column selection part , 100 ... AND circuit, 341 ... counter, 342 ... decoder, 800 ... switch

Claims (3)

Multiple memory cores,
A plurality of word lines specifying row addresses of the memory cores;
Row address designating means for designating the row address and selecting the word line;
A double bit line from which data to be written to the memory core is added and data of the memory core is read;
In a semiconductor memory comprising:
Data in which the word line is designated by the row address designating means, a first logic level is added to one of the double bit lines, and the other data of the double bit line corresponds to the first logic level A determination procedure is performed to determine whether the second bit line is at a second logic level, and the other data on the second bit line is added to the second logic level. A semiconductor memory comprising a test circuit that performs a determination procedure for determining whether or not the data corresponds to the above and performs the above operation for all word lines. Multiple memory cores,
A plurality of word lines specifying row addresses of the memory cores;
Row address designating means for designating the row address and selecting the word line;
A double bit line from which data to be written to the memory core is added and data of the memory core is read;
In a semiconductor memory comprising:
A word line designating circuit for designating the word line; designating the word line by the word line designating circuit; adding a first logic level to one of the double bit lines; A determination procedure for determining whether or not the other data is data corresponding to the first logic level is performed, and then data of a second logic level is added to one of the double bit lines, A test circuit for performing a determination procedure for determining whether or not the other data of the heavy bit line is data corresponding to the second logic level and performing the above operation for all word lines is provided. Semiconductor memory.   2. The determination procedure of the test circuit, wherein an exclusive OR operation is performed on both data of the double bit line, and the determination is performed based on an operation result of the exclusive OR operation. The semiconductor memory according to claim 2.

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