JP2005201829A - Method of generating delay trouble test pattern for semiconductor integrated circuit, and method of inspecting delay trouble therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of generating a test pattern capable of conducting a dynamic test for each path in a semiconductor integrated circuit including a memory circuit. <P>SOLUTION: An objective trouble is selected from a data line of the memory circuit (step 101), the longest test-allowable path corresponding to the selected objective trouble is selected (step 102), an initialization pattern (step 103) and a transition pattern (step 104) of the longest test-allowable path are found, an initialization pattern (step 105) and a transition pattern (step 106) of an address line are found, an initialization pattern (step 107) and a transition pattern (step 108) of a control signal group are found, a value provided by reading out a value written in the memory circuit into an output set value scanning FF group is found as an expected value (step 109), and the patterns found in the steps 103-109 are generated as a serial pattern (step 110). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a test pattern generation method used for testing a semiconductor integrated circuit including a memory circuit, in particular, a test pattern generation method for detecting a path delay fault in a memory peripheral circuit, and an inspection method using the generated test pattern. It is about.

  As shown in FIG. 28, the actual operation test of the conventional memory circuit is performed on the input path to the memory M and the output path from the memory circuit M, the functional path (normal operation path) and the test path of the logic circuit section CC. An additional circuit (selector S) capable of switching (test AD, test DI, test NCE, test NRE, test NWE) is provided, the test path is selected by the selector S, and the memory BIST or from the outside This is done by applying a test pattern from the test path to the memory circuit M by direct access. The semiconductor integrated circuit shown in FIG. 28 replaces some of the flip-flops in the logic circuit section with scan flip-flops, and these flip-flops set the test flip-flops in the memory circuit M. Group (SFF group) and an output value setting scan flip-flop group (output value setting SFF group) that receives the output of the memory circuit M, and the scan flip-flops of these scan flip-flop groups are connected in series The circuit can be controlled and observed from outside the semiconductor integrated circuit. However, in the above test, the path from the SFF group to the memory circuit M and the path from the memory circuit M to the output value setting SFF group are not subject to the test.

Therefore, a test method has been developed that makes it possible to test a memory circuit including such a path. That is, an input path from the input terminal of the circuit to be inspected to the address input terminal of the memory circuit incorporated in the circuit to be inspected and an output path from the data output terminal of the memory circuit to the output pin of the circuit to be inspected are secured. The memory read address given to the address input terminal of the built-in memory circuit is switched from the input terminal of the circuit to be inspected to the address input terminal of the built-in memory circuit, and output until a preset time elapses after the read address of the built-in memory is switched A memory test (delay fault test) is performed by examining whether or not the signal value of the pin has changed (see, for example, Patent Document 1).
In order to test a path delay fault in an integrated circuit, it is necessary to form a test pattern. A test pattern sequence for testing a path delay fault in such an integrated circuit (generally, two test patterns v1 and v2 are required to test a delay fault, and the test pattern v2 is as shown in FIG. The test circuit must be generated in a circuit in which the combinational circuit is expanded at two times, and these two test patterns are called test pattern series). The path activation table shown in FIG. 30 and the implication table and figure shown in FIG. The logic value is generated by assigning the logic value to each signal line in the circuit to be inspected (logic circuit portion CC in FIGS. 28 and 29) according to the five-value logic shown in FIG. As shown in FIG. 32, S0 shown in FIGS. 30 and 31 is “0” in any of the patterns v1 and v2, S1 is “1” in any of the patterns v1 and v2, and U0 is “x” in the pattern v1. The pattern v2 is “0”, the U1 is “x” in the pattern v1, the pattern v2 is “1”, and xx indicates that both v1 and v2 are “x”.

  FIG. 30 (a) shows the other input signal value required to activate the circuit when the output state changes when one input of the AND gate changes from "0" to "1". In this case, “U1” may be set. Further, as shown in FIG. 30B, when one input of the OR gate changes from “1” to “0”, the other input is changed in order to change the output state (activate the circuit). “U0” may be set. In FIG. 30 (c), when one of the inputs of the AND gate or NAND gate and the OR gate or NOR gate rises from "0" to "1", it falls from "1" to "0". The other input signal values necessary to activate these gates in each case are shown.

  FIG. 31 (a) shows the output state in each combination when the inputs of the two input terminals x1 and x2 of the AND gate are any of S0, U0, S1, U1 and XX, respectively. For example, when x1 is S0 and x2 is U0, the pattern v1 = <0, x> and the pattern v2 = <0, 0>, indicating that the output is <0, 0> = S0. FIG. 31B shows the output state in each combination when the inputs of the two input terminals x1 and x2 of the NOR gate are any one of S0, U0, S1, U1 and XX, respectively. c) shows what the output of the output terminal z becomes when the input of the input terminal x of the inverter is S0, U0, S1, U1, XX.

  An example of an integrated circuit that tests for path delay faults using scan FFs is shown in FIG. In the integrated circuit of FIG. 33, the transition value setting SFF group is formed by the scan FFs 1 to 9, the initial value setting SFF group is formed by the scan FFs 11 to 18, and the scan FFs 1 to 9 and 11 to 18 are serially connected. The scan shift operation is performed when the scan enable signal is in the scan mode, and the normal operation is performed in the normal mode.

  As shown in FIG. 33, the output of the scan FF1 and the output of the scan FF2 are supplied to the AND gate g1, the output of the input terminal X1 and the scan FF3 are supplied to the AND gate g2, and the output of the scan FF4 and the output of the scan FF5 are The output from the input terminal X3 and the scan FF6 is supplied to the AND gate g6, the output from the scan FF7 and the input terminal X4 are supplied to the AND gate g7, and the outputs from the input terminal X5 and the scan FF9 are AND gates. The output of the AND gate g1 and the output of the AND gate g2 are supplied to the OR gate g3, the output of the OR gate g3 is supplied to the input of the scan FF11, and the output of the AND gate g2 is supplied to the input of the scan FF12. The output of the input terminal X2 and the AND gate g4 is supplied to the OR gate g5. The output of the OR gate g5 is supplied to the input of the scan FF 13, the output of the AND gate g4 is supplied to the input of the scan FF 14, and the output of the AND gate g6 and the output of the AND gate g7 are supplied to the OR gate g8. The output of the gate g7 is supplied to the input of the scan FF 16, the output of the OR gate g8 is supplied to the input of the scan FF 15, the output of the scan FF 8 and the output of the AND gate g9 are supplied to the OR gate g10, and the output of the OR gate g10 Is supplied to the input of the scan FF 17, and the output of the ADN gate g 9 is supplied to the input of the scan FF 18.

  Further, the output of the scan FF 13 is supplied to the NOT gate G2, the output of the scan FF 12 and the output of the NOT gate G2 are supplied to the NAND gate G1, the outputs of the NAND gate G1 and the scan FF 14 are supplied to the NAND gate G3, and the scan FF 17 Is supplied to the NOT gate G7, the output of the scan FF16 and the output of the NOT gate G7 are supplied to the NAND gate G8, the output of the NAND gate G8 and the output of the scan FF18 are supplied to the NAND gate G9, and the output of the scan FF11. The output of the NAND gate G3 is supplied to the NOR gate G4, the output of the scan FF 15 and the output of the NAND gate G3 are supplied to the NAND gate G5, and the output of the NOR gate G4 and the output of the NAND gate G5 are supplied to the NOR gate G6. , NOR The output of the bets G6 is supplied to the external terminal X6, the output of NAND gate G5 is supplied to the external terminal X7, the output of the NAND gate G9 is supplied to the external terminal X8.

In such a circuit, to generate a test pattern for a path delay fault of a rising transition from “0” to “1” in a path indicated by a bold line in the drawing, that is, scan FF13-G2-G1-G3-G5-X7. First, a transition signal is set for each signal line on the path under test as shown in FIG. 33, and then an input signal line (not on the path of the logic gate on the path as shown in FIG. A signal value for activating each gate of the path is set in the off-inputs using the path activation table shown in FIG. That is, an initialization pattern is formed in the scan FFs 11 to 18. The initialization pattern is <1,1,0,0, x, 1, x, x, x>. Next, as shown in FIG. 34 (b), in order to generate a transition pattern in the scan FFs 11-18, the value of each signal line of the combinational circuit using the scan SFFs 11-18 as a pseudo external output is determined. That is, transition patterns are formed in the scan FFs 1 to 9 and X1 to 5. The transition pattern is <x, x, 1, 1, 1, 1, x, x, x, 1, x, 1, x, x>. Therefore, in the example of FIG. 33, the test pattern series for testing the path delay fault indicated by the bold line in the figure is <scan FF1-9, scan FF11-18, X1-5> = <x, x, 1, 1, 1,1, x, x, x, 1,1,0,0, x, 1, x, x, x, 1, x, 1, x, x>. In this case, “x” can be assigned an arbitrary value of “0” or “1” (see, for example, Non-Patent Document 1).
JP-A-5-128015 Angela Krstic / Kwang-Ting (Tim) Cheng, “Delay Fault Testing for VLSI Circuits”, (publisher: Kluwer Academic Publishers), (published date: September 1, 1998), (cited page; pp.101-130 )

  In the conventional method of testing the memory circuit alone by switching the function path (normal operation path) and the test path shown in FIG. 28, since the memory portion is cut out from the circuit to be tested, the path in which the memory is actually used However, since the test contents are limited to static ones such as stuck-at faults, dynamic faults such as delay faults could not be detected. Therefore, it has been impossible to completely guarantee the operation of the product by performing dynamic tests on the memory address input, data input, data output, and control input paths.

  Further, in the method described in Patent Document 1, it is difficult to secure the input path and the output path, and it is further determined whether a delay fault has actually occurred in any of the input path, the memory, and the output path. It was difficult to do.

  The method described in Non-Patent Document 1 can detect a delay fault in a selected path. However, only such a detection method can delay all address inputs, data inputs, and memory control signal groups of a memory circuit. A test pattern for inspecting a failure cannot be generated, and not all delay failures can be reliably inspected.

  The present invention solves the above-described conventional problems, and uses a test pattern generation method capable of performing a dynamic test of each path of a semiconductor integrated circuit including a memory circuit, and the generated test pattern. The purpose is to provide an inspection method.

In order to achieve the above object, an invention according to claim 1 includes a memory circuit and a logic circuit portion connected to the memory circuit, and a part or all of the flip-flops of the logic circuit portion are formed as scan flip-flops. By using these scan flip-flops, an initial value setting scan flip-flop group for setting an initial value in the memory circuit and a transition value setting in the memory circuit via the initial value setting scan flip-flop group Forming a transition value setting scan flip-flop group to be performed and an output value setting scan flip-flop group receiving the output of the memory circuit, and connecting the scan flip-flops of the scan flip-flop group in series For semiconductor integrated circuits that enable control and observation inside the circuit from outside Te, wherein for detecting delay faults in the path memory circuit, a method of generating a test pattern of the scan flip-flop group and the logic circuit portion,
Selecting a target fault for generating the test pattern from a data line of the memory circuit; selecting a longest testable path corresponding to the selected target fault; and selecting the longest testable path selected. A step of obtaining a data line initialization pattern for initialization, a step of obtaining a data line transition pattern for activating the selected longest testable path, and an address for setting an address line of the memory circuit to a predetermined value Obtaining a pattern series; obtaining a control value pattern series for setting a control signal group of the memory circuit to a value writable to the memory; and a value of a data line of the memory circuit with respect to the obtained data line transition pattern And an address label of the memory circuit for the obtained address pattern series. When the address value of the address line of the memory circuit for the address pattern series is read after writing to the memory circuit with the control value of the memory circuit with respect to the value of the control pattern and the obtained control value pattern series A step of obtaining a value received by the output value setting scan flip-flop group from the memory circuit as an expected value of the target failure, the obtained data line initialization pattern, the data line transition pattern, the address pattern series, and the And a step of generating the control value pattern series and the expected value as a serial pattern of the scan flip-flop group.

As a result, a test pattern can be formed to detect a delay fault in a path connected to the data line of the memory circuit, and a delay fault inspection becomes possible.
According to a second aspect of the present invention, a memory circuit and a logic circuit unit connected to the memory circuit are provided, and some or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops, and these scan flip-flops The initial value setting scan flip-flop group for setting the initial value in the memory circuit, and the transition value setting scan flip-flop group for setting the transition value in the memory circuit via the initial value setting scan flip-flop group. A flip-flop group and an output value setting scan flip-flop group for receiving the output of the memory circuit are formed, and the scan flip-flops of the scan flip-flop group are serially connected to each other in the circuit from the outside of the semiconductor integrated circuit. In a semiconductor integrated circuit capable of controlling and observing, the logic circuit section Wherein for detecting delay faults path memory circuit, a method of generating a test pattern of the scan flip-flop group,
Selecting a target fault for generating the test pattern from an address line of the memory circuit; selecting a longest testable path corresponding to the selected target fault; and selecting the longest testable path selected. A step of obtaining an address line initialization pattern for initialization, a step of obtaining an address line transition pattern for activating the selected longest testable path, and data for setting a data line of the memory circuit to a predetermined value Obtaining a pattern series; obtaining a control value pattern series for setting a control signal group of the memory circuit to a value writable in the memory; a value of a data line of the memory circuit with respect to the obtained data pattern series; Address of the memory circuit for the obtained address line transition pattern The memory circuit when reading the value of the address line of the memory circuit with respect to the address line transition pattern after writing to the memory circuit with the value of in and the control value of the memory circuit with respect to the control value pattern series Obtaining the value received by the output value setting scan flip-flop group as the expected value of the target failure, the obtained address line initialization pattern, the address line transition pattern, the data pattern series, and the control value pattern series Generating the expected value as a serial pattern of the scan flip-flop group, obtaining an address different from the value of the address line of the memory circuit with respect to the address line transition pattern as an initialization address, and the data pattern system A step of obtaining data different from the value of the data line of the memory circuit as initialization data, and a value of the control signal group of the memory circuit capable of writing the initialization data to the initialization address. As a feature.

As a result, a test pattern can be formed to detect a delay fault in the path connected to the address line of the memory circuit, and a delay fault inspection becomes possible.
According to a third aspect of the present invention, there is provided a memory circuit and a logic circuit portion connected to the memory circuit, and a part or all of the flip-flops of the logic circuit portion are replaced with scan flip-flops. The initial value setting scan flip-flop group for setting the initial value in the memory circuit, and the transition value setting scan flip-flop group for setting the transition value in the memory circuit via the initial value setting scan flip-flop group. A flip-flop group and an output value setting scan flip-flop group for receiving the output of the memory circuit are formed, and the scan flip-flops of the scan flip-flop group are serially connected to each other in the circuit from the outside of the semiconductor integrated circuit. In a semiconductor integrated circuit capable of controlling and observing, the logic circuit section Wherein for detecting delay faults path memory circuit, a method of generating a test pattern of the scan flip-flop group,
Selecting a target fault for generating the test pattern from a data outline of the memory circuit; selecting a longest testable path corresponding to the selected target fault; and the selected testable Obtaining first memory initialization data for initializing the longest path; obtaining second memory initialization data for activating the selected longest testable path; and A step of obtaining a first memory initialization address for writing one memory initialization data, an address for writing the second memory initialization data in the memory circuit, and an address for writing the first memory initialization data Obtaining a second memory initialization address having a different address, and storing the first memory initialization data in the memory circuit; Obtaining a memory initialization control value for setting the second memory initialization data to a value writable to the memory circuit; an address for reading the first memory initialization data; and a control signal for the memory circuit Obtaining a data-out initialization pattern comprising a group value; obtaining a data-out transition pattern comprising an address for reading the second memory initialization data and a value of a control signal group of the memory circuit; A step of obtaining, as an expected value, a value received by the output value setting scan flip-flop group serving as an end point of the longest testable path activated by the data-out transition pattern, the data-out initialization pattern, and the data-out transition pattern; The expected value is generated as a serial pattern of the scan flip-flop group. It is characterized by a step of.

As a result, a test pattern can be formed to detect a delay fault of a path connected from the data outline of the memory circuit, and a delay fault inspection becomes possible.
According to a fourth aspect of the present invention, a memory circuit and a logic circuit unit connected to the memory circuit are provided, and a part or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops. The initial value setting scan flip-flop group for setting the initial value in the memory circuit, and the transition value setting scan flip-flop group for setting the transition value in the memory circuit via the initial value setting scan flip-flop group. A flip-flop group and an output value setting scan flip-flop group for receiving the output of the memory circuit are formed, and the scan flip-flops of the scan flip-flop group are serially connected to each other in the circuit from the outside of the semiconductor integrated circuit. In a semiconductor integrated circuit capable of controlling and observing, the logic circuit section Wherein for detecting delay faults path memory circuit, a method of generating a test pattern of the scan flip-flop group,
The step of selecting the longest testable path corresponding to the target failure that transitions from write disable to write enable of the write control signal of the memory circuit that generates the test pattern, and initialization of the selected longest testable path A step of obtaining a write enable initialization pattern to be performed; a step of obtaining a write enable transition pattern for activating the selected longest testable path; and an address pattern series for setting an address line of the memory circuit to a predetermined value. Determining a data pattern sequence for setting a data line of the memory circuit to a predetermined value; and determining a control value pattern sequence for setting a control signal group of the memory circuit to a value that can be written to the memory circuit. And a memory circuit for the obtained data pattern sequence The address of the memory circuit with respect to the address pattern sequence after writing to the memory circuit with the value of the data line and the value of the address line of the memory circuit with respect to the determined address pattern sequence and the determined write enable transition pattern A step of obtaining, as an expected value, a value received by the output value setting scan flip-flop group from the memory circuit when reading an address value of a line; and the obtained write enable initialization pattern sequence and the write enable transition pattern sequence Generating the address pattern series, the data pattern series, and the expected value as a serial pattern of the flip-flop group, and initializing and adding the address line value of the memory circuit to the address pattern series Obtaining the initialization data as data different from the value of the data line of the memory circuit for the data pattern series, and writing the initialization data into the memory circuit at the initialization address. And a step of obtaining a value of a control signal group of the memory circuit as a memory initialization control value.

  As a result, a test pattern can be formed to detect a delay fault when the path connected to the write enable line of the memory circuit transitions from a write disabled state to a writable state, thereby enabling a delay fault inspection.

The invention according to claim 5 includes a memory circuit and a logic circuit portion connected to the memory circuit, and a part or all of the flip-flops of the logic circuit portion are replaced with scan flip-flops, and these scan flip-flops The initial value setting scan flip-flop group for setting the initial value in the memory circuit, and the transition value setting scan flip-flop group for setting the transition value in the memory circuit via the initial value setting scan flip-flop group. A flip-flop group and an output value setting scan flip-flop group that receives the output of the memory circuit are formed, and the scan flip-flops of the scan flip-flop group are serially connected to each other in the circuit from the outside of the semiconductor integrated circuit. In the semiconductor integrated circuit that enables control and observation, the logic circuit section Wherein for detecting delay faults path memory circuit, a method of generating a test pattern of the scan flip-flop group,
The step of selecting the longest testable path corresponding to the target failure that makes a transition from writable to non-writable of the write control signal of the memory circuit that generates the test pattern, and the write enable that initializes the longest testable path Obtaining an initialization pattern; obtaining a write enable transition pattern for activating the longest testable path; obtaining a test pattern sequence for setting an address line of the memory circuit to a predetermined value; Obtaining a first memory initialization data to be written to a predetermined value in the memory circuit corresponding to the enable initialization pattern and the address pattern series; and the memory circuit corresponding to the write enable transition pattern and the address pattern series The second memory that writes to the predetermined value in the first Obtaining a data having a value different from that of the first memory initialization data, obtaining a control value pattern series for setting a control signal group of the memory circuit to a value writable to the memory circuit, and obtaining the obtained data Write to the memory circuit based on the value of the data line of the memory circuit for the first memory initialization data, the value of the address line of the memory circuit for the obtained address pattern series, and the obtained write enable initialization pattern. A step of obtaining, as an expected value, a value received by the output value setting scan flip-flop group from the memory circuit when the address value of the address line of the memory circuit with respect to the address pattern series is read after performing The write enable initialization pattern and the write rice Generating a transition pattern, the address pattern series, the first memory initialization data, the second memory initialization data, the control value pattern series, and the expected value as a serial pattern of the flip-flop group; It is characterized by having.

  As a result, a test pattern can be formed to detect a delay fault when the path connected to the write enable line of the memory circuit transits from writable to non-writable, thereby enabling a delay fault inspection.

According to a sixth aspect of the present invention, a memory circuit and a logic circuit unit connected to the memory circuit are provided, and some or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops. The initial value setting scan flip-flop group for setting the initial value in the memory circuit, and the transition value setting scan flip-flop group for setting the transition value in the memory circuit via the initial value setting scan flip-flop group. A flip-flop group and an output value setting scan flip-flop group for receiving the output of the memory circuit are formed, and the scan flip-flops of the scan flip-flop group are serially connected to each other in the circuit from the outside of the semiconductor integrated circuit. In the semiconductor integrated circuit that enables control and observation, the logic circuit section Wherein for detecting delay faults path memory circuit, a method of generating a test pattern of the scan flip-flop group,
The step of selecting the longest testable path corresponding to the target fault that transitions to the readable state from the unreadable read control signal of the memory circuit that generates the test pattern, and the initialization of the selected longest testable path A step of obtaining a read enable initialization pattern to be performed; a step of obtaining a read enable transition pattern for activating the selected longest testable path; and an address pattern series for setting an address line of the memory circuit to a predetermined value. Obtaining a data pattern sequence for setting a data line of the memory circuit to a predetermined value; and determining a value of the address line of the memory circuit with respect to the address pattern sequence for a control signal group of the memory circuit. And the memory circuit for the data pattern series A control value initialization pattern that is set to a value that can be written to the memory circuit by a value of the data line; and a control signal group of the memory circuit is transferred to the memory circuit for the address line of the memory circuit for the address pattern series Determining a control value transition pattern that is set to a value that can be read from the memory circuit according to a value and a value of the data line of the memory circuit with respect to the data pattern series; and a value of the data line of the memory circuit with respect to the data pattern series And the address line value of the memory circuit for the address pattern series and the address line address value of the memory circuit for the address pattern series after writing to the memory circuit by the read enable initialization pattern. A step of obtaining, as an expected value, a value received from the memory circuit by the output value setting scan flip-flop group from the memory circuit, a step of obtaining a value different from the expected value as an output setting value pattern, and the read enable initialization Pattern, read enable transition pattern, address pattern series, data pattern series, control value initialization pattern, control value transition pattern, output set value pattern, and expected value, serial number of scan flip-flop group And a step of generating as a pattern.

  As a result, a test pattern can be formed to detect a delay fault when the path connected to the read enable line of the memory circuit makes a transition from unreadable to readable, thereby enabling a delay fault inspection.

The invention according to claim 7 includes a memory circuit and a logic circuit portion connected to the memory circuit, and a part or all of the flip-flops of the logic circuit portion are replaced with scan flip-flops. The initial value setting scan flip-flop group for setting the initial value in the memory circuit, and the transition value setting scan flip-flop group for setting the transition value in the memory circuit via the initial value setting scan flip-flop group. A flip-flop group and an output value setting scan flip-flop group for receiving the output of the memory circuit are formed, and the scan flip-flops of the scan flip-flop group are serially connected to each other in the circuit from the outside of the semiconductor integrated circuit. In a semiconductor integrated circuit capable of controlling and observing, the logic circuit section Wherein for detecting delay faults path memory circuit, a method of generating a test pattern of the scan flip-flop group,
The step of selecting the longest testable path corresponding to the target failure that transitions from readable to non-readable of the read control signal of the memory circuit that generates the test pattern, and initialization of the selected longest testable path Obtaining a read enable initialization pattern to be performed; generating a read enable transition pattern for activating the longest testable path; and predetermined first memory initialization corresponding to the obtained read enable initialization pattern A step of obtaining an address, a step of obtaining a second memory initialization address corresponding to the obtained read enable transition pattern with a value different from the first memory initialization address, and the obtained first memory initialization address First memory initialization data for writing predetermined data into the memory circuit in FIG. Determining the second memory initialization data to be written to the memory circuit at the determined second memory initialization address with a value different from the first memory initialization data, and the memory circuit Determining a memory initialization control value pattern sequence for setting the control signal group of the first memory initialization data and the second memory initialization data to values that can be written to the memory circuit; Obtaining an address for reading the written first memory initialization data and a value of an initial value scan flip-flop group for setting a control signal group of the memory circuit; and a second memory initial value written to the memory circuit Of the transition value scan flip-flop group for setting the address for reading the digitized data and the control signal group of the memory circuit And a step of obtaining, as an expected value, a value received by the output value setting scan flip-flop group from the memory circuit when the data written in the memory circuit is read based on the value of the initial value scan flip-flop group. The read enable initialization pattern, the read enable transition pattern, the value of the initial value scan flip-flop group, the value of the transition value scan flip-flop group, and the expected value, and the scan flip-flop group And a step of generating as a serial pattern.

  As a result, a test pattern can be formed to detect a delay fault when the path connected to the read enable line of the memory circuit transitions from readable to non-readable, thereby enabling a delay fault inspection.

The invention according to claim 8 further includes a memory circuit, a memory test circuit, and a logic circuit unit connected to the memory circuit and the memory test circuit, wherein a part or all of the flip-flops of the logic circuit unit is a scan flip-flop. The initial value setting scan flip-flop group for setting the initial value in the memory circuit by these scan flip-flops, and the transition value of the transition value in the memory circuit through the initial value setting scan flip-flop group. A transition value setting scan flip-flop group for setting and an output value setting scan flip-flop group for receiving the output of the memory circuit are formed, and the scan flip-flops of the scan flip-flop group are serially connected to form a semiconductor. Enables control and observation inside the integrated circuit And the semiconductor integrated circuit, there is provided an inspection method for inspecting the presence or absence of a delay fault of the path of said memory circuit and the logic circuit portion,
A step of applying memory initialization data from the memory test circuit to the memory circuit; and a test pattern in the initial value setting scan flip-flop group, transition value setting scan flip-flop group, and output value setting scan flip-flop group A step of applying a clock to the memory circuit and the scan flip-flop group at an actual operation speed of the memory circuit, and a step of reading a value of the output value setting scan flip-flop group It is characterized by.

  Accordingly, the delay fault inspection is performed using the test pattern generated in the invention according to the second aspect, the third aspect, the third aspect, the fourth aspect, or the seventh aspect. It becomes possible to do.

  The present invention can test this path to detect its delay faults even when a memory circuit is present on the path in the circuit, thus ensuring dynamic operation in the circuit, and Reliability can be dramatically improved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, terms used in the specification are defined.
"Path, path delay time, path delay failure"
A signal transition path in the circuit is called a path. The time when the signal transitions from the input signal line to the output signal line of the path is called a path delay time. When the path delay time becomes larger than a predetermined value, the circuit does not operate normally. This is called a path delay fault.
"Longest path"
The longest path is a path having the longest signal transition time. For example, the longest path for the data line DI [0] of the memory circuit M indicates a path having the longest signal transition time from the output or external input of the scan FF to the data line DI [0] of the memory circuit M. Similarly, the longest path for the data out DO [0] of the memory circuit M indicates a path having the longest signal transition time from the data out DO [0] of the memory circuit M to the input or external output of the scan FF.
Testable path
The testable path indicates a path where a test pattern for the path delay fault can be generated.

Next, FIG. 1 shows an example of a memory circuit that uses the delay fault test pattern generation method and the delay fault inspection method for a semiconductor integrated circuit according to the present embodiment.
As shown in FIG. 1A, the address line of the memory circuit M is 3 bits of AD [2: 0], the data line is 3 bits of DI [2: 0], and the data outline is DO [2: 0]. 3 bits.

  When the chip enable signal NCE is “0”, access to the memory circuit M is possible. When the chip enable signal NCE is “1”, access to the memory circuit M is prohibited. Further, when the write enable signal NWE is “0”, the write operation to the memory circuit M is possible, and when the write enable signal NWE is “1”, the write operation to the memory circuit M is prohibited. Further, when the read enable signal NRE is “0”, the read operation to the memory circuit M is possible, and when the read enable signal NRE is “1”, the read operation to the memory circuit M is prohibited.

  When the write enable signal NWE is “0” and the read enable signal NRE is “0”, it is assumed that neither the write operation nor the read operation to the memory circuit M can be performed correctly, and the write enable signal NWE is “1”. When the read enable signal NRE is “1”, neither the write operation nor the read operation is performed on the memory circuit M, and the output of the data outline DO [2: 0] holds the previous state. .

  Further, the normal operation path and the test path can be switched to the address line AD [2: 0], the data line DI [2: 0], the control signal group (NCE, NWE, NRE), and the clock signal input line (CLK), respectively. Selectable selectors S1 to S10 are provided, and a memory test circuit T is formed by these selectors S1 to S10. For the other selectors S1 to S9 except the selector S10 of the clock signal input line, the test path is selected when the test mode signal is “L (0)”.

  The clock selected for the control signal of the selector S10 of the clock signal input line is shown in FIG. When the test mode signal is “L (0)”, the test clock is selected regardless of the value of the scan mode signal (scan enable signal), the test mode signal is “H (1)”, and the scan mode signal Is “L”, the scan clock is selected, and when the test mode signal is “H” and the scan mode signal is “H”, the normal operation clock is selected.

Hereinafter, a delay fault test pattern generation method and a delay fault inspection method for a semiconductor integrated circuit according to the present invention will be described.
[Embodiment 1]
As Embodiment 1, a test pattern generation method for inspecting a data line (DI) of a memory circuit M will be described.

  FIG. 2 is a circuit diagram showing a data line test pattern generation method according to the first embodiment. The integrated circuit shown in FIG. 2 is a circuit diagram of a logic circuit unit that forms the normal operation path of FIG. 1, and a part (or all) of the logic circuit unit may be replaced with a scan flip-flop (scan FF). ), And by these scan FFs, an initial value setting scan flip-flop group (scan FF group) for setting an initial value in the memory circuit M, and a transition value to the memory circuit M via the initial value setting scan FF group Are formed, and a transition value setting scan flip-flop group (scan FF group) and an output value setting scan flip-flop group (scan FF group) receiving the output of the memory circuit M are formed. Can be controlled and observed in the circuit from outside the semiconductor integrated circuit.

  As shown in FIG. 2, the output of the scan FF1 and the output of the scan FF2 are supplied to the AND gate g1, the output of the input terminal X1 and the scan FF3 are supplied to the AND gate g2, and the output of the scan FF4 and the output of the scan FF5 are The output of the input terminal X3 and the scan FF6 is supplied to the AND gate g6, the output of the scan FF8 and the input terminal X4 are supplied to the AND gate g7, and the outputs of the input terminal X5 and the scan FF9 are AND gates. g9 is supplied.

  Further, the output of the AND gate g1 and the output of the AND gate g2 are supplied to the OR gate g3, the output of the OR gate g3 is supplied to the scan FF11, the output of the AND gate g2 is supplied to the scan FF12, and AND with the input terminal X2. The output of the gate g4 is supplied to the OR gate g5, the output of the OR gate g5 is supplied to the scan FF 13, the output of the AND gate g4 is supplied to the scan FF 14, and the output of the AND gate g6 and the output of the AND gate g7 are OR gates. The output of the AND gate g7 is supplied to the scan FF16, the output of the OR gate g8 is supplied to the scan FF15, the output of the scan FF8 and the output of the AND gate g9 are supplied to the OR gate g10, and the OR gate g10 Is supplied to the scan FF 17 and the ADN gate g The output of is supplied to the scan FF 18.

  Further, the output of the scan FF 13 is supplied to the NOT gate G2, the output of the scan FF 12 and the output of the NOT gate G2 are supplied to the NAND gate G1, the outputs of the NAND gate G1 and the scan FF 14 are supplied to the NAND gate G3, and the scan. The output of FF17 is supplied to NOT gate G7, the output of scan FF16 and the output of NOT gate G7 are supplied to NAND gate G8, the output of NAND gate G8 and the output of scan FF18 are supplied to NAND gate G9, and the output of scan FF11 The output and the output of the NAND gate G3 are supplied to the NOR gate G4, the output of the scan FF15 and the output of the NAND gate G3 are supplied to the NAND gate G5, and the output of the NOR gate G4 and the output of the NAND gate G5 are supplied to the NOR gate G6. Is done.

  The output of the NOR gate G6 is supplied (inputted) to the selector S4 together with the test data line DI [0] (FIG. 1), the test mode signal is supplied as the control signal of the selector S4, and the output of the selector S4 is the memory circuit. M is supplied to the data line DI [0]. The NAND gate G5 is supplied with the test data line DI [1] (FIG. 1) to the selector S5, the test mode signal is supplied as a control signal for the selector S5, and the output of the selector S5 is the data line of the memory circuit M. DI [1] is supplied. Further, the output of the NAND gate G9 is supplied to the selector S6 together with the test data line DI [2] (FIG. 1), the test mode signal is supplied as the control signal of the selector S6, and the output of the selector S6 is the data of the memory circuit M. Supplied to line DI [2].

  The output of the scan FF 20 is supplied to the scan FF 23. The output of the scan FF 23 is supplied to the selector S7 together with the test chip enable NCE (FIG. 1). The test mode signal is supplied as a control signal for the selector S7. The output is supplied to the chip enable NCE of the memory circuit M. The output of the scan FF 21 is supplied to the scan FF 24, the output of the scan FF 23 is supplied to the selector S8 together with the test write enable NWE (FIG. 1), and the test mode signal is supplied as a control signal for the selector S8. The output is supplied to the write enable NWE of the memory circuit M. Further, the output of the scan FF 22 is supplied to the scan FF 25, the output of the scan FF 25 is supplied to the selector S9 together with the test read enable NRE (FIG. 1), and the test mode signal is supplied as a control signal of the selector S9. The output is supplied to the read enable NRE of the memory circuit M.

  Further, the output of the scan FF 26 is supplied to the scan FF 29, the output of the scan FF 29 is supplied to the input of the selector S1 together with the test AD [0] (FIG. 1), and the test mode signal is supplied as a control signal of the selector S1, The output of the selector S1 is supplied to the address line AD [0] of the memory circuit M. The output of the scan FF 27 is supplied to the scan FF 30, the output of the scan FF 30 is supplied to the selector S2 together with the test AD [1] (FIG. 1), the test mode signal is supplied as a control signal for the selector S2, and the selector S2 Is supplied to the address line AD [1] of the memory circuit M. Further, the output of the scan FF 28 is supplied to the input of the scan FF 31, the output of the scan FF 31 is supplied to the selector S3 together with the test AD [2] (FIG. 1), and the test mode signal is supplied as a control signal of the selector S3. The output of the selector S3 is supplied to the address line AD [2] of the memory circuit M.

  The data outline DO [0] of the memory circuit is connected to the input of the scan FF 32, the data outline DO [1] of the memory circuit M is connected to the input of the scan FF 33, and the data outline DO [2] of the memory circuit M is Connected to the input of the scan FF 34.

  The clock CLK, the test clock TCLK, and the scan clock SCLK are connected to the input of the selector 10, the test mode signal is connected as the control signal S1 of the selector S10, and the scan mode signal (scan enable signal) is connected to the selector S10. Connected as the control signal S2, the output of the selector 10 is supplied to the CLK of the memory circuit. As described above, the clock is selected and supplied to the CLK of the memory circuit by the test mode signal (control signal S1) and the scan mode signal (control signal S2).

  The scan FFs 1 to 9, 11 to 18, and 20 to 34 are configured to perform a scan shift operation when the scan enable signal is in the scan mode and perform a normal operation in the normal mode. The scan FFs 1 to 9, the scan FFs 20 to 22 and the scan FFs 26 to 28 constitute a transition value setting SFF group, and the scan FFs 11 to 18, the scan FFs 23 to 25, and the scan FFs 29 to 31 constitute an initial value setting SFF group. An output value setting SFF group is configured by the FFs 32 to 34.

Next, the processing procedure of the test pattern generation method for inspecting the data line (DI) will be described with reference to the flowchart shown in FIG.
Step-101
First, a target failure is selected from the data lines DI [2: 0] for the memory circuit M of the semiconductor integrated circuit to be inspected. This target failure may be selected manually, or may be created by automatically extracting from the circuit information by an electronic computer. For example, the transition rise of DI [1] in the data line in FIG. 2 (a delay fault rising from “0” to “1”) is selected as the target fault.
Step-102
Next, the longest testable path corresponding to the selected target failure is selected. For example, the longest testable path indicated by the bold line in FIG. 2, the scan FF 13 -G 2 -G 1 -G 3 -G 5 -DI [1] is selected. The method of selecting the longest testable path is described in the document “A. Murakami, S. Kajihara, T. Sasao, I. Pomeranz and SM Reddy,“ Selection of Potenrially Testable Path Delay Faults for Test generation, ”International Test Conf., Pp.376. -384, Oct.2000. "
Step-103
Next, a data line initialization pattern (test pattern) that provides an initial value for initializing the longest testable path is obtained. That is, the values of the initial value setting scan FF groups 11 to 18 in FIG. 2 are generated. The values of the initial value setting scan FF groups 11 to 18 at this time are <1, 1, 0, x, 1, x, x, x>, respectively. This is the data line initialization pattern.
Step-104
Subsequently, a data line transition pattern (test pattern) for activating the longest testable path is obtained. That is, the values of the transition value setting scan FF groups 1 to 9 and the input terminals X1 to X5 in FIG. 2 are generated. At this time, the values of the transition value setting scan FF groups 1 to 9 and the values of the input terminals X1 to X5 are <x, x, 1, 1, 1, 1, x, x, x, 1, x, 1, x, respectively. , X>. This is the data line transition pattern.
Step-105
Next, the value of the initial value setting scan FF group (address line initialization pattern) for setting an arbitrary value to the address line [2: 0] is obtained. For example, the values of the initial value setting scan FFs 29 to 31 are generated so that the address of the memory circuit becomes an arbitrary value AD [2: 0] = <0, 0, 0>. The values of the initial value setting scan FFs 29 to 31 at this time are <0, 0, 0>.
Step-106
Subsequently, the value of the transition value setting scan FF group (address line transition pattern) is obtained so that the value of the initial value setting scan FF group of the address line does not change. That is, the values of the transition value setting scan FFs 26 to 28 are generated. The value of the transition value setting scan FF at this time is <0, 0, 0>. The pattern generated in steps -105 and 106 becomes an address pattern series.
Step-107
Next, a value of an initial value setting scan FF group (control signal group initialization pattern) for setting a value in which the control signal group of the memory circuit is allowed to be written to the memory circuit is obtained. That is, the values of the initial value setting scan FFs 23 to 25 are generated so that the values <0, 0, 1> for permitting the write operation to NCE, NWE, and NRE, which are control signal groups of the memory circuit. The values of the initial value setting scan FFs 23 to 25 at this time are <0, 0, 1>.
Step-108
Next, the value of the transition value setting scan FF group (control signal group transition pattern) is obtained so that the value of the initial value setting scan FF group of the control signal group does not change. That is, a value is generated in the transition value setting scan FFs 20 to 22. The values of the transition value setting scan FFs 20 to 22 at this time are <0, 0, 1>. The pattern generated in steps 107 and 108 becomes a control value pattern series.
Step-109
Subsequently, an output set value scan FF group (output set value pattern) when the value written in the memory circuit M by the value of the transition value set scan FF is read as an arbitrary value of the address line set in step -105. ) As the expected value. For example, a value DO [2: 0] = <0,1,0> read from the address AD [2: 0] = <0,0,0> written in the memory circuit is output value setting scan FFs 32-34. The value <0, 1, 0> when received in the above is the expected value.
Step-110
Next, a data line initialization pattern, a data line transition pattern, an address pattern series, a control value pattern series, and an expected value are generated as shift patterns. That is, the value of the transition value setting scan FF group, the value of the initial value setting scan FF group, and the expected value are generated as a serial pattern. This completes the test pattern generation for the target failure.

An inspection method using the test pattern generated in this way will be described with reference to the flowchart of FIG. 4 and waveform diagrams at respective terminals of the memory circuit of FIG.
Step-201
First, the generated serial pattern is set in each scan FF by a scan shift operation. When a value is set in each scan FF in this scan shift operation, each terminal of the memory circuit has NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <0, 0, 0>, DI [2: 0] = <1, 0, 0>.
Step-202
Next, the scan mode signal is switched to the normal operation mode. The scan enable signal is set to “0”.
Step-203
Next, a clock is applied to the test target memory circuit M and the scan FF at the actual operation clock speed of the test target memory circuit M (initialization of the longest testable path). When the clock is input in this way, data <1, 0, 0> is written to the address <0, 0, 0> of the memory circuit M. At this time, DI [2: 0] = <1,1,1> is changed.
Step-204
Next, a clock is applied to the test target memory circuit M and the scan FF at the actual operation clock speed of the test target memory circuit M (the transition of the longest testable path). When the clock is input in this way, data <1, 1, 1> is written at address <0, 0, 0> of the memory circuit.
Step-205
Next, the value of the same address written to the test target memory circuit M is read. Change NWE = 1 and NRE = 0 and read the address <0, 0, 0> of the memory circuit. If no delay fault has occurred in the data line DI [1], the value <1, 1, 1> written in the memory circuit M is read out. However, if a delay fault has occurred, the value <0> written in the initialization pattern only for DI [1] is read.
Step-206
Next, the scan mode signal is switched to the scan mode. The scan enable signal is set to “1”.
Step-207
Subsequently, the value is shifted out to the external terminal by the scan shift operation and compared with the expected value. A scan shift operation is performed and an expected value comparison is performed. If a value different from the expected value is observed in the expected value comparison, it is determined that the test target failure has a delayed failure.

  According to the above processing procedure, the target fault is selected from the data line for the memory circuit of the semiconductor integrated circuit to be inspected, the longest testable path corresponding to the selected target fault is selected, and the longest testable path is initialized. A data line initialization pattern that provides an initial value for the data, then a data line transition pattern for activating the longest testable path, an address pattern series, a control value pattern series, and a transition value setting scan FF The value written in the memory circuit M by the value of the output line is obtained as the expected value of the output set value scan FF group when the value is read with an arbitrary value of the address line, and these data line initialization pattern and data line transition pattern , Address pattern series, control value pattern series and expected value, scan FF group serial pattern Then, this serial pattern is set in the transition value setting scan FF group and the initial value setting scan FF group, the clock signal is switched to the scan clock signal, and the address pattern series is generated. Whether the selected target fault has a delay fault by writing the data line initialization pattern and transition pattern data to the address set in, and then calling the value of the output value setting scan FF group and comparing it with the expected value Can be determined.

As described above, according to the first embodiment, a test pattern can be formed to detect a delay fault in a path connected to the data line of the memory circuit, and a delay fault inspection can be performed. Therefore, the dynamic operation in the integrated circuit (LSI) in which the memory circuit M exists can be guaranteed, and the reliability of the product can be greatly improved.
[Embodiment 2]
As a second embodiment, a test pattern generation method for inspecting an address line (AD) of a memory circuit M will be described.

  FIG. 6 is a circuit diagram showing a test pattern generation method for address lines in the second embodiment. The integrated circuit shown in FIG. 6 is a circuit diagram of the logic circuit section forming the normal operation path of FIG. 1, and the same transition value setting SFF group, initial value setting SFF group, and output value setting SFF group as in the first embodiment. It has. Differences from the first embodiment shown in FIG. 2 will be described.

  As shown in FIG. 6, the output of the NOR gate G6 is supplied to the selector S1 together with the test data line AD [0], the test mode signal is supplied as a control signal to the selector S1, and the output of the selector S1 is the memory circuit M Is supplied to the data line AD [0]. The NAND gate G5 is supplied to the selector S2 together with the test data line AD [1], the test mode signal is supplied as a control signal to the selector S2, and the output of the selector S2 is supplied to the data line AD [1] of the memory circuit M. Supplied. Further, the output of the NAND gate G9 is supplied to the selector S3 together with the test data line AD [2], the test mode signal is supplied as the control signal of the selector S3, and the output of the selector S3 is the data line AD [2 of the memory circuit M. ] Is supplied.

  The output of the scan FF 29 is supplied to the selector S4 together with the test DI [0], the test mode signal is supplied as a control signal for the selector S4, and the output of the selector S4 is supplied to the address line DI [0] of the memory circuit M. Is done. The output of the scan FF 30 is supplied to the selector S5 together with the test DI [1], the test mode signal is supplied as a control signal of the selector S5, and the output of the selector S5 is supplied to the address line DI [1] of the memory circuit M. Is done. Further, the output of the scan FF 31 is supplied to the selector S6 together with the test DI [2], the test mode signal is supplied as a control signal of the selector S6, and the output of the selector S6 is supplied to the address line DI [2] of the memory circuit M. Is done.

Next, a processing procedure of a test pattern generation method for inspecting an address line (AD) will be described with reference to a flowchart shown in FIG.
Step-301
First, the target failure is selected from the address line for the memory circuit M of the semiconductor integrated circuit to be inspected. This target failure may be selected manually, or may be created by automatically extracting from the circuit information by an electronic computer. For example, the transition rise (the delay fault from “0” to “1”) of AD [1] of the address line in FIG. 6 is selected as the target fault.
Step-302
Next, the longest testable path corresponding to the selected target failure is selected. When the address line AD [1] is selected, the longest testable path indicated by the bold line in FIG. 6, the scan FF 13-G2-G1-G3-G5-AD [1] is selected.
Step-303
Next, an address line initialization pattern that provides an initial value for initializing the longest testable path is obtained. That is, the values of the initial value setting scan FF groups 11 to 18 are generated. At this time, the values of the initial value setting scan FF groups 11 to 18 are <1, 1, 0, x, 1, x, x, x>, respectively. This is an address line initialization pattern.
Step-304
Subsequently, an address line transition pattern for activating the longest testable path is obtained. That is, the values of the transition value setting scan FF groups 1 to 9 and the input terminals X1 to X5 are generated. At this time, the values of the transition value setting scan FF groups 1 to 9 and the values of the input terminals X1 to X5 are <x, x, 1, 1, 1, 1, x, x, x, 1, x, 1, x, respectively. , X>. This is an address line transition pattern.
Step-305
Next, the value of the initial value setting scan FF group (data line initialization pattern) for setting an arbitrary value to the data line DI [2: 0] is obtained. For example, the values of the initial value setting scan FFs 29 to 31 are generated so that the data in the memory circuit M becomes an arbitrary value DI [2: 0] = <0, 0, 0>. The values of the initial value setting scan FFs 29 to 31 at this time are <0, 0, 0>.
Step-306
Next, the value of the transition value setting scan FF group (data line transition pattern) is obtained so that the value of the initial value setting scan FF group of the data line does not change. That is, the values of the transition value setting scan FFs 26 to 28 are generated. The value of the transition value setting scan FF at this time is <0, 0, 0>. The pattern generated in steps -305 and 306 becomes a data pattern series.
Step-307
Next, a value of an initial value setting scan FF group (control signal group initialization pattern) for setting a value in which the control signal group of the memory circuit is allowed to be written to the memory circuit is obtained. That is, the values of the initial value setting scan FFs 23 to 25 are generated so that the values <0, 0, 1> for permitting the write operation to NCE, NWE, and NRE, which are control signal groups of the memory circuit. The values of the initial value setting scan FFs 23 to 25 at this time are <0, 0, 1>.
Step-308
Subsequently, the value of the transition value setting scan FF group (control signal group transition pattern) is obtained so that the value of the initial value setting scan FF group of the control signal group does not change. That is, the values of the transition value setting scan FFs 20 to 22 are generated. The values of the transition value setting scan FFs 20 to 22 at this time are <0, 0, 1>. The pattern generated in Steps 307 and 308 is a control value pattern series.
Step-309
Next, the value of the output set value scan FF group (output set value pattern) when the value written in the memory circuit M by the value of the transition value set scan FF is read with the address line value set in step -304 is expected. Calculate as a value. The value DO [2: 0] = <0, 0, 0> read at the address AD [2: 0] = <1, 1, 1> written in the memory circuit M is output value setting scan FFs 32-34. The expected value is the value when
Step-310
Next, an address line initialization pattern, an address line transition pattern, a data pattern series, a control value pattern series, and an expected value are generated as a shift pattern of the scan FF group. That is, the values and expected values of the transition value setting scans FF1-9, 20-22, 26-28 and the initial value setting scans FF11-18, 23-25, 29-30 are generated as serial patterns.
Step-311
Next, an address obtained by inverting the address bit of the target failure of the memory circuit address with respect to the address line transition pattern is obtained as a memory initialization address. That is, a memory initialization address for initializing the memory circuit is generated. The value of the memory initialization address at this time is AD [2: 0] = <0 when the address AD [1] of the write address in the address line transition pattern is changed from “1” to the value “0”. 1, 0, 1>.
Step-312
Next, data different from the data of the memory circuit for the data pattern is obtained as memory initialization data. The memory initialization data at this time is set to an arbitrary value other than the write data DI [2: 0] = <0, 0, 0> in the transition pattern. In this embodiment, DI [2: 0] = <1,1,1>.
Step-313
Next, a value that can be written to the memory circuit is obtained as a memory initialization control value. The memory initialization control value at this time is set to a value that permits writing to the memory circuit. In this embodiment, NCE = 0, NWE = 0, and NRE = 1. The memory initialization address, the memory initialization data, and the memory initialization control value generated in Steps 311, 312, and 312 are the test path initialization pattern.

This completes the test pattern generation for the target failure.
The inspection method using the test pattern generated in this way will be described with reference to the flowchart of FIG. 8 and waveform diagrams at each terminal of the memory circuit of FIG.
Step-401
First, the test mode signal is set to the test mode. The test mode signal is set to “0” which is the test mode.
Step-402
Next, the generated initialization pattern of the test path is applied to initialize the memory circuit M. That is, writing from the test path to the memory circuit M is performed. At this time, the terminals of the memory circuit M are NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <1, 0, 1>, DI [2: 0] = <1, 1, 1>, and data <1, 1, 1> is written to address <1, 0, 1> of memory circuit M.
Step-403
Next, the scan enable signal (SE signal) is set to the scan mode. That is, the scan enable signal is set to the scan mode “1”.
Step-404
Next, the generated serial pattern is set in each scan FF by a scan shift operation. When a value is set in each scan FF by the scan shift operation, each terminal of the memory circuit has NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <1, 0, 0>, DI [ 2: 0] = <0, 0, 0>.
Step-405
Next, the scan enable signal (SE signal) and the test mode signal are set to the normal mode. That is, the scan enable signal is set to “0” which is the normal mode. Further, the test mode signal is set to “1” which is the normal mode.
Step-406
Next, a clock is applied to the test target memory circuit M and each scan FF at the actual operation clock speed of the test target memory circuit M (transition occurs in the longest testable path). When a clock is input, data <0, 0, 0> is written at address <1, 0, 0> of the memory circuit. At this time, AD [2: 0] = <1,1,1>.
Step-407
Next, a clock is applied to the test target memory circuit M and each scan FF at the actual operation clock speed of the test target memory circuit M (a value after transition of the longest testable path is written to the memory circuit). When the clock is input, data <0, 0, 0> is written to the address <1, 1, 1> of the memory circuit.
Step-408
Next, NRE = 0 and NWE = 1 of the memory circuit M are set, and the value of the address written to the test target memory circuit M is read. That is, the value of the address <1, 1, 1> of the memory circuit M is read by changing NWE = 1 and NRE = 0. If no delay fault has occurred in the data line AD [1], the data DI [2: 0] of the address AD [2: 0] = <1,1,1> written in the memory circuit with the memory initialization pattern = <0, 0, 0> is read. However, if a delay fault has occurred, the data DI [2: 0] = <1,1,1 of the value address AD [2: 0] = <1,0,1> written in the initialization pattern > Is read out.
Step-409
Next, the scan enable signal SE is set to the scan mode. That is, the scan enable signal is set to “1”.
Step-410
Next, the value of the output value setting scan FF group is shifted out to the external terminal by the scan shift operation and compared with the expected value. In the expected value comparison, when a value different from the expected value is observed, it is determined that the test target failure has a delayed failure.

  According to the above processing procedure, the target fault is selected from the address line for the memory circuit of the semiconductor integrated circuit to be inspected, the longest testable path corresponding to the selected target fault is selected, and the longest testable path is initialized. An address line initialization pattern for providing an initial value is obtained, an address line transition pattern for activating the longest testable path is obtained, a data pattern series and a control value pattern series are obtained, and a transition value setting scan FF is obtained. The value of the output set value scan FF group when the value written in the memory circuit M by the value of the address is read as the value of the address line is obtained as an expected value, and the address line initialization pattern, address line transition pattern, and data pattern series are obtained. And the control value pattern series and the expected value are generated as a serial pattern of the scan FF group. Then, a test pattern generation is generated, and an address obtained by inverting the address bit of the target failure of the address is obtained as a memory initialization address, and data different from the data of the memory circuit M for the data pattern series is obtained as memory initialization data. Further, a value that can be written to the memory circuit M is obtained as a memory initialization control value, and an initialization pattern of the test path is formed.

  Then, in the test mode, the initialization pattern of the test path is written to the memory circuit M, and then the serial pattern is set in the transition value setting scan FF group and the initial value setting scan FF group in the scan mode. By writing data pattern series data to the set address, taking out the value of the output value setting scan FF group, and comparing it with the expected value, it can be determined whether or not the selected target fault has a delay fault.

  As described above, according to the second embodiment, a test pattern can be formed to detect a delay fault in a path connected to the address line of the memory circuit, and a delay fault inspection can be performed. Therefore, the dynamic operation in the integrated circuit (LSI) in which the memory circuit M exists can be guaranteed, and the reliability of the product can be greatly improved.

In the second embodiment, the address AD [2: 0] is specified and the memory initialization pattern of the memory circuit is applied, but the initialization of all the memory circuits is the same. In this case, a delay fault test can be performed even when a plurality of delay faults occur.
[Embodiment 3]
As a third embodiment, a test pattern generation method for inspecting the data outline (DO) of the memory circuit M will be described.

  FIG. 10 is a circuit diagram showing a test pattern generation method for address lines in the third embodiment. The integrated circuit shown in FIG. 10 is a circuit diagram of the logic circuit section forming the normal operation path of FIG. 1, and the same transition value setting SFF group, initial value setting SFF group, and output value setting SFF group as in the first embodiment. It has.

  As shown in FIG. 10, the output of the scan FF1 and the output of the scan FF2 are supplied to the OR gate g3, the output of the input terminal X1 and the scan FF3 are supplied to the OR gate g5, and the output of the scan FF4 and the output of the scan FF5 are This is supplied to the AND gate g8, and the outputs of the input terminal X2 and the scan FF 6 are supplied to the OR gate g10.

  The output of the OR gate g3 is supplied to the scan FF11, the output of the scan FF2 is supplied to the scan FF12, the output of the OR gate g5 is supplied to the scan FF13, the output of the OR gate g8 is supplied to the scan FF14, and the scan FF5 Is supplied to the scan FF 15, the output of the OR gate g 10 is supplied to the scan FF 16, and the output of the scan FF 6 is supplied to the scan FF 17.

  Further, the output of the scan FF 13 is supplied to the NOT gate G2, the output of the scan FF 12 and the output of the NOT gate G2 are supplied to the NAND gate G1, the outputs of the NAND gate G1 and the scan FF 11 are supplied to the NOR gate G4, and the scan FF 14 The output and the output of the NAND gate G1 are supplied to the NAND gate G5, the output of the scan FF16 is supplied to the NOT gate G7, the output of the scan FF15 and the output of the NOT gate G7 are supplied to the NAND gate G8, and the output of the NAND gate G8 The output of the scan FF 17 is supplied to the NAND gate G9.

  The output of the NOR gate G4 is supplied to the selector S4 together with the test data line DI [0], the test mode signal is supplied as the control signal of the selector S4, and the output of the selector S4 is the data line DI [0] of the memory circuit M. ] Is supplied. The NAND gate G5 is supplied to the selector S5 together with the test data line DI [1], the test mode signal is supplied as a control signal for the selector S5, and the output of the selector S5 is supplied to the data line DI [1] of the memory circuit M. Supplied. Further, the output of the NAND gate G9 is supplied to the selector S6 together with the test data line DI [2], the test mode signal is supplied as a control signal for the selector S6, and the output of the selector S6 is the data line DI [2] of the memory circuit M. ] Is supplied.

  The output of the scan FF 20 is supplied to the scan FF 23, the output of the scan FF 23 is supplied to the selector S7 together with the test chip enable NCE, the test mode signal is supplied as a control signal of the selector S7, and the output of the selector S7 is a memory circuit. M is supplied to the chip enable NCE. The output of the scan FF 21 is supplied to the scan FF 24, the output of the scan FF 24 is supplied to the selector S8 together with the test write enable NWE, the test mode signal is supplied as a control signal of the selector S8, and the output of the selector S8 is a memory circuit. M is supplied to the write enable NWE. Further, the output of the scan FF 22 is supplied to the scan FF 25, the output of the scan FF 25 is supplied to the selector S9 together with the test read enable NRE, the test mode signal is supplied as a control signal of the selector S9, and the output of the selector S9 is a memory circuit. This is supplied to the M read enable NRE.

  Further, the output of the scan FF 26 is supplied to the scan FF 29, the output of the scan FF 29 is supplied to the selector S1 together with the test AD [0], the test mode signal is supplied as a control signal of the selector S1, and the output of the selector S1 is a memory. This is supplied to the address line AD [0] of the circuit M. The output of the scan FF 27 is supplied to the scan FF 30, the output of the scan FF 30 is supplied to the selector S 2 together with the test AD [1], the test mode signal is supplied as a control signal for the selector S 2, and the output of the selector S 2 is a memory It is supplied to the address line AD [1] of the circuit M. Further, the output of the scan FF 28 is supplied to the input of the scan FF 31, the output of the scan FF 31 is supplied to the selector S3 together with the test AD [2], and the test mode signal is supplied as a control signal of the selector S3. The output is supplied to the address line AD [2] of the memory circuit M.

  The data outline DO [0] of the memory circuit M and the data outline DO [1] of the memory circuit M are supplied to the NAND gate G10, and the data outline DO [1] of the memory circuit M and the data outline DO [2] of the memory circuit M are supplied. ] Is supplied to the AND gate G11, the output of the NAND gate G10 is connected to the input of the scan FF 32, the output of the NAND gate G10 is connected to the input of the NOT gate G12, and the output of the NOT gate G12 is connected to the input of the scan FF 33 The output of the NAND gate G11 is connected to the input of the scan FF 34.

  The clock CLK, the test clock TCLK, and the scan clock SCLK are respectively connected to the input of the selector 10, the test mode signal is connected as the control signal S1 of the selector S10, and the scan mode signal is connected as the control signal S2 of the selector S10. The output of the selector 10 is supplied to the CLK of the memory circuit. As described above, the clock is selected and supplied to the CLK of the memory circuit by the test mode signal (control signal S1) and the scan mode signal (control signal S2).

Next, the processing procedure of the test pattern generation method for inspecting the data outline (DO) will be described with reference to the flowchart shown in FIG.
Step-501
First, the target failure is selected from the data outline for the memory circuit M of the semiconductor integrated circuit to be inspected. This target failure may be selected manually, or may be created by automatically extracting from the circuit information by an electronic computer. For example, a transition rise (delay failure from “0” to “1”) of DO [0] in the data outline indicated by a bold line in FIG. 10 is selected as the target failure.
Step-502
Next, the longest testable path corresponding to the selected target failure is selected. When DO [0] in the data outline is selected, DO [0] -G10-G12-scan FF33 is selected as the longest testable path.
Step-503
Next, first memory initialization data for initializing the longest testable path is obtained. The data DO [2: 0] = <0, 0, 0>.
Step-504
Next, second memory initialization data for activating the longest test path is obtained. At this time, the data DO [2: 0] = <1, 1, 0>.
Step-505
Next, a first memory initialization address for writing the first memory initialization data is generated. For example, the first memory initial value address AD [2: 0] = <0, 0, 0>.
Step-506
Next, a second memory initialization address for writing the second memory initialization data is generated. For example, the second memory initialization address AD [2: 0] = <1,1,1>.
Step-507
Next, a memory initialization control value for writing the first memory initialization data and the second memory initialization data is generated. That is, the control values for writing the first memory initialization data and the second memory initialization data are NCE = 0, NWE = 0, and NRE = 1.
Step-508
Next, the address for reading the first memory initialization data and the value of the control signal group are generated in the initial value setting scan FF (data out initialization pattern is generated). That is, the initial value setting scan FFs 23 to 25 and 29 to 31 are readable so that AD [2: 0] = <0, 0, 0>, which is the address at which the first memory initialization data is written, can be read. Generate the value of. The values of the initial value setting scan FFs 23 to 25 and 29 to 31 at this time are <0, 1, 0, 0, 0, 0>.
Step-509
Next, an address for reading the second memory initialization data pattern and a value of the control signal group are generated in the transition value setting scan FF (data-out transition pattern is generated). That is, the values of the transition value setting scan FFs 20 to 22 and 26 to 28 are generated so that AD [2: 0] = <1,1,1>, which is the address at which the second memory initialization data is written, can be read. . The values of the transition value setting scan FFs 20 to 22 and 26 to 28 at this time are <0, 1, 0, 1, 1, 1>.
Step-510
Next, a value received by the output set value scan FF group (output set value pattern) when the second memory initialization data is read at the second memory initialization address is obtained as an expected value. That is, the value DO [2: 0] = <1, 1, 0> of the address AD [2: 0] = <1,1,1> read by the transition value setting scan FF is set to be output. The values read to the scan FFs 32 to 34 at this time are <0, 1, 0>. This value is the expected value.
Step-511
Next, a data-out initialization pattern, a data-out transition pattern, and an expected value are generated as shift patterns. That is, the values of the transition value setting scan FFs 20 to 22 and 26 to 28, the values of the initial value setting scan FFs 23 to 25, 29 to 31, and the expected value are generated as serial patterns, and the test pattern generation for the target failure is completed.

An inspection method using the test pattern generated in this way will be described with reference to the flowchart of FIG. 12 and waveform diagrams at each terminal of the memory circuit of FIG.
Step-601
First, the test mode signal is set to the test mode. The test mode signal is set to “0” which is the test mode.
Step-602
Next, the first memory initialization data is applied to the generated first memory initialization address, and the memory circuit is initialized. That is, the first memory initialization data is written from the test path to the memory circuit M. The respective terminals of the memory circuit M at this time are NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <0,0,0>, DI [2: 0] = <0,0, 0>, and data <0, 0, 0> is written to the address <0, 0, 0> of the memory circuit M.
Step-603
Next, the second memory initialization data is applied to the generated second memory initialization address, and the memory circuit is initialized. That is, the second memory initialization data is written from the test path to the memory circuit M. At this time, the terminals of the memory circuit M are NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <1,1,1>, DI [2: 0] = <1,1, 0>, and data <1, 1, 0> is written at address <1, 1, 1> of the memory circuit.
Step-604
Next, the scan enable signal is set to the scan mode. That is, the scan enable signal is set to the scan mode “1”.
Step-605
Next, the generated serial pattern is set in each scan FF by a scan shift operation. When a value is set in each scan FF by scan shift, each terminal of the memory circuit M has NCE = 0, NWE = 1, NRE = 0, AD [2: 0] = <0, 0, 0>, DI [ 2: 0] = <X, X, X>.
Step-606
Next, the scan enable signal (SE signal) and the test mode signal are set to the normal mode. That is, the scan enable signal is set to “0” which is the normal mode. Further, the test mode signal is set to “1” which is the normal mode.
Step-607
Next, a clock is applied to the test target memory circuit M and each scan FF at the scan clock speed (initialization of the longest testable path). When the clock is input, the data at the address <0, 0, 0> of the memory circuit M is read and <0, 0, 0> is output as the data out. At this time, AD [2: 0] = <1,1,1>.
Step-608
Next, a clock is applied to the test target memory circuit M and each scan FF at the actual operation clock speed of the test target memory circuit M (transition occurs in the longest testable path). When the clock is input, the data at the address <1, 1, 1> of the memory circuit is read and <1, 1, 0> is output as the data out.
Step-609
Next, a clock is applied to the test target memory circuit M and each scan FF at the actual operation clock speed of the test target memory circuit M (the value after transition of the longest testable path is taken into the output value setting scan FF group). If no delay fault has occurred in the data-out DO [1], the output value setting scan FFs 32 to 34 are <0, 1, 0>. However, if a delay fault has occurred, only the output value setting scan FF 33 becomes the value <0> written at the address AD [2: 0] = <0, 0, 0>.
Step-610
Next, the scan enable signal is set to the scan mode. That is, the scan enable signal is set to “1”.
Step-611
Next, the value is shifted out to the external terminal by the scan shift operation and compared with the expected value. In the expected value comparison, when a value different from the expected value is observed, it is determined that the test target failure has a delayed failure.

  According to the above processing procedure, the target fault is selected from the data outline for the memory circuit M of the semiconductor integrated circuit to be tested, the longest testable path corresponding to the selected target fault is selected, and the longest testable path is initialized. First memory initialization data is obtained, and then second memory initialization data for activating the longest test path is obtained. Then, a first memory initialization address for obtaining an address for writing the first memory initialization data is generated, and then a second memory initialization address for obtaining an address for writing the second memory initialization data Is generated.

  Next, a memory initialization control value for writing the first memory initialization data and the second memory initialization data is generated, and an address and a value of the control signal group are used for reading the first memory initialization data. Is generated in the initial value setting scan FF group (the first initialization pattern is generated), and the address for reading the second memory initialization data and the value of the control signal group are subsequently stored in the transition value setting scan FF group. Generate (generate a second initialization pattern).

Then, the value of the output set value scan FF group when the second memory initialization data is read at the second memory initialization address is obtained as an expected value.
Subsequently, the first initialization pattern and the second initialization pattern are generated as shift patterns of the initial value setting scan FF group and the transition value setting scan FF group (test pattern generation is generated).

  Then, in the test mode, the first memory initialization data is written into the memory circuit M, and then the second memory initialization data is written into the memory circuit M. Then, the serial pattern is set in the transition value setting scan FF group and the initial value setting scan FF group according to the scan mode, and the first memory initialization data and the second memory initialization data written by the scan clock signal are read, and the transition is performed. The value after the transition of the longest path that can be tested by the address setting of the value setting scan FF group is taken into the output value setting scan FF and compared with the expected value to determine whether the selected target fault has a delay fault Can do.

As described above, according to the third embodiment, a test pattern can be formed to detect a delay fault of a path connected to the data outline of the memory circuit, and a delay fault inspection can be performed. Therefore, the dynamic operation in the integrated circuit (LSI) in which the memory circuit M exists can be guaranteed, and the reliability of the product can be greatly improved.
[Embodiment 4]
As a fourth embodiment, a method for generating a test pattern of a write enable line at the time of “nonWrite → Write” at the time when the write enable NWE of the memory circuit M transitions from write disable to write enable will be described.

  FIG. 14 is a circuit diagram showing a write enable line test pattern generation method according to the fourth embodiment. The integrated circuit shown in FIG. 14 is a circuit diagram of the logic circuit unit forming the normal operation path of FIG. 1, and the same transition value setting SFF group, initial value setting SFF group, and output value setting SFF group as in the first embodiment. It has.

  The output of the scan FF1 and the output of the scan FF2 are supplied to the AND gate g3, the output of the scan FF2 is supplied to the scan FF12, the outputs of the input terminal X1 and the scan FF3 are supplied to the AND gate g5, and the input terminal X2 is supplied to the scan FF14. , The input terminal X3 is supplied to the scan FF15, the output of the scan FF4 and the output of the scan FF5 are supplied to the OR gate g8, the outputs of the input terminal X4 and the scan FF6 are supplied to the OR gate g10, The output is supplied to the scan FF 18, the output of the OR gate g3 is supplied to the scan FF 11, the output of the OR gate g5 is supplied to the scan FF 13, the output of the OR gate g8 is supplied to the scan FF 16, and the output of the OR gate g10 is This is supplied to the input of the scan FF 17.

  The output of the scan FF 13 is supplied to the NOT gate G2, the output of the scan FF 12 and the output of the NOT gate G2 are supplied to the NAND gate G1, the outputs of the NAND gate G1 and the scan FF 11 are supplied to the AND gate G10, and the scan FF 14 The output and the output of the scan FF 15 are supplied to the input of the NAND gate G5, the output of the scan FF 17 is supplied to the NOT gate G7, the output of the scan FF 16 and the output of the NOT gate G7 are supplied to the NAND gate G8, The output and the output of the scan FF 18 are supplied to the NAND gate G9.

  The output of the scan AND gate G10 is supplied to the selector S8 together with the test write enable NWE, the test mode signal is supplied as a control signal for the selector S8, and the output of the selector S8 is supplied to the write enable NWE of the memory circuit M. . The NAND gate G5 is supplied to the selector S7 together with the test chip enable NCE, the test mode signal is supplied as a control signal for the selector S7, and the output of the selector S7 is supplied to the chip enable NCE of the memory circuit M. Further, the output of the NAND gate G9 is supplied to the selector S9 together with the test read enable NRE, the test mode signal is supplied as a control signal of the selector S9, and the output of the selector S9 is supplied to the read enable NRE of the memory circuit M.

  Further, the output of the scan FF 20 is supplied to the scan FF 23, the output of the scan FF 23 is supplied to the selector S4 together with the test DI [0], the test mode signal is supplied as the control signal of the selector S4, and the output of the selector S4 is the memory. It is supplied to DI [0] of the circuit M. The output of the scan FF 21 is supplied to the input of the scan FF 24, the output of the scan FF 24 is supplied to the selector S5 together with the test DI [1], the test mode signal is supplied as a control signal of the selector S5, and the output of the selector S5 Is supplied to DI [1] of the memory circuit M. The output of the scan FF 22 is supplied to the scan FF 25, the output of the scan FF 25 is supplied to the selector S6 together with the test DI [2], the test mode signal is supplied as a control signal of the selector S6, and the output of the selector S9 is the memory. It is supplied to DI [2] of the circuit M.

  The output of the scan FF 26 is supplied to the scan FF 29, the output of the scan FF 29 is supplied to the selector S1 together with the test AD [0], the test mode signal is supplied as a control signal of the selector S1, and the output of the selector S1 is a memory. This is supplied to the address line AD [0] of the circuit M. The output of the scan FF 27 is supplied to the scan FF 30, the output of the scan FF 30 is supplied to the selector S 2 together with the test AD [1], the test mode signal is supplied as a control signal for the selector S 2, and the output of the selector S 2 is a memory It is supplied to the address line AD [1] of the circuit M. Further, the output of the scan FF 28 is supplied to the scan FF 31, the output of the scan FF 31 is supplied to the selector S3 together with the test AD [2], the test mode signal is supplied as a control signal of the selector S3, and the output of the selector S3 is a memory. This is supplied to the address line AD [2] of the circuit M.

  Further, the data outline DO [0] of the memory circuit M is connected to the input of the scan FF 32, the data outline DO [1] of the memory circuit M is connected to the input of the scan FF 33, and the data outline DO [2] of the memory circuit M is Connected to the input of the scan FF 34.

  The clock CLK, the test clock TCLK, and the scan clock SCLK are respectively connected to the input of the selector 10, the test mode signal is connected as the control signal S1 of the selector S10, and the scan mode signal is connected as the control signal S2 of the selector S10. The output of the selector 10 is supplied to the CLK of the memory circuit. As described above, the clock is selected and supplied to the CLK of the memory circuit by the test mode signal (control signal S1) and the scan mode signal (control signal S2).

Next, the processing procedure of the test pattern generation method “nonWrite → Write” for the write enable line NWE will be described with reference to the flowchart shown in FIG.
Step-701
First, the longest testable path corresponding to a failure that makes a transition from write disable to write enable to the write enabled memory circuit for the memory circuit M of the semiconductor integrated circuit under test is selected. For example, the scan FF 13 -G 2 -G 1 -G 10-is the longest testable path for the transition failure (delay failure from “1” to “0”) from write disable to write enable of the write enable NWE in FIG. Select NWE.
Step-702
Next, a write enable initialization test pattern that provides an initial value for initializing the longest testable path is obtained. That is, a value is generated in the initial value setting scan FFs 11 to 13 related to the longest testable path. The values of the initial value setting scan FFs 11 to 13 at this time are <1, x, 1>, respectively.
Step-703
Subsequently, a write enable transition test pattern for activating the longest testable path is obtained. That is, values are generated in the transition value setting scans FF1 to FF3 and the input terminal X1 related to the initial value setting scans FF11 to FF13. The values of the transition value setting scans FF1 to FF3 at this time and the value of the input terminal X1 are <0, 1, 0, 0>, respectively.
Step-704
Next, an address pattern series for setting an arbitrary value in the address line is obtained. For example, values are generated in the initial value setting scan FFs 29 to 31 and the transition value setting scan FFs 26 to 28 so that the address is an arbitrary value AD [2: 0] = <0, 1, 0>. The value at this time is <0, 1, 0, 0, 1, 0>.
Step-705
Subsequently, a data pattern series for setting an arbitrary value in the data line is obtained. For example, values are generated in the initial value setting scan FFs 23 to 25 and the transition value setting scan FFs 20 to 22 so that the data of the memory circuit becomes an arbitrary value DI [2: 0] = <0, 1, 0>. . <0, 1, 0, 0, 1, 0> at this time.
Step-706
Next, a control value pattern series for setting a value capable of writing the control signal group of the memory circuit M to the memory circuit M is obtained. That is, the initial value setting scan FFs 14 to 18 and the transition value setting scans FF4 to FF6 and the input terminal X2 are set so that the values <0, 1> for allowing the write operation to the control signals NCE and NRE of the memory circuit Generate a value for ~ X4. The values at this time are <1,1, x, x, 0, x, x, 0,1,1, x>.
Step-707
Next, the value of the output setting value scan FF group (output setting value pattern) when the value written in the memory circuit by the value of the transition value setting scan FF group is read with the address line value set in step -704 is obtained. Obtained as an expected value. That is, the value DI [2: 0] = <0, 1, 0> written in the memory circuit with the values set in the transition value setting scan FFs 20 to 22 and 26 to 28 is read from DO [2: 0]. The value is set in the output value setting scan FFs 32 to 34. The values of the output value setting scan FFs 32 to 34 at this time are <0, 1, 0>. The value at this time is assumed as the expected value.
Step-708
Next, a write enable initialization pattern series, a write enable transition pattern series, an address pattern series, a data pattern series, and an expected value are generated as serial patterns of the scan FF group. That is, the values set in the initial value setting scan FF group and the transition value setting scan FF group and the expected value are generated as a shift pattern.
Step-709
Subsequently, an address line value for the address pattern generated in step -704 is obtained as an initialization address. The memory initialization address at this time is the write address AD [2: 0] = <0, 1, 0> to the memory circuit in the address pattern series generated in step -704.
Step-710
Next, data different from the value of the data line for the data pattern generated in step -705 is obtained as initialization data. The memory initialization data at this time is set to an arbitrary value other than the write data DI [2: 0] = <0, 1, 0> to the memory circuit in the data pattern series generated in step -705. In this embodiment, DI [2: 0] = <1, 0, 1>.
Step-711
Subsequently, the memory initialization control value of the control signal group of the memory circuit is obtained so that the pattern generated in steps -709 and 710 can be written to the memory circuit. A value of a memory circuit control group for writing the memory initialization data generated in step -710 to the memory circuit with respect to the memory initialization address generated in step -709 is obtained. In this embodiment, NCE = 0, NWE = 0, and NRE = 1. In steps -709, 710, and 711, an initialization pattern of the test path of the memory circuit is generated.

This completes the test pattern generation for the target failure.
An inspection method using the test pattern generated in this way will be described with reference to the flowchart of FIG. 16 and waveform diagrams at each terminal of the memory circuit of FIG.
Step-801
First, the test mode signal is set to the test mode. That is, the test mode signal is set to “0” which is the test mode.
Step-802
Next, the generated test path initialization pattern (memory initialization address, memory initialization data, and memory initialization control value) is applied to initialize the memory circuit. That is, the memory initialization data is written from the test path to the memory initialization address of the memory circuit M. The respective terminals of the memory circuit M at this time are NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <0,1,0>, DI [2: 0] = <1,0, 1>, and data <1, 0, 1> is written to address <0, 1, 0> of the memory circuit M.
Step-803
Next, the scan enable signal (SE signal) is set in the scan mode. That is, the scan enable signal is set to “1” which is the scan mode.
Step-804
Next, the generated serial pattern is set in each scan FF by a scan shift operation. When a value is set in each scan FF in the scan shift operation, each terminal of the memory circuit has NCE = 0, NWE = 1, NRE = 1, AD [2: 0] = <0, 1, 0>, DI [ 2: 0] = <0, 1, 0>.
Step-805
Next, the scan enable signal and the test mode signal are set to the normal mode. That is, the scan enable signal is set to “0” which is the normal mode. Further, the test mode signal is set to “1” which is the normal mode.
Step-806
Next, a clock is applied to the test target memory circuit and the scan FF at the actual operation clock speed of the test target memory circuit M (non-write operation of the memory circuit M). When the clock is input, the write enable NWE = 0 is set.
Step-807
Next, a clock is applied to the test target memory circuit and the scan FF at the actual operation clock speed of the test target memory circuit (write operation of the memory circuit M). When the clock is input, the data DI [2: 0] = <0,1,0> of the address <0,1,0> of the memory circuit M is written into the memory circuit M.
Step-808
Next, NWE = 1 and NRE = 0 of the memory circuit M are set, and the value of the data at the address written in the transition pattern to the test target memory circuit is read. Address AD [2: 0] = <0, 1, 0> is read. When a delay failure has occurred in the write enable NWE, the write operation to the memory circuit is not performed normally, and the memory initialization data DI [2: 0] = <1, 0, 1> is read. If no delay fault has occurred, DI [2: 0] = <0, 1, 0> is read.
Step-809
Next, the scan enable signal is set to the scan mode. That is, the scan enable signal is set to “1”.
Step-810
Next, the value is shifted out to the external terminal by the scan shift operation and compared with the expected value. In the expected value comparison, when a value different from the expected value is observed, it is determined that the test target failure has a delayed failure.

  According to the above processing procedure, the target fault is selected from the data enable line for the memory circuit M of the semiconductor integrated circuit to be inspected, the longest testable path corresponding to the selected target fault is selected, and the longest testable path is initialized. An initialization test pattern that gives an initial value for the determination is obtained, and a transition test pattern for activating the longest testable path is obtained. Subsequently, an address pattern series for setting an arbitrary value on the address line is obtained, a data pattern series for setting an arbitrary value on the data line is obtained, and a control signal group of the memory circuit M can be written to the memory circuit M. A control value pattern series for setting a value is obtained. Next, the value of the output setting value scan FF group when the value written in the memory circuit by the value of the transition value setting scan FF is read by the address line value generated by the address pattern series is obtained as an expected value, and the initial value A serial pattern is generated based on the values set in the setting scan FF group and the transition value setting scan FF group and the expected value.

  Next, the address line value for the address pattern generated in the address pattern series is obtained as an initialization address, the data different from the data line value for the data pattern generated in the data pattern series is obtained as initialization data, and subsequently initialized. A memory initialization control value for obtaining a value of a control signal group of the memory circuit M is obtained so that data can be written into the memory circuit M, and an initialization pattern of a test path of the memory circuit M is generated.

  Then, in the test mode, the initialization pattern is written from the test path to the memory circuit M, and then the serial pattern is set in the transition value setting scan FF group and the initial value setting scan FF group in the scan mode. Is read out, and the data value at the address written in the transition pattern to the test target memory circuit M is read, and then it is taken into the output value setting scan FF and compared with the expected value, thereby delaying the selected target fault. It can be determined whether there is.

  As described above, according to the fourth embodiment, a test pattern can be formed to detect a delay fault of a path connected to a write enable in “nonWrite → Write” of the memory circuit M, and a delay fault inspection can be performed. . Therefore, the dynamic operation in the integrated circuit (LSI) in which the memory circuit M exists can be guaranteed, and the reliability of the product can be greatly improved.

In the fourth embodiment, the address AD [2: 0] is specified and the memory initialization data of the memory circuit is applied in the initialization of the memory circuit. It may be initialized to a value other than the data to be written.
[Embodiment 5]
As a fifth embodiment, a method for generating a test pattern for a write enable line in “Write → nonWrite” when the write enable NWE of the memory circuit M transitions from write enabled to write disabled will be described. The circuit diagram showing the test pattern generation method for the write enable line in the fifth embodiment is the same as that in the fourth embodiment (FIG. 14), and the description thereof is omitted.

The processing procedure of the write enable line test pattern generation method “Write → nonWrite” will be described with reference to the flowchart shown in FIG.
Step-1101
First, the longest testable path corresponding to a failure that transitions from write enable to write disable to the write enable memory circuit for the memory circuit M of the semiconductor integrated circuit to be tested is selected. For example, the scan FF 13 -G 2 -G 1 -G 10-is the longest testable path for the transition enable (delay failure from “0” to “1”) from write enable to write disable of the write enable NWE in FIG. Select NWE.
Step-1102
Next, a write enable initialization test pattern that provides an initial value (NWE = 0) for initializing the longest testable path is obtained. That is, a value is generated in the initial value setting scan FFs 11 to 13 related to the selected longest testable path. At this time, the values of the initial value setting scan FF groups 11 to 13 are <1, 1, 1>, respectively.
Step-1103
Subsequently, a write enable transition test pattern for activating the longest testable path is obtained. That is, values are generated in the transition value setting scans FF1 to FF3 and the input terminal X1 related to the initial value setting scans FF11 to FF13. The values of the transition value setting scans FF1 to 3 that give NWE = 1 and the value of the input terminal X1 are <1, 0, 1, x>, respectively.
Step-1104
Next, an address pattern series for setting an arbitrary value in the address line is obtained. For example, values are generated in the initial value setting scan FFs 29 to 31 and the transition value setting scan FFs 26 to 28 so that the address is an arbitrary value AD [2: 0] = <0, 1, 0>. The address pattern series at this time is <0, 1, 0, 0, 1, 0>.
Step-1105
Next, first memory initialization data to be written to a predetermined value is obtained in the memory circuit M corresponding to the write enable initialization pattern and the address pattern series. For example, the initial value setting scan FF 23 to the first memory initialization data DI [2: 0] = <0, 1, 0> written to the address AD [2: 0] = <0, 1, 0>. A value is generated at 25.
Step-1106
Next, second memory initialization data to be written to a predetermined value in the memory circuit M corresponding to the write enable transition pattern and the address pattern series is obtained with a value different from the first memory initialization data. For example, the transition value is set so that the data DI [2: 0] = <1, 0, 1> is different from the first memory initialization data written to the address AD [2: 0] = <0, 1, 0>. Values are generated in the scan FFs 20-22. The data pattern sequence generated by Step-1105 and Step-1106 is <1,0,1,0,1,0,0>.
Step-1107
Next, a control value pattern series for setting values that can write the control signal group of the memory circuit to the memory circuit is obtained. That is, the initial value setting scan FFs 14 to 18 and the transition value setting scans FF4 to FF6 and the input terminal X2 are set so that the values <0, 1> for allowing the write operation to the control signals NCE and NRE of the memory circuit Generate a value for ~ X4. The values at this time are <1,1, x, x, 0, x, x, 0,1,1, x>.
Step-1108
Next, the value of the output setting value scan FF group (output setting value pattern) when the value written in the memory circuit M by the value of the initialization setting scan FF group is read with the address line value set in Step-1104. As the expected value. That is, the value DI [2: 0] = <0, 1, 0> written in the memory circuit M by the values set in the initial value setting scan FFs 23 to 25 and 29 to 31 is read from DO [2: 0]. Are set in the output value setting scan FFs 32 to 34. The values of the output value setting scan FFs 32 to 34 at this time are <0, 1, 0>. The value at this time is assumed as the expected value.
Step-1109
Next, the write enable initialization pattern, the write enable transition pattern, the address pattern series, the first memory initialization data, the second memory initialization data, the control value pattern series, and the expected value are used as the serial pattern of the scan FF group. Generate. That is, the values set in the initial value setting scan FF group and the transition value setting scan FF group and the expected value are generated as a serial pattern.

This completes the test pattern generation for the target failure.
An inspection method using the test pattern generated in this way will be described with reference to the flowchart of FIG. 19 and waveform diagrams at each terminal of the memory circuit of FIG.
Step-1301
First, the scan enable signal (SE signal) is set to the scanned mode. That is, the scan mode signal is set to “1” which is the scan mode.
Step-1302
Next, the generated serial pattern is set in each scan FF by a scan shift operation. When a value is set in each scan FF by this scan shift operation, each terminal of the memory circuit has NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <0, 1, 0>, DI [2: 0] = <0, 1, 0>.
Step-1303
Next, the scan enable signal and the test mode signal are set to the normal mode. That is, the scan enable signal is set to “0” which is the normal mode. Further, the test mode signal is set to “1” which is the normal mode.
Step-1304
Next, a clock is applied to the test target memory circuit M and each scan FF at the actual operation clock speed of the test target memory circuit M (write operation of the memory circuit M). When the clock is input, data <0, 1, 0> is written to address <0, 1, 0>, and write enable NWE = 1 is set.
Step-1305
Next, a clock is applied to the test target memory circuit M and each scan FF at the actual operation clock speed of the test target memory circuit M (non-write operation of the memory circuit M). When a clock is input, the terminals of the memory circuit are AD [2: 0] = <0,1,0>, DI [2: 0] = <1,0,1>, and the address <0,1 , 0>, the data <1, 0, 1> of the second memory initialization pattern is about to be written into the memory circuit.
Step-1306
Next, NWE = 1 and NRE = 0 of the memory circuit are set, and the data value of the address written in the transition pattern to the test target memory circuit is read. Address AD [2: 0] = <0, 1, 0> is read. When a delay failure has occurred in the write enable NWE, the non-write operation to the memory circuit is not performed normally, and the rewritten data DI [2: 0] = <1, 0, 1> is read. If no delay fault has occurred, DI [2: 0] = <0, 1, 0> is read.
Step-1307
Next, the scan enable signal SE is set to the scan mode. Set the scan enable signal to "1".
Step-1308
Next, the value is shifted out to the external terminal by the scan shift operation and compared with the expected value. In the expected value comparison, when a value different from the expected value is observed, it is determined that the test target failure has a delayed failure.

  According to the above processing procedure, the target fault is selected from the data enable line NWE for the memory circuit of the semiconductor integrated circuit to be inspected, the longest testable path corresponding to the selected target fault is selected, and the longest testable path is initialized. An initialization test pattern that gives an initial value for the determination is obtained, and a transition test pattern for activating the longest testable path is obtained.

  Subsequently, an address pattern series for setting an arbitrary value in the address line is obtained, a data pattern series for setting the first memory initialization data and the second memory initialization data in the data line is obtained, and the memory circuit M A control value pattern series for setting the control signal group to a value that can be written to the memory circuit M is obtained. Next, the value of the output setting value scan FF group when the value written in the memory circuit M by the value of the initial value setting scan FF group is read by the address line value generated by the address pattern series is obtained as an expected value, A serial pattern is generated based on the values set in the initial value setting scan FF group and the transition value setting scan FF group and the expected value.

  Then, the serial pattern is set to the transition value setting scan FF group and the initial value setting scan FF group by the scan mode, data is written by the scan clock signal, and then, the test target memory circuit M is tried to be written by the transition value pattern. Whether the selected target fault has a delay fault by reading the data value, taking it into the output value setting scan FF, and comparing it with the expected value, that is, by confirming that the data is not rewritten in the transition value pattern Can be determined.

As described above, according to the fifth embodiment, a test pattern can be formed to detect a delay fault of a path connected to a write enable in “Write → nonWrite” of the memory circuit M, and a delay fault inspection can be performed. . Therefore, the dynamic operation in the integrated circuit (LSI) in which the memory circuit M exists can be guaranteed, and the reliability of the product can be greatly improved.
[Embodiment 6]
As a fourth embodiment, a method for generating a test pattern for a read enable line in “nonRead → Read” when the read enable NRE of the memory circuit M transitions from unreadable to readable will be described.

  FIG. 21 is a circuit diagram showing a test pattern generation method for read enable lines in the sixth embodiment. The integrated circuit shown in FIG. 21 is a circuit diagram of the logic circuit section forming the normal operation path of FIG. 1, and the same transition value setting SFF group, initial value setting SFF group, and output value setting SFF group as in the first embodiment. It has.

  The output of the scan FF1 and the output of the scan FF2 are supplied to the AND gate g3, the output of the scan FF2 is supplied to the scan FF12, the outputs of the input terminal X1 and the scan FF3 are supplied to the AND gate g5, and the input terminal X2 is supplied to the scan FF14. , The input terminal X3 is supplied to the scan FF15, the output of the scan FF4 and the output of the scan FF5 are supplied to the OR gate g8, the outputs of the input terminal X4 and the scan FF6 are supplied to the OR gate g10, The output is supplied to the scan FF 18, the output of the OR gate g3 is supplied to the input of the scan FF 11, the output of the OR gate g5 is supplied to the scan FF 13, the output of the OR gate g8 is supplied to the scan FF 16, and the OR gate g10 The output is supplied to the scan FF 17.

  The output of the scan FF 13 is supplied to the NOT gate G2, the output of the scan FF 12 and the output of the NOT gate G2 are supplied to the NAND gate G1, the outputs of the NAND gate G1 and the scan FF 11 are supplied to the AND gate G10, and the scan FF 14 The output and the output of the scan FF 15 are supplied to the input of the NAND gate G5, the output of the scan FF 17 is supplied to the NOT gate G7, the output of the scan FF 16 and the output of the NOT gate G7 are supplied to the NAND gate G8, and the output of the scan FF 18 Is supplied to the NOT gate G11, and the output of the NAND gate G8 and the output of the NOT gate G11 are supplied to the NAND gate G9.

  The output of the scan AND gate G10 is supplied to the selector S8 together with the test write enable NWE, the test mode signal is supplied as a control signal for the selector S8, and the output of the selector S8 is supplied to the write enable NWE of the memory circuit M. . The NAND gate G5 is supplied to the selector S7 together with the test chip enable NCE, the test mode signal is supplied as a control signal for the selector S7, and the output of the selector S7 is supplied to the chip enable NCE of the memory circuit M. Further, the output of the NAND gate G9 is supplied to the selector S9 together with the test read enable NRE, the test mode signal is supplied as a control signal of the selector S9, and the output of the selector S9 is supplied to the read enable NRE of the memory circuit M.

  The output of the scan FF 20 is supplied to the scan FF 23, the output of the scan FF 23 is supplied to the selector S4 together with the test DI [0], the test mode signal is supplied as the control signal of the selector S4, and the output of the selector S4 is the memory. It is supplied to DI [0] of the circuit M. The output of the scan FF 21 is supplied to the scan FF 24, the output of the scan FF 24 is supplied to the selector S5 together with the test DI [1], the test mode signal is supplied as the control signal of the selector S5, and the output of the selector S5 is the memory. It is supplied to DI [1] of the circuit M. Further, the output of the scan FF 22 is supplied to the scan FF 25, the output of the scan FF 25 is supplied to the selector S6 together with the test DI [2], the test mode signal is supplied as the control signal of the selector S6, and the output of the selector S9 is the memory. It is supplied to DI [2] of the circuit M.

  The output of the scan FF 26 is supplied to the scan FF 29, the output of the scan FF 29 is supplied to the selector S1 together with the test AD [0], the test mode signal is supplied as a control signal of the selector S1, and the output of the selector S1 is a memory. This is supplied to the address line AD [0] of the circuit M. The output of the scan FF 27 is supplied to the scan FF 30, the output of the scan FF 30 is supplied to the selector S 2 together with the test AD [1], the test mode signal is supplied as a control signal for the selector S 2, and the output of the selector S 2 is a memory It is supplied to the address line AD [1] of the circuit M. Further, the output of the scan FF 28 is supplied to the scan FF 31, the output of the scan FF 31 is supplied to the selector S3 together with the test AD [2], the test mode signal is supplied as a control signal of the selector S3, and the output of the selector S3 is a memory. This is supplied to the address line AD [2] of the circuit M.

  The data outline DO [0] of the memory circuit M is connected to the input of the scan FF 32, the data outline DO [1] of the memory circuit M is connected to the input of the scan FF 33, and the data outline DO [2] of the memory circuit M is Connected to the input of the scan FF 34.

  The clock CLK, the test clock TCLK, and the scan clock SCLK are respectively connected to the input of the selector 10, the test mode signal is connected as the control signal S1 of the selector S10, and the scan mode signal is connected as the control signal S2 of the selector S10. The output of the selector 10 is supplied to the CLK of the memory circuit. As described above, the clock is selected and supplied to the CLK of the memory circuit by the test mode signal (control signal S1) and the scan mode signal (control signal S2).

Next, the processing procedure of the test pattern generation method “nonRead → Read” of the read enable line NWE will be described with reference to the flowchart shown in FIG.
Step-901
First, the longest testable path for the transition from read enable to non-readable to the memory circuit M of the semiconductor integrated circuit to be tested is selected. For example, the scan FF 17 -G 7 -G 8 -G 9-is the longest testable path for the transition failure (delay failure from “1” to “0”) from the unreadable to readable state of the write enable NRE in FIG. Select NRE.
Step-902
Next, a read enable initialization test pattern that provides an initial value for initializing the longest testable path is obtained. That is, values are generated in the initial value setting scan FF groups 16-18. The values of the initial value setting scan FF groups 16 to 18 at this time are <1, 0, x>, respectively.
Step-903
Next, a read enable transition test pattern for activating the longest testable path is obtained. That is, values are generated in the transition value setting scan FF groups 4 to 6 and the input terminal X4. At this time, the values of the transition value setting scan FF groups 4 to 6 and the value of the input terminal X4 are <1, 1, 0, 1>, respectively.
Step-904
Next, an address pattern series for setting an arbitrary value in the address line is obtained.
Values are generated in the initial value setting scan FFs 29 to 31 and the transition value setting scan FFs 26 to 28 so that the address becomes an arbitrary value AD [2: 0] = <0, 1, 0>. The value at this time is <0, 1, 0, 0, 1, 0>.
Step-905
Next, a data pattern series for setting an arbitrary value in the data line is obtained. Values are generated in the initial value setting scan FFs 23 to 25 and the transition value setting scan FFs 20 to 22 so that the data of the memory circuit becomes an arbitrary value DI [2: 0] = <0, 1, 0>. <0, 1, 0, 0, 1, 0> at this time.
Step-906
Next, a control value (control signal group) initialization pattern for setting a value that can write the control signal group of the memory circuit to the memory circuit in the initial value scan FF is obtained. That is, values are generated in the initial value setting scan FFs 11 to 15 so that the values <0, 0> for permitting a write operation to the control signals NCE and NWE of the memory circuit. The values at this time are <0, x, x, 1, 1>.
Step-907
Next, a control value (control signal group) transition pattern for setting a value capable of reading the control signal group of the memory circuit from the memory circuit in the transition value scan FF is obtained. That is, values are generated at the transition value setting scans FF1 to FF3 and the input terminals X1 to X3 so that the values <0, 1> for permitting the read operation to the control signals NCE and NWE of the memory circuit. The value at this time is <1,1,0,1,1,1>.
Step-908
Next, the output set value scan FF (output setting) when the value written in the memory circuit by the value of the initial value setting scan FF group (read enable initialization pattern) is read with the address line value set in step -904. Value pattern) group values are obtained as expected values. That is, the value DI [2: 0] = <0, 1, 0> written in the memory circuit M by the values set in the initial value setting scan FFs 23 to 25 and 29 to 30 is read from DO [2: 0]. Are set in the output value setting scan FFs 32 to 34. The values of the output value setting scan FFs 32 to 34 at this time are <0, 1, 0>. The value at this time is assumed as the expected value.
Step-909
Next, the inverted value of the expected value is set as the value of the output setting value FF group (output value setting pattern) at the time of the test. A value different from the expected value generated in step -908 is obtained. Since the expected value is <0,1,0>, here the value is <1,0,1>.
Step-910
Next, a read enable initialization pattern, a read enable transition pattern, an address pattern series, a data pattern series, a control value initialization pattern, a control value transition pattern, an output set value pattern, and an expected value are generated as scan FF group serial patterns. To do. That is, the values set in the transition value setting scan FF, the initial value setting scan FF, and the output value setting scan FF, and the expected value are generated as a serial pattern.

This completes the test pattern generation for the target failure.
The inspection method using the test pattern generated in this way will be described with reference to the flowchart of FIG. 23 and the waveform diagrams at each terminal of the memory circuit of FIG.
Step-1001
First, the scan enable signal (SE signal) is set to the scan mode. That is, the scan mode signal is set to “1” which is the scan mode.
Step-1002
Next, the generated serial pattern is set in each scan FF by a scan shift operation. When a value is set in each scan FF in the scan shift operation, each terminal of the memory circuit has NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <0, 1, 0>, DI [ 2: 0] = <0, 1, 0>.
Step-1003
Next, the scan enable signal SE and the test mode signal are set to the normal mode. That is, the scan enable signal is set to “0” which is the normal mode. Further, the test mode signal is set to “1” which is the normal mode.
Step-1004
Next, a clock is applied to the test target memory circuit M and each scan FF at the actual operation clock speed of the test target memory circuit M (write operation of the memory circuit M). When a clock is input, data DI [2: 0] = <0,1,0> of address AD [2: 0] = <0,1,0> of the memory circuit is written. At this time, NRE = 0 and NWE = 1 are set.
Step-1005
Next, a clock is applied to the test target memory circuit M and each scan FF at the actual operation clock speed of the test target memory circuit M (read operation of the memory circuit M). When the clock is input, data at the address <0, 1, 0> of the memory circuit is read from the memory circuit. When a delay fault has occurred in the read enable NRE, the read operation to the memory circuit M is not performed normally, and the output set value FF groups 32 to 34 are <1, 0, 1> which are different from the expected values. ing. If no delay fault has occurred, DI [2: 0] = <0, 1, 0> is read.
Step-1006
Next, the scan enable signal is set to the scan mode. That is, the scan enable signal is set to “1” which is the scan mode.
Step-1007
Next, the value is shifted out to the external terminal by the scan shift operation and compared with the expected value. When a scan shift operation is performed and a value different from the expected value is observed in the expected value comparison, it is determined that there is a delay fault in the test target fault.

  According to the above processing procedure, the target fault is selected from the read enable line for the memory circuit of the semiconductor integrated circuit to be inspected, the longest testable path corresponding to the selected target fault is selected, and the longest testable path is initialized. A read enable initialization test pattern for obtaining an initial value for obtaining a read enable transition test pattern for activating the longest testable path is obtained. Subsequently, an address pattern series for setting an arbitrary value on the address line is obtained, a data pattern series for setting an arbitrary value on the data line is obtained, a control signal group of the memory circuit is written to the memory circuit, and then Then, a control value pattern series (control value initialization pattern and control value transition pattern) for setting values that can be read out is obtained. Next, the value of the output setting value scan FF group when the value written in the memory circuit by the value of the initial value setting scan FF group is read by the address line value generated by the address pattern series is obtained as an expected value. An inverted value of the value is obtained and set as a value of the output value scan FF group (output set value pattern), and a read enable initialization pattern, a read enable transition pattern, an address pattern series, a data pattern series, a control value initialization pattern, and a control value A serial pattern is generated based on the transition pattern, output set value pattern, and expected value.

  Then, the serial pattern is set in the transition value setting scan FF group, the initial value setting scan FF group, and the output setting value scan FF group in the scan mode, and the initial value pattern is written to the test target memory circuit M by the scan clock signal. It is possible to determine whether or not the selected target fault has a delay fault by reading the value of the address data, taking it into the output value setting scan FF, and comparing it with the expected value.

As described above, according to the sixth embodiment, a test pattern can be formed to detect a delay fault of a path connected to a read enable in “nonRead → Read” of the memory circuit M, and a delay fault inspection can be performed. . Therefore, the dynamic operation in the integrated circuit (LSI) in which the memory circuit M exists can be guaranteed, and the reliability of the product can be greatly improved.
[Embodiment 7]
As a seventh embodiment, a method for generating a test pattern for a write enable line in “READ → nonREAD” when the read enable NRE of the memory circuit M transitions from readable to unreadable will be described. The circuit diagram showing the test pattern generation method for the write enable line in the seventh embodiment is the same as that in the sixth embodiment (FIG. 21), and the description is omitted.

The processing procedure of the test pattern generation method “READ → nonREAD” of the read enable line will be described with reference to the flowchart shown in FIG.
Step-1201
First, the longest testable path for the transition from the read enable to the read impossible for the memory circuit M of the semiconductor integrated circuit to be inspected is selected. For example, the scan FF 17 -G 7 -G 8 -G 9-is the longest testable path for the transition enable (delay failure from “0” to “1”) from the readable to unreadable state of the write enable NRE in FIG. Select NRE.
Step-1202
Next, a read enable initialization test pattern that provides an initial value for initializing the longest testable path is obtained. That is, values are generated in the initial value setting scan FF groups 16 to 18 where NRE = 0. The values of the initial value setting scan FF groups 16 to 18 at this time are <x, 1, 0>, respectively.
Step-1203
Next, a read enable transition test pattern for activating the longest testable path is obtained. That is, values are generated in the transition value setting scan FF groups 4 to 6 and the input terminal X4 where NRE = 1. At this time, the values of the transition value setting scan FF groups 4 to 6 and the value of the input terminal X4 are <1, 1, 0, 0>, respectively.
Step-1204
Next, a first memory initialization address for reading the memory circuit M with the initialization pattern is obtained. For example, AD [2: 0] = <0, 1, 0>, which is a first memory initialization address for initializing the memory circuit M, is obtained.
Step-1205
Next, a second memory initialization address that is different from the first memory initialization address for reading out the memory circuit M with the transition pattern is obtained. For example, an address AD [2: 0] = <1, 0, 1> which is a second memory initialization address different from the first memory initialization address is obtained.
Step-1206
Next, first memory initialization data, which is data to be written to the memory circuit M at the first memory initialization address, is obtained. For example, the first memory initialization data DI [2: 0] = <1, written to the memory circuit M with the first memory initialization address AD [2: 0] = <0, 1, 0>. 1,1> is obtained.
Step-1207
Next, second memory initialization data, which is data to be written to the memory circuit M at the second memory initialization address and is different from the first memory initialization data, is obtained. For example, DI [2: 0] = <0, which is the second memory initialization data written to the memory circuit at the address AD [2: 0] = <1, 0, 1>, which is the second memory initialization address. Find 0,0>.
Step-1208
Next, a memory initialization control value for setting in the initial value scan FF a value capable of reading the control signal group of the memory circuit from the memory circuit is obtained. That is, in order to write the first and second memory initialization data to the first and second memory initialization addresses, respectively, to allow the write operation to the control signal group NCE and NWE of the memory circuit. NCE, NWE = <0,0> is obtained. Steps-1204 to 1208 form a first memory initialization pattern and a second memory initialization pattern for the test path.
Step-1209
Next, the value of the initial value setting scan FF group is set to read the first memory initialization data written to the address of the first memory initialization pattern. A value is generated in the initial value setting scan FFs 11 to 15 and 29 to 31 with NCE and NWE = <0, 1> so that the data of the first memory initialization address can be read from the memory circuit M. The values of the scan FFs at this time are <1, 0, x, 1, 1, 0, 1, 0>.
Step-1210
Next, the value of the transition value setting scan FF group is set in order to read the second memory initialization data written to the address of the second memory initialization pattern. That is, the transition value setting scans FF1 to FF3, 26 to 28 and the input terminals X1 to X1 are set to NCE, NWE = <0,1> so that the data of the second memory initialization address can be read from the memory circuit. Generate a value for X3. At this time, the value of each scan FF and the value of the input terminal are <1, 0, x, 1, 0, 1, x, 1, 1>.
Step-1211
Next, the value of the output set value scan FF group (output set value pattern) when the value written in the memory circuit M by the first memory initialization pattern is read by the address line value set in Step-1204 is expected. Calculate as a value. That is, the value <1, 1, 1> written to the memory circuit M at the first memory initialization address AD [2: 0] = <0, 1, 0> is read from DO [2: 0]. The output value setting scan FFs 32 to 34 are set. At this time, the values of the output value setting scan FFs 32 to 34 are <1, 1, 1>. The value at this time is assumed as the expected value.
Step-1212
Next, a read enable initialization pattern, a read enable transition pattern, an initial value setting scan FF group value, a transition value setting scan FF group value, and an expected value are generated as a serial pattern of the scan FF group.

An inspection method using the test pattern generated in this way will be described with reference to the flowchart of FIG. 25 and waveform diagrams at each terminal of the memory circuit of FIG.
Step 1401
Set the test mode signal to test mode. The test mode signal is set to “0” which is the test mode.
Step-1402
Next, the memory circuit is initialized by applying the first memory initialization pattern and the second memory initialization pattern generated in steps -1204 to -1207.

That is, first, the memory circuit M is written from the test path to the memory circuit M using the first memory initialization address pattern, the first memory initialization data pattern, and the memory initialization control value. The respective terminals of the memory circuit M at this time are NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <0,1,0>, DI [2: 0] = <1,1, 1>, and data <1,1,1> is written at address <0,1,0> of the memory circuit. Subsequently, the memory circuit M is written from the test path to the memory circuit using the second memory initialization address pattern, the second memory initialization data pattern, and the memory initialization control value. The respective terminals of the memory circuit M at this time are NCE = 0, NWE = 0, NRE = 1, AD [2: 0] = <1,0,1>, DI [2: 0] = <0, 0, 0>, and data <0, 0, 0> is written at address <1, 0, 1> of the memory circuit.
Step-1403
Next, the scan enable signal (SE signal) is set in the scan mode. That is, the scan enable signal is set to “1” which is the scan mode.
Step-1404
Next, the generated serial pattern is set in each scan FF by a scan shift operation. When a value is set in each scan FF by the scan shift operation, each terminal of the memory circuit has NCE = 0, NWE = 1, NRE = 0, AD [2: 0] = <0, 1, 0>, DI [ 2: 0] = <x, x, x>.
Step-1405
Next, the scan enable signal and the test mode signal are set to the normal operation mode. The scan enable signal is set to “0” which is the normal mode. Further, the test mode signal is set to “1” which is the normal mode.
Step-1406
Next, a clock is applied to the test target memory circuit M and the scan FF at the actual operation clock speed of the test target memory circuit M (read operation of the memory circuit M). When the clock is input, DO [2: 0] = <1,1,1> of the address <0,1,0> is output, and then the address AD [2: 0] = <1 of the memory circuit M is output. , 0, 1>, NRE = 1, and NWE = 1.
Step-1407
Next, a clock is applied to the test target memory circuit M and each scan FF at the actual operation clock speed of the test target memory circuit M (access operation to the memory circuit M “read operation occurs when a delay fault occurs”). When a clock is input, if a delay fault has occurred in the read enable NRE, a read operation to the memory circuit M is performed, and the output set values FF groups 32 to 34 store the DO [ 2: 0] = <0, 0, 0>. If no delay fault has occurred, the read operation to the memory circuit M is not performed, and the output set value FF groups 32 to 34 = <D0 for D0 [2: 0] = <1,1,1> read in step 1406. 1,1,1> is maintained.
Step-1408
Next, the scan enable signal is set to the scan mode. Set the scan enable signal to "1".
Step-1409
Next, the value is shifted out to the external terminal by the scan shift operation and compared with the expected value. When a scan shift operation is performed and a value different from the expected value is observed in the expected value comparison, it is determined that there is a delay fault in the test target fault.

  According to the above processing procedure, the target fault is selected from the read enable line for the memory circuit of the semiconductor integrated circuit to be inspected, the longest testable path corresponding to the selected target fault is selected, and the longest testable path is initialized. A read enable initialization test pattern for obtaining an initial value for obtaining a read enable transition test pattern for activating the longest testable path is obtained. Subsequently, a first memory initialization pattern and a second memory initialization pattern are formed (a data pattern for obtaining an address pattern series for setting an arbitrary value in the address line and setting an arbitrary value in the data line) A series is obtained, and a control signal group for writing the data pattern series to the memory circuit M is obtained). Next, the value of the output set value scan FF group when the value written in the memory circuit M by the first memory initialization pattern is read by the address line value generated by the address pattern series is obtained as an expected value. Subsequently, a control signal group for reading values written in the memory circuit M by the first memory initialization pattern and the second memory initialization pattern is obtained, and values of the initial value setting scan FF group including these control signal groups are obtained. A serial pattern is generated based on the value of the transition value setting scan FF group, the read enable initialization pattern, the read enable transition pattern, and the expected value.

  Then, the first memory initialization pattern and the second memory initialization pattern are written to the memory circuit M in the test mode, and the serial patterns are set in the transition value setting scan FF group and the initial value setting scan FF group in the scan mode. The data value at the address written in the first memory initial value pattern to the test target memory circuit M is read, and the written data is taken into the output value setting scan FF group and selected by comparing with the expected value. It can be determined whether there is a delay fault in the target fault.

  As described above, according to the seventh embodiment, a test pattern can be formed to detect a delay fault in a path connected to a read enable at the time of “Read → nonRead” of the memory circuit M, and a delay fault inspection can be performed. . Therefore, the dynamic operation in the integrated circuit (LSI) in which the memory circuit M exists can be guaranteed, and the reliability of the product can be greatly improved.

  In the first to seventh embodiments, the values of the data line, the address line, or the control signal group are set by the scan shift operation using serial patterns for the initial value setting scan FF and the transition value setting scan FF. However, it is also possible to set from a test path or a memory test circuit.

  In the first to seventh embodiments, the control signal group is set to NCE, NWE, and NRE. However, other control terminals can be written to any address of the memory circuit or can be read from any address of the memory circuit. This can be achieved.

  In the first to seventh embodiments, the data-out value is incorporated into the output setting scan FF group, the value of the output terminal is observed by the scan shift operation, and the expected value is compared. It is also possible to observe the output from the test path and compare the expected value, or compare the expected value with a test circuit.

  Further, according to the first to seventh embodiments, even if the memory circuit M exists on the path in the integrated circuit (LSI), the delay test on the path can be performed. It is possible to guarantee the dynamic operation and improve the reliability of the product remarkably, but by using the static function test as described in the conventional technology together, it is possible to guarantee the dynamic operation in the circuit. It is possible to dramatically improve the reliability of the product by performing both static operation guarantees at the same time.

  According to the delay fault test pattern generation method and the delay fault inspection method of a semiconductor integrated circuit according to the present invention, even if a memory circuit exists on the path in the circuit, the path fault is tested and the delay fault is detected. Therefore, it is possible to guarantee the dynamic operation in the circuit, and to improve the reliability of the product drastically, and it can be applied to new development or improvement of the semiconductor integrated circuit.

1 is a diagram showing a memory circuit and a memory test circuit that use a delay fault test pattern generation method and a delay fault test method for a semiconductor integrated circuit according to a first embodiment of the present invention, and a clock control diagram of the memory test circuit. It is a circuit diagram which shows the test pattern generation method of the data line of the memory circuit. It is a figure which shows the test pattern production | generation method of the data line of the memory circuit. It is a figure which shows the test | inspection method of the data line of the memory circuit. It is a timing chart showing a data line inspection method of the memory circuit. FIG. 10 is a circuit diagram showing a test pattern generation method for an address line of a memory circuit using a delay fault test pattern generation method for a semiconductor integrated circuit and a delay fault inspection method in Embodiment 2 of the present invention; It is a figure which shows the test pattern generation method of the address line of the memory circuit. It is a figure which shows the inspection method of the address line of the memory circuit. 4 is a timing chart showing an address line inspection method of the memory circuit. FIG. It is a circuit diagram which shows the test pattern generation method of the data outline of the memory circuit which uses the delay fault test pattern generation method and delay fault inspection method of the semiconductor integrated circuit in Embodiment 3 of this invention. It is a figure which shows the test pattern generation method of the data outline of the memory circuit. It is a figure which shows the test method of the data outline of the memory circuit. It is a timing chart showing a data outline inspection method of the memory circuit. FIG. 10 is a circuit diagram showing a test pattern generation method for a write enable line of a memory circuit using a delay fault test pattern generation method for a semiconductor integrated circuit and a delay fault inspection method in Embodiment 4 of the present invention. It is a figure which shows the test pattern production | generation method of the write enable line of the memory circuit. It is a figure showing the inspection method of the write enable line of the memory circuit. 4 is a timing chart showing a write enable line inspection method for the memory circuit. FIG. It is a figure which shows the test pattern generation method of the write enable line of the memory circuit which uses the delay fault test pattern generation method of a semiconductor integrated circuit in Embodiment 5 of this invention, and a delay fault inspection method. It is a figure showing the inspection method of the write enable line of the memory circuit. 4 is a timing chart showing a write enable line inspection method for the memory circuit. FIG. It is a circuit diagram which shows the test pattern generation method of the read enable line of the memory circuit which uses the delay fault test pattern generation method and delay fault inspection method of the semiconductor integrated circuit in Embodiment 6 of this invention. It is a figure which shows the test pattern production | generation method of the read enable line of the memory circuit. It is a figure which shows the test | inspection method of the read enable line of the memory circuit. FIG. 4 is a timing chart showing a read enable line inspection method for the same memory circuit. It is a figure which shows the test pattern generation method of the read enable line of the memory circuit which uses the delay fault test pattern generation method of a semiconductor integrated circuit and the delay fault inspection method in Embodiment 7 of this invention. It is a figure which shows the test | inspection method of the read enable line of the memory circuit. FIG. 4 is a timing chart showing a read enable line inspection method for the same memory circuit. It is a circuit diagram which shows a memory peripheral circuit. It is a circuit diagram which shows the structure which expanded the memory peripheral circuit for 2 time. It is a figure which shows the path | route activation table used for a test pattern production | generation. It is a figure which shows the implication table used for a test pattern production | generation. It is a figure which shows the quinary logic used for a test pattern production | generation. It is a figure which shows an example of the test pattern generation method of a path delay fault. It is a figure which shows an example of the test pattern generation method of a path delay fault.

Explanation of symbols

1-9 Scan flip-flop 11-18 Scan flip-flop 20-34 Scan flip-flop S1-S10 Selector circuit X1-X5 Input terminal X6-X8 Output terminal

Claims (8)

A memory circuit and a logic circuit unit connected to the memory circuit, and a part or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops; An initial value setting scan flip-flop group for setting, a transition value setting scan flip-flop group for setting a transition value in the memory circuit via the initial value setting scan flip-flop group, and an output of the memory circuit Integrated circuit that forms an output value setting scan flip-flop group that receives power and connects the scan flip-flops of these scan flip-flops serially to enable control and observation inside the semiconductor integrated circuit In, the delay of the path between the logic circuit portion and the memory circuit To detect the disabled, a method of generating a test pattern of the scan flip-flop group,
Selecting a target fault for generating the test pattern from a data line of the memory circuit;
Selecting the longest testable path corresponding to the selected target fault;
Obtaining a data line initialization pattern to initialize the selected longest testable path;
Obtaining a data line transition pattern for activating the selected longest testable path;
Obtaining an address pattern series for setting an address line of the memory circuit to a predetermined value;
Obtaining a control value pattern series for setting a control signal group of the memory circuit to a value writable to the memory;
The value of the data line of the memory circuit with respect to the determined data line transition pattern, the value of the address line of the memory circuit with respect to the determined address pattern series, and the control value of the memory circuit with respect to the determined control value pattern series, When the address value of the address line of the memory circuit with respect to the address pattern series is read after writing to the memory circuit, the value that the output value setting scan flip-flop group receives from the memory circuit is the target failure. The process of obtaining the expected value of
Generating the obtained data line initialization pattern, the data line transition pattern, the address pattern series, the control value pattern series, and the expected value as a serial pattern of the scan flip-flop group;
A method for generating a delay fault test pattern for a semiconductor integrated circuit, comprising: A memory circuit and a logic circuit unit connected to the memory circuit, and a part or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops; An initial value setting scan flip-flop group for setting, a transition value setting scan flip-flop group for setting a transition value in the memory circuit via the initial value setting scan flip-flop group, and an output of the memory circuit Integrated circuit that forms an output value setting scan flip-flop group that receives power and connects the scan flip-flops of these scan flip-flops serially to enable control and observation inside the semiconductor integrated circuit In, the delay of the path between the logic circuit portion and the memory circuit To detect the disabled, a method of generating a test pattern of the scan flip-flop group,
Selecting a target failure for generating the test pattern from an address line of the memory circuit;
Selecting the longest testable path corresponding to the selected target fault;
Obtaining an address line initialization pattern for initializing the selected longest testable path;
Obtaining an address line transition pattern for activating the selected longest testable path;
Obtaining a data pattern series for setting a data line of the memory circuit to a predetermined value;
Obtaining a control value pattern series for setting a control signal group of the memory circuit to a value writable to the memory;
The value of the data line of the memory circuit for the determined data pattern series, the value of the address line of the memory circuit for the determined address line transition pattern, and the control value of the memory circuit for the control value pattern series are transferred to the memory circuit. When the value of the address line of the memory circuit with respect to the address line transition pattern is read after the writing of the output value, the value received by the output value setting scan flip-flop group from the memory circuit is set as the expected value of the target failure. The desired process;
Generating the obtained address line initialization pattern, the address line transition pattern, the data pattern series, the control value pattern series, and the expected value as a serial pattern of the scan flip-flop group;
Obtaining an address different from the value of the address line of the memory circuit for the address line transition pattern as an initialization address;
Obtaining data different from the value of the data line of the memory circuit for the data pattern series as initialization data;
Obtaining a value of a control signal group of the memory circuit capable of writing the initialization data to the initialization address as an initialization control value;
A method for generating a delay fault test pattern for a semiconductor integrated circuit, comprising: A memory circuit and a logic circuit unit connected to the memory circuit, and a part or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops; An initial value setting scan flip-flop group for setting, a transition value setting scan flip-flop group for setting a transition value in the memory circuit via the initial value setting scan flip-flop group, and an output of the memory circuit Integrated circuit that forms an output value setting scan flip-flop group that receives power and connects the scan flip-flops of these scan flip-flops serially to enable control and observation inside the semiconductor integrated circuit In, the delay of the path between the logic circuit portion and the memory circuit To detect the disabled, a method of generating a test pattern of the scan flip-flop group,
Selecting a target fault for generating the test pattern from a data outline of the memory circuit; and
Selecting the longest testable path corresponding to the selected target fault;
Obtaining first memory initialization data for initializing the selected longest testable path;
Obtaining second memory initialization data for activating the selected longest testable path;
Obtaining a first memory initialization address for writing the first memory initialization data to the memory circuit;
Obtaining a second memory initialization address in which an address for writing the second memory initialization data to the memory circuit is different from an address for writing the first memory initialization data;
Obtaining a memory initialization control value for setting the first memory initialization data and the second memory initialization data in the memory circuit to values that can be written to the memory circuit;
Obtaining a data-out initialization pattern comprising an address for reading the first memory initialization data and a value of a control signal group of the memory circuit;
Obtaining a data-out transition pattern comprising an address for reading the second memory initialization data and a value of a control signal group of the memory circuit;
Obtaining as an expected value a value received by the output value setting scan flip-flop group serving as an end point of the longest testable path activated by the data-out transition pattern;
Generating the data-out initialization pattern, the data-out transition pattern, and the expected value as a serial pattern of the scan flip-flop group;
A method for generating a delay fault test pattern for a semiconductor integrated circuit, comprising: A memory circuit and a logic circuit unit connected to the memory circuit, and a part or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops; An initial value setting scan flip-flop group for setting, a transition value setting scan flip-flop group for setting a transition value in the memory circuit via the initial value setting scan flip-flop group, and an output of the memory circuit Integrated circuit that forms an output value setting scan flip-flop group that receives power and connects the scan flip-flops of these scan flip-flops serially to enable control and observation inside the semiconductor integrated circuit In, the delay of the path between the logic circuit portion and the memory circuit To detect the disabled, a method of generating a test pattern of the scan flip-flop group,
Selecting the longest testable path corresponding to a target failure that makes a transition to a writable state from a non-writable write control signal of the memory circuit that generates the test pattern;
Obtaining a write enable initialization pattern for initializing the selected longest testable path;
Obtaining a write enable transition pattern for activating the selected longest testable path;
Obtaining an address pattern series for setting an address line of the memory circuit to a predetermined value;
Obtaining a data pattern series for setting a data line of the memory circuit to a predetermined value;
Obtaining a control value pattern series for setting a control signal group of the memory circuit to a value writable to the memory circuit;
After writing to the memory circuit by the value of the data line of the memory circuit for the determined data pattern series and the value of the address line of the memory circuit for the determined address pattern series and the determined write enable transition pattern Obtaining a value received by the output value setting scan flip-flop group from the memory circuit as an expected value when reading the value of the address of the address line of the memory circuit for the address pattern series;
Generating the write enable initialization pattern series, the write enable transition pattern series, the address pattern series, the data pattern series, and the expected value as a serial pattern of the flip-flop group;
Obtaining an address line value of the memory circuit for the address pattern series as an initialization address;
Obtaining data different from the value of the data line of the memory circuit for the data pattern series as initialization data;
Obtaining a value of a control signal group of the memory circuit capable of writing the initialization data into the memory circuit at the initialization address as a memory initialization control value;
A method for generating a delay fault test pattern for a semiconductor integrated circuit, comprising: A memory circuit and a logic circuit unit connected to the memory circuit, and a part or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops; An initial value setting scan flip-flop group for setting, a transition value setting scan flip-flop group for setting a transition value in the memory circuit via the initial value setting scan flip-flop group, and an output of the memory circuit Integrated circuit that forms an output value setting scan flip-flop group that receives power and connects the scan flip-flops of these scan flip-flops serially to enable control and observation inside the semiconductor integrated circuit In, the delay of the path between the logic circuit portion and the memory circuit To detect the disabled, a method of generating a test pattern of the scan flip-flop group,
Selecting the longest testable path corresponding to the target failure that transitions from writable to writable in the write control signal of the memory circuit that generates the test pattern;
Obtaining a write enable initialization pattern for initializing the longest testable path;
Obtaining a write enable transition pattern for activating the longest testable path;
Obtaining a test pattern sequence for setting an address line of the memory circuit to a predetermined value;
Obtaining first memory initialization data to be written to a predetermined value in the memory circuit corresponding to the write enable initialization pattern and the address pattern series;
Obtaining second memory initialization data to be written to a predetermined value in the memory circuit corresponding to the write enable transition pattern and the address pattern series, with a value different from the first memory initialization data;
Obtaining a control value pattern series for setting a control signal group of the memory circuit to a value writable to the memory circuit;
The value of the data line of the memory circuit with respect to the determined first memory initialization data, the value of the address line of the memory circuit with respect to the determined address pattern series, and the determined write enable initialization pattern A step of obtaining, as an expected value, the value received by the output value setting scan flip-flop group from the memory circuit when reading the value of the address of the address line of the memory circuit with respect to the address pattern series after writing;
The obtained write enable initialization pattern, the write enable transition pattern, the address pattern series, the first memory initialization data, the second memory initialization data, the control value pattern series, and the expected value, Generating as a serial pattern of flip-flop groups;
A method for generating a delay fault test pattern for a semiconductor integrated circuit, comprising: A memory circuit and a logic circuit unit connected to the memory circuit, and a part or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops; An initial value setting scan flip-flop group for setting, a transition value setting scan flip-flop group for setting a transition value in the memory circuit via the initial value setting scan flip-flop group, and an output of the memory circuit Integrated circuit that forms an output value setting scan flip-flop group that receives power and connects the scan flip-flops of these scan flip-flops serially to enable control and observation inside the semiconductor integrated circuit In, the delay of the path between the logic circuit portion and the memory circuit To detect the disabled, a method of generating a test pattern of the scan flip-flop group,
Selecting the longest testable path corresponding to the target failure that transitions to readable from the unreadable read control signal of the memory circuit that generates the test pattern;
Obtaining a read enable initialization pattern for initializing the selected longest testable path;
Obtaining a read enable transition pattern for activating the selected longest testable path;
Obtaining an address pattern series for setting an address line of the memory circuit to a predetermined value;
Obtaining a data pattern series for setting a data line of the memory circuit to a predetermined value;
The control signal group of the memory circuit is set to a value that can be written to the memory circuit by the value of the address line of the memory circuit with respect to the address pattern series and the value of the data line of the memory circuit with respect to the data pattern series. Obtaining a control value initialization pattern to be set;
The control signal group of the memory circuit is set to a value that can be read from the memory circuit by the value of the address line of the memory circuit with respect to the address pattern series and the value of the data line of the memory circuit with respect to the data pattern series. Obtaining a control value transition pattern to be set;
After writing to the memory circuit by the value of the data line of the memory circuit for the data pattern series and the value of the address line of the memory circuit for the address pattern series and the read enable initialization pattern, the address pattern series Obtaining the value received by the output value setting scan flip-flop group from the memory circuit as an expected value when reading the value of the address of the address line of the memory circuit for
Obtaining a value different from the expected value as an output set value pattern;
The read enable initialization pattern, the read enable transition pattern, the address pattern series, the data pattern series, the control value initialization pattern, the control value transition pattern, the output set value pattern, and the expected value, Generating a flip-flop group as a serial pattern;
A method for generating a delay fault test pattern for a semiconductor integrated circuit, comprising: A memory circuit and a logic circuit unit connected to the memory circuit, and a part or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops; An initial value setting scan flip-flop group for setting, a transition value setting scan flip-flop group for setting a transition value in the memory circuit via the initial value setting scan flip-flop group, and an output of the memory circuit Integrated circuit that forms an output value setting scan flip-flop group that receives power and connects the scan flip-flops of these scan flip-flops serially to enable control and observation inside the semiconductor integrated circuit In, the delay of the path between the logic circuit portion and the memory circuit To detect the disabled, a method of generating a test pattern of the scan flip-flop group,
Selecting the longest testable path corresponding to the target failure that makes a transition from readable to unreadable from the read control signal of the memory circuit that generates the test pattern;
Obtaining a read enable initialization pattern for initializing the selected longest testable path;
Generating a read enable transition pattern for activating the longest testable path; and
Obtaining a predetermined first memory initialization address corresponding to the obtained read enable initialization pattern;
Obtaining a second memory initialization address corresponding to the obtained read enable transition pattern with a value different from the first memory initialization address;
Obtaining first memory initialization data for writing predetermined data to the memory circuit at the obtained first memory initialization address;
Obtaining second memory initialization data to be written to the memory circuit at the obtained second memory initialization address with a value different from the first memory initialization data;
Obtaining a memory initialization control value pattern series for setting the control signal group of the memory circuit to a value that allows the first memory initialization data and the second memory initialization data to be written to the memory circuit;
Obtaining an address for reading first memory initialization data written in the memory circuit and a value of an initial value scan flip-flop group for setting a control signal group of the memory circuit;
Obtaining an address for reading the second memory initialization data written in the memory circuit and a value of a transition value scan flip-flop group for setting a control signal group of the memory circuit;
A step of obtaining, as an expected value, a value received by the output value setting scan flip-flop group from the memory circuit when reading the data written in the memory circuit by a value of the initial value scan flip-flop group;
The read enable initialization pattern, the read enable transition pattern, the value of the initial value scan flip-flop group, the value of the transition value scan flip-flop group, and the expected value are obtained as a serial number of the scan flip-flop group. Generating as a pattern;
A method for generating a delay fault test pattern for a semiconductor integrated circuit, comprising: A memory circuit, a memory test circuit, and a logic circuit unit connected to the memory circuit and the memory test circuit, wherein a part or all of the flip-flops of the logic circuit unit are replaced with scan flip-flops; An initial value setting scan flip-flop group for setting an initial value in the memory circuit, and a transition value setting scan flip-flop group for setting a transition value in the memory circuit via the initial value setting scan flip-flop group And an output value setting scan flip-flop group that receives the output of the memory circuit, and the scan flip-flops of the scan flip-flop group are connected in series to control the circuit in the circuit from the outside of the semiconductor integrated circuit. In semiconductor integrated circuits that enable observation, Serial An inspection method for inspecting the presence or absence of a delay fault of the path of the logic circuit portion and the memory circuit,
Applying memory initialization data from the memory test circuit to the memory circuit;
A step of setting a test pattern in the initial value setting scan flip-flop group, the transition value setting scan flip-flop group, and the output value setting scan flip-flop group;
Applying a clock to the memory circuit and the scan flip-flop group at an actual operation speed of the memory circuit;
Reading the value of the output value setting scan flip-flop group;
A method for delay fault inspection of a semiconductor integrated circuit, comprising:

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