JP2005129174A - Semiconductor device having memory self-checking function - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress increase of a BIST circuit even when memory capacity of a memory part is increased, in a semiconductor device. <P>SOLUTION: A circuit used when usual operation is performed is used also as a part of the BIST circuit, in the semiconductor device having a memory self-checking function. Expected values are stored in a data input latch 2 serving both as the data input latch of a memory used for usual operation and the data input latch of expected values of a test circuit, read data of the memory are stored in a data output latch 3 serving as both the output latch of the memory used for usual operation and the compared data latch. The semiconductor device has a comparator 4 comparing the output of the data input latch and the output of the data output latch with each other, a read/write control counter 5 generating read write mode switching signals by dividing a clock frequency, a means 14 reversing the data of the data input latch, and a means 8 making a refresh address counter serve also as the address generating counter of the test circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a memory self-inspection function, and in particular, a semiconductor having a memory self-inspection function, such as a semiconductor integrated circuit device incorporating a circuit capable of performing a so-called built-in self-test (hereinafter referred to as a BIST circuit). Relates to the device.

  In recent years, system LSIs having a configuration in which a plurality of functional blocks are integrated in a single chip have been developed due to demands for higher density and higher integration of semiconductor integrated circuit devices. In particular, recently, an embedded LSI in which a large-capacity memory such as a DRAM and a logic are mixedly mounted in the same chip has attracted attention, and a BIST circuit for self-inspecting each functional block in the chip has been attracting attention. Consideration is being actively conducted.

  A semiconductor integrated circuit device having a configuration as shown in FIG. 4 (for example, Patent Document 1) has already been proposed. This semiconductor integrated circuit device includes a memory unit 104 such as a DRAM to which self-inspection data is written and read, and a BIST circuit 115 for inspecting the memory unit 104 is provided. The BIST circuit 115 includes an address generator 102, a data generator 108, a memory control signal generator 107, a comparison circuit 109, and a mixer circuit 111.

  The address generator 102 is configured by combining a plurality of counters, and outputs various self-test signals while counting up or counting down according to the external clock 103. That is, the address generator 102 outputs an internal clock (hereinafter referred to as ICLK) 106 and a phase signal for operating the memory unit 104, and inverts the level of the self-test data in a cycle output from the data generator 108. A pattern control signal (hereinafter referred to as a PATCNT signal) and a row address (hereinafter referred to as a ROW address) of the memory unit 104 are output.

  The address generator 102 outputs a column address (hereinafter referred to as a “COL address”) of the memory unit 104, while the level is changed every time self-test data is written in the entire memory area of the memory unit 104. Inverted alternately, in other words, a reverse control signal (hereinafter referred to as a REVCNT signal) whose level is inverted in a cycle in which all memory areas of the memory unit 104 are accessed is also output. At this time, the ROW address and the COL address 105 and ICLK 106, which are self-check addresses, are provided to the memory unit 104, and the phase signal is provided to the memory control signal generator 107. On the other hand, the PATCNT signal and the REVCNT signal are supplied in common to the data generator 108 and the comparison circuit 109, and the REVCNT signal is also supplied to the mixer circuit 111 alone.

  The data generator 108 generates self-test data patterned by the PATCNT signal and the REVCNT signal output from the address generator 102. Each time the level of the PATCNT signal is inverted, “0” and “1” are generated. Is output to the memory unit 104. In this data generator 108, every time the level of the REVCNT signal is inverted, that is, in a cycle of accessing the entire memory area of the memory unit 104, the pattern of the self-inspection data is completely inverted. Yes.

  The memory control signal generator 107 generates a memory control signal in response to the phase signal from the address generator 102. As a memory control signal for controlling writing and reading of self-test data to the memory unit 104, , ROW address strobe signal (RAS), COL address strobe signal (CAS), and write enable signal (WE). These memory control signals are output from the memory control signal generator 107 to the memory unit 104. The memory control signal generator 107 generates a data latch clock (DLCK) 113, and the DLCK 113 is output to the comparison circuit 109.

  The comparison circuit 109 determines whether or not the self-inspection data 101 read from the memory unit 104 matches the self-inspection data represented by the PATCNT signal and the REVCNT signal, that is, whether the pass (good) or not. It is determined whether the signal is (defective), and a path signal is output as a pass / fail signal if there is a match, and a flag signal (hereinafter referred to as a RECOG signal) 110 indicating a failure is output if there is a mismatch. . That is, since the self-inspection data that is patterned by the data generator 108 and written to the memory unit 104 is a simple repetitive pattern, the pattern of the read self-inspection data is a combination of the PATCNT signal and the REVCNT signal. If the pattern matches the pattern determined by, the RECOG signal output from the comparison circuit 109 indicates a pass, and the RECOG signal in the case of mismatch does indicate a fail.

The mixer circuit 111 periodically inverts the RECOG signal 110 output from the comparison circuit 109 by receiving the REVCNT signal output from the address generator 102. The mixer circuit 111 receives the REVCNT signal and the RECOG signal from the mixer circuit 111. A signal (hereinafter referred to as MOUT signal) 114 indicating the comparison result obtained by taking the exclusive OR of the signals is to be output. Therefore, the MOUT signal 114 output from the mixer circuit 111 accesses the same waveform as the RECOG signal 110 if the RECOG signal 110 input from the comparison circuit 109 indicates a path, that is, accesses all addresses of the memory unit 104. If the RECOG signal 110 indicates a failure, the waveform of the RECOG signal 110 has the same waveform as if it locally changed to a high level or a low level. Signal.
JP-A-11-260096

  By the way, in a semiconductor integrated circuit device, the function of a BIST circuit is generally matched with the memory capacity of a memory unit mixedly mounted in the same chip. Specifically, the memory capacity of the memory unit is When the memory capacity is 1 Mbit, the function of the address generation circuit and the like is appropriate for the memory capacity of 1 Mbit, and when the memory capacity is 4 Mbit, the function of the address generation circuit and the like is appropriate for the memory capacity of 4 Mbit. Is done.

  However, as long as such a configuration is used, the BIST circuit such as an address generation circuit increases with the increase in the memory capacity of the memory unit in the recent system LSI, and the occupied area of the BIST circuit in the LSI area increases. The problem of becoming.

  In view of the above, an object of the present invention is to allow an increase in the BIST circuit in a semiconductor device even when the memory capacity of a memory portion increases.

In order to achieve this object, a semiconductor device having a memory self-inspection function according to the present invention combines a circuit used during normal operation and a part of a BIST circuit.
As a result, an increase in circuit due to the BIST circuit, which is a test circuit, can be minimized, and an increase in chip area can be suppressed and an effect of reducing costs can be obtained.

  According to the present invention, in the above, the data input latch for storing the write data of the memory and the expected value at the time of the memory test, the data output latch for storing the read data of the memory, the output of the data input latch, It is preferable to have a means for testing the memory cell by comparing the output of the data output latch.

  According to the invention, in the above, a memory cell array, an input latch that temporarily stores write data to the memory cell array, and an output latch that temporarily stores read data from the memory cell array; A comparator for comparing the output of the input latch with the output of the output latch; means for switching between reading and writing of the memory; means for inverting data in the input latch; and means for generating an address of the memory It is preferable to have it.

According to the present invention, in the above, it is preferable that a binary counter is used as the means for generating an address.
According to the present invention, in the above, it is preferable to have means for latching the result of the output of the comparator.

  According to the present invention, in the above, it is preferable that the means for inverting the data of the input latch inverts the input data by feeding back the inverted output of the input latch to the input of the input latch. is there.

  According to the present invention, in the above, it is preferable that the means for switching between reading and writing of the memory generates a write / read mode switching signal by dividing the clock.

  According to the present invention, it is preferable to have a series of counters for generating a write / read mode switching signal, a data inversion control signal, a column address signal, and a row address signal.

According to the present invention, in the above, it is preferable that the refresh address counter of the memory is also used as the row address counter at the time of the test.
Further, according to the present invention, in the above, it is preferably used as a burn-in pattern generator.

Further, according to the present invention, in the above, it is preferable that the output of the most significant bit of the series of counters is used as an end signal of the test circuit.
According to the present invention, in the above, it is preferable that a clock for latching the result of the comparator is generated from the series of counters.

According to the present invention, in the above, it is preferable that the row-related control signal of the memory is generated from a series of counters.
According to the present invention, in the above, it is preferable that a plurality of memory cores are arranged on the same chip and have a means for generating a test end signal from the end signal of the BIST circuit for each memory core.

According to the present invention, in the above, it is preferable that the semiconductor device having a memory self-inspection function is a semiconductor memory.
According to the present invention, in the above, it is preferable that the semiconductor device having a memory self-inspection function is a semiconductor integrated circuit.

  A memory self-inspection method in a semiconductor device according to the present invention includes a memory cell array in a semiconductor device having a memory self-inspection function that combines a circuit used during normal operation and a part of a BIST circuit, and the memory cell array. An input latch that temporarily stores write data to the output, an output latch that temporarily stores read data from the memory cell array, a comparator that compares the output of the input latch and the output of the output latch, The memory is tested using means for switching between reading and writing of the memory, means for inverting the data in the input latch, and means for generating an address of the memory.

  Specifically, the first semiconductor device according to the present invention has a memory core such as a DRAM to which self-inspection data is written and read, and temporarily stores the write data to inspect the memory core. A data input latch that stores data, a data output latch that temporarily stores read data, a first selector that switches between positive and inverted signals of the data input latch, and a second that switches between a normal input and an output signal of the first selector A selector, a comparator that compares the output of the data input latch and the output of the data output latch, a write / read control counter, a complement counter of the data input latch, a column address counter that controls the column decoder, and a row decoder The row address counter to be controlled and the comparator edge A latch for outputting the flag of the pass / fail judgment in force, in which BIST circuit composed of a flip-flop is provided to the memory core within the same chip and for outputting a determination signal from the pass / fail flag. Then, the expected value is stored in the data input latch that is used as both the data input latch of the memory used for normal operation and the data input latch of the expected value of the test circuit, and the compared data of the output latch of the memory used for normal operation and the test circuit The read data of the memory is stored in a data output latch that also serves as a latch. Further, a comparator for comparing the output of the data input latch and the output of the data output latch, a write / read control counter having a flip-flop for dividing the clock and generating a write / read mode switching signal, and the data input latch By having means for inverting the data and means for generating an address by using the refresh address counter in combination with the address generation of the test circuit, the memory can be self-inspected.

  The second semiconductor device according to the present invention is characterized in that in the first semiconductor device, a binary counter is used as a series of counters and means for generating an address, and it is possible to configure a counter with easy control and a small circuit scale. And

  According to a third semiconductor device of the present invention, in a system LSI incorporating a plurality of memory cores, the most significant bit of a series of counters corresponding to each memory capacity is used as each END signal, and a logical product signal of each END signal is used. By using the inspection end signal, the completion of the self-inspection and burn-in inspection of the LSI memory can be confirmed, and at the same time, the pass / fail judgment can be easily confirmed by the judgment output signal of each memory.

  The semiconductor device of the present invention has the above-described configuration, and by sharing a circuit used during normal operation and a part of the BIST circuit, it is possible to minimize circuit increase due to the BIST circuit as a test circuit. In addition, the effect of reducing the cost can be obtained while suppressing the increase in the chip area.

  In addition to the above effects, the semiconductor device according to the present invention uses a binary counter as a series of counters and means for generating addresses. In addition to the effects described above, the address control of the test circuit can be easily achieved. Since the circuit scale is small and can be realized with a small area, an effect of cost reduction can be obtained.

  The semiconductor device according to the present invention incorporates a plurality of memory cores by using the most significant bit of a series of counters corresponding to each memory capacity as each END signal and the logical product of each END signal as a test end signal. In the system LSI, the pass / fail judgment can be easily confirmed by the logical product of each END signal and the judgment output signal of each memory.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a first semiconductor device according to an embodiment of the invention, and FIG. 2 is an explanatory diagram illustrating timing of the semiconductor device of FIG.

  As shown in FIG. 1, the first semiconductor device according to the embodiment of the present invention has a memory core 1 such as a DRAM to which self-inspection data is written and read, and inspects the memory core 1. Therefore, a data input latch 2 that temporarily stores write data, a data output latch 3 that temporarily stores read data, a selector 14 that switches a positive / inverted signal of the data input latch, a normal input, and an output of the selector 14 A selector 13 that switches between signals, a comparator 4 that compares the output of the data input latch 2 and the output of the data output latch 3, a write / read control counter 5, and a complement counter that outputs a data inversion control signal of the data input latch 6 and an interface for outputting output data to the main sense amplifier and DO latch 3 in the memory core 1. A column decoder 11 for controlling the face block, a column address counter 7 for controlling the column decoder 11, a row decoder 12 connected to a large number of memory cells in the memory core 1 through word lines, and a row decoder 12 A memory that controls the input / output timing of data in the memory core 1 and controls the DO latch 3 in response to a write / read switching signal that is an output from the row address counter 8 to be controlled and the write / read control counter 5 The BIST circuit including the timing control block 10, the latch 15 that outputs a pass / fail judgment flag by the output from the comparator 4 by the comparator edge, and the flip-flop 16 that outputs the judgment signal from the pass / fail flag is the same. Provided in the chip .

A part of the BIST circuit is also used as a circuit used in normal operation.
That is, the selector 14 is switched by the data inversion control signal that is the output signal of the complement counter 6 of the data input latch that counts up or down the normal rotation signal and the inversion signal from the data input latch 2 with a clock (hereinafter referred to as CLK), The output of the selector 13 that switches the output signal of the selector 14 and the normal input by the test switching signal is used as the input signal of the data input latch 2. With this configuration, the data input latch 2 is used as a data generator that temporarily stores the write data during the normal operation and the test operation, and operates as a data generator that automatically generates data during the test.

The data output latch 3 also serves as an output latch of a memory used for normal operation and a compared data latch at the time of testing, and temporarily stores read data of the memory.
At this time, the column address and the row address of the memory core 1 are automatically generated by the column address counter 7 and the row address counter 8 constituted by a plurality of counters, and control the column decoder 11 and the row decoder 12, respectively. The column decoder 11 and the row decoder 12 are used for both a normal operation and a test operation, and are controlled by a column address input and a row address input from the outside during the normal operation.

  Furthermore, the memory timing control block 10 generates data input / output timing signals by external row address control signals, column address control signals, and write enable signals during normal operation, and write / read during test operations. In response to a write / read switching signal output from the control counter 5, a data input / output timing signal is generated. That is, the memory core 1 and the DO latch 3 are controlled for both the normal operation and the test operation.

The row address counter 8 also serves as a refresh address counter that outputs an END signal during normal operation, and controls the row decoder 12.
The output result of the data input latch 2 that is an expected value at the time of the test and the output result of the data output latch 3 that is read from the memory core 1 are input to the comparator 4. If the output result of the latch 2 and the output result of the data output latch 3 as the data to be compared match, a low level is output, and if they do not match, a high level output is output. The latch 15 outputs a pass / fail judgment flag. By monitoring the pass / fail flag, the fail address can be confirmed. Further, by inputting the pass / fail flag of the latch 15 as the clock of the flip-flop 16, the output result of the data input latch 2 which is an expected value in the entire address space and the output result of the data output latch 3 which is the data to be compared are obtained. If they match, the determination output signal from the flip-flop 16 is fixed at the low level, and the output result of the data input latch 2 that is an expected value at one or more locations and the output result of the data output latch 3 that is the data to be compared are displayed. In the case of mismatch, the determination output signal from the flip-flop 16 remains fixed at the high level after the address where the mismatch initially occurred.

  FIG. 2 shows this timing. In FIG. 2, when reset (hereinafter referred to as RST) is released and chip enable (hereinafter referred to as CE) becomes valid, a write / read is performed for each address by a switching signal from the write / read control counter 5 in synchronization with CLK. Begins. Then, the output DIN of the data input latch 2 which is an expected value automatically generated by the data input latch 2 and the selectors 13 and 14 and the output DO of the data output latch 3 which is the compared data read from the memory core 1 are compared with each other. 4 and the output of the write / read control counter 5 is latched by the latch 15 with the comparator edge obtained by ANDing the write / read mode switching signal and CLK with the AND gate 9. Output pass / fail flag. For example, as shown in FIG. 2, when a mismatch occurs between the low-level data at address # 1 and the high-level data at address # 3, a mismatch is detected in the low-level comparator result at address # 1, and the determination output signal goes high. Thus, even if the subsequent address # 2 matches the result of the comparator, the determination output signal remains at the high level. Therefore, a test is performed in association with the END signal which is the output signal of the most significant bit of the series of counters 5, 6, 7, and 8. When the END signal is output after the test of all address spaces is completed, By checking, it is possible to easily know the pass / fail judgment of the entire memory core 1.

  At this time, if the output DIN of the data input latch 2 that is the expected value and the output DO of the data output latch 3 that is the data to be compared read from the memory core 1 match at all addresses, the determination output in FIG. The signal is fixed at a low level.

Further, since it has a self-inspection function that enables the self-inspection of the memory with such a small number of terminal controls, it can also be used as a pattern generator at the time of burn-in inspection.
As described above, in the first semiconductor device according to the embodiment of the present invention, the circuit used during normal operation and a part of the BIST circuit are shared, so that the BIST circuit which is a test circuit is used. The circuit increase can be minimized. For this reason, an increase in the chip area can be suppressed, the cost can be reduced, and further, it can be used as a pattern generator at the time of burn-in.

  The second semiconductor device according to the embodiment of the present invention includes a write / read control counter 5 that generates a write / read mode switching signal and a complement that generates a data inversion control signal in the first semiconductor device described above. A series of counters including a counter 6, a column address counter 7 for generating a column address signal, and a row address counter 8 for generating a row address signal are constituted by binary counters. By configuring with a binary counter in this way, the control of the counter is easy, and the circuit scale of the counter circuit is small and can be realized with a small area. Therefore, chip area reduction and cost reduction effects can be obtained.

  In FIG. 1, the series of counters 5, 6, 7, and 8 generate a write / read mode switching signal, a data inversion control signal, a column address signal, and a row address signal in this order. However, this order is not particularly limited.

  The third semiconductor device according to the embodiment of the present invention can confirm the end of the self-inspection and the burn-in inspection using the inspection end signal generating circuit shown in FIG. 3, and each monitor when the inspection end signal is output. By confirming the determination output as a signal, the final pass / fail determination of each memory core can be performed.

  In FIG. 3, first to third BIST circuits 17, 18, and 19 are BIST circuits corresponding to memory cores having different memory capacities. The END signal 1 and the END signal 2 are sent from the BIST circuits 17, 18, and 19, respectively. , END signal 3, determination output 1, determination output 2, and determination output 3. A signal obtained by ANDing the END signal 1, the END signal 2, and the END signal 3 by the AND gate 20 is used as a test end signal. By confirming the determination output 1, the determination output 2, and the determination output 3 when the inspection end signal is output, the determination of pass / fail of each memory core can be easily confirmed.

In FIG. 3, three BIST circuits 17, 18, and 19 are exemplified, but it goes without saying that the same configuration can be confirmed when there are two or more BIST circuits.
In FIG. 3, the BIST circuit corresponding to the memory cores having different memory capacities is illustrated, but the same applies to the case where the memory capacities are the same.

  The semiconductor device having the memory self-inspection function of the present invention can minimize the increase in circuit due to the BIST circuit as a test circuit by sharing a circuit used during normal operation and a part of the BIST circuit. In addition, it is useful as a semiconductor device or the like having a built-in circuit capable of suppressing the increase in chip area and reducing the cost and capable of performing BIST.

1 is a configuration diagram of a semiconductor device having a memory self-inspection function as a first semiconductor device according to an embodiment of the present invention. FIG. 1 is a timing chart of the semiconductor device having the memory self-inspection function. Test end signal generation circuit diagram in the case where a plurality of memory cores are built in the third semiconductor device according to the embodiment of the present invention Configuration diagram of conventional memory self-test circuit

Explanation of symbols

1 Memory Core 2 Data Input Latch 3 Data Output Latch 4 Comparator 5 Write / Read Control Counter 6 Complement Counter 7 Column Address Counter 8 Row Address Counter (Refresh Address Counter)
13 Selector 14 Selector 15 Latch

Claims (17)

  A semiconductor device having a memory self-inspection function, wherein a circuit used during normal operation and a part of a circuit capable of performing a built-in self-test are combined.   A data input latch for storing memory write data and an expected value at the time of a memory test, a data output latch for storing memory read data, an output of the data input latch, and an output of the data output latch are compared. 2. A semiconductor device having a memory self-inspection function according to claim 1, further comprising means for testing a memory cell at a rate.   A memory cell array; an input latch for temporarily storing write data to the memory cell array; an output latch for temporarily storing read data from the memory cell array; an output of the input latch; and the output latch 2. A comparator for comparing the output of the memory, means for switching between reading and writing of the memory, means for inverting data in the input latch, and means for generating an address of the memory. Semiconductor device having a memory self-inspection function.   4. A semiconductor device having a memory self-inspection function according to claim 3, wherein a binary counter is used as means for generating an address.   4. A semiconductor device having a memory self-inspection function according to claim 3, further comprising means for latching a result of the output of the comparator.   4. The memory self-test according to claim 3, wherein the means for inverting the data of the input latch performs inverting of the input data by feeding back the inverted output of the input latch to the input of the input latch. A semiconductor device having a function.   4. The semiconductor device having a memory self-inspection function according to claim 3, wherein said means for switching between reading and writing of the memory divides the clock to generate a write / read mode switching signal.   8. The memory according to claim 3, further comprising a series of counters for generating a write / read mode switching signal, a data inversion control signal, a column address signal, and a row address signal. A semiconductor device having a self-inspection function.   9. The semiconductor device having a memory self-inspection function according to claim 1, wherein a refresh address counter of the memory is also used as a row address counter for testing.   10. The semiconductor device having a memory self-inspection function according to claim 1, wherein the semiconductor device is used as a burn-in pattern generator.   9. The semiconductor device having a memory self-test function according to claim 8, wherein the output of the most significant bit of the series of counters is used as an end signal of the test circuit.   9. The semiconductor device having a memory self-test function according to claim 8, wherein a clock for latching a result of the comparator is generated from a series of counters.   9. The semiconductor device having a memory self-inspection function according to claim 8, wherein a row control signal of the memory is generated from a series of counters.   2. The memory device according to claim 1, further comprising means for generating a test end signal from an end signal of a circuit in which a plurality of memory cores are arranged on the same chip and can perform a built-in self test for each memory core. A semiconductor device having an inspection function.   15. The semiconductor device having a memory self-inspection function according to claim 1, wherein the semiconductor device is a semiconductor memory.   15. The semiconductor device having a memory self-inspection function according to claim 1, wherein the semiconductor device is a semiconductor integrated circuit.   In a semiconductor device having a memory self-inspection function that combines a circuit used during normal operation and a part of a circuit capable of performing a built-in self-test, a memory cell array and write data to the memory cell array are temporarily stored An input latch for storing data, an output latch for temporarily storing read data from the memory cell array, a comparator for comparing the output of the input latch with the output of the output latch, and reading and writing of the memory A method of self-inspecting a memory in a semiconductor device, wherein the memory is tested using a switching means, a means for inverting data in the input latch, and a means for generating an address of the memory.

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