JP2000251496A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform discrimination when a vender test mode is set surely without usinf a measuring device such as an ammeter and the like. SOLUTION: When a vender test mode in which a burn-in test is performed is set, a test input signal TBIN of a Hi level is outputted to a normal/burn-in signal output circuit 10 from a test control circuit, an inverter 13 is made a floating state, and an inverter 16 is operated. Therefore, data MO0 outputted from a sense amplifier is outputted to an output buffer as reversed data of data written through inverters 15-17. This reversed data are monitored by a burn-in tester, and it is discriminated that a burn-in test mode is set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test mode setting technique in a semiconductor integrated circuit device, and more particularly to a technique which is effective when applied to the determination of a setting state in a vendor test mode.

[0002]

2. Description of the Related Art According to studies by the present inventor, a synchronous DRAM (Dynamic Random A) has been disclosed.
In a semiconductor integrated circuit device such as an access memory, a normal mode setting is performed in order to reduce a test time for a large-scale circuit, to confirm an internal operation state that cannot be confirmed by a normal command control, and to perform efficient screening. Separately, a vendor test mode setting is provided.

In this vendor test mode, four command control signal combinations (chip select / CS, row address strobe / RA) synchronized with an external clock signal are used.
S, column address strobe / CAS, write enable / WE), MRS (Mode Register)
r Set) command and a signal obtained by combining a Hi signal and a Lo signal input to a specific address terminal.

[0004] Whether or not the vendor test mode is set is determined, for example, by measuring a current value flowing to an external terminal to which a power supply voltage which is an operating voltage of the semiconductor integrated circuit device is supplied. I have.

[0005] As an example describing in detail the test technology of this type of semiconductor integrated circuit device, see, for example, Shinji Matsushita (ed.) Published by Press Journal Co., Ltd. on May 30, 1997, "Monthly Semiconductor World".
d Special Issue, ULSI Test Technology ", 1997 Special Issue, Vol. 16, No. 8, pages P19 to P23, and this document describes a test technique in a DRAM.

[0006]

However, the present inventor has found that the above-mentioned semiconductor integrated circuit device has the following problems.

In other words, in order to determine whether or not the vendor test mode has been set, an ammeter must be connected and the current value must be measured, so that setting and measurement time are required. There is a problem that the efficiency is reduced and the productivity of the semiconductor integrated circuit device is reduced.

It is an object of the present invention to provide a semiconductor integrated circuit device which does not require a measuring instrument such as an ammeter and can reliably determine when a vendor test mode is set.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention includes data control means for inverting data read when a test control signal is input and outputting the inverted data to an output buffer.

Further, the semiconductor integrated circuit device of the present invention is provided with data control means for inverting and outputting the write data input through the input buffer when the test control signal is input.

Further, the semiconductor integrated circuit device of the present invention
The test control signal input to the data control means comprises a signal output from a control circuit when a burn-in test is set.

Also, in the semiconductor integrated circuit device according to the present invention, the data control means may output the input data without inverting the first data output section, and the data output section may invert the input data and output the inverted data. And a control unit for generating a control signal for performing switching control of the first and second data output units based on a test control signal.

As described above, when the burn-in test is set, the read data is inverted and output, so that the burn-in test mode can be easily and reliably monitored by monitoring it with the burn-in tester. It can be determined that the setting has been made.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a memory in a synchronous DRAM according to an embodiment of the present invention, and FIG. 2 is a normal / burn-in provided in the memory according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a signal output circuit.

In this embodiment, the synchronous DR
A memory (semiconductor integrated circuit device) 1 that is an AM has a memory array 2 in which memory cells, which are the minimum units of storage, are regularly arranged in an array. This memory array 2 is composed of two banks 2A and 2B.
It has a bank configuration.

A row decoder 3 is connected to each memory array 2.
Selects a word line in the row (row) direction of the memory array 2.

Further, a sense amplifier 4 and a column decoder 5 are connected to each memory array 2. The sense amplifier 4 amplifies data of the column decoder 5, and the column decoder 5 selects a bit line in a column (column) direction.

A column address counter 6 is connected to these column decoders 5. An address buffer 7 is connected to the column address counter 6 and each row decoder 3.

The column address counter 6 generates an address based on an address signal input from the address buffer 7. The address buffer 7 receives the input address signals in the column direction and the row direction based on the input address signals.
Each internal address signal is generated and output to the column address counter 6 and each row decoder 3.

The memory 1 is provided with a control circuit 8. The control circuit 8 reads the clock signal CLK input from the outside, the clock enable signal CKE which is a permission signal for accepting the clock signal, the chip select signal / CS for selecting a chip, and the address in the row direction at an appropriate timing. , A column address strobe signal / CAS as a control signal for reading an address in a column direction at an appropriate timing, a write enable signal / WE as a write enable signal, and a selection signal. An input signal such as an input / output mask signal DQM or a command signal is input via an input terminal, and various control signals and a control signal in which the command signal is decoded by a command buffer / decoder are output.
Here, the above-mentioned command buffer / decoder is provided in the control circuit 8.

The control circuit 8 is provided with a clock generation circuit for generating a signal synchronized with the clock signal CLK and supplying the signal as a clock signal which is a basic operation of the memory 1. The generated clock signal is supplied via an internal clock bus.

Further, the control circuit 8 is provided with a test control circuit. The test control circuit controls the memory 1 at the time of testing, and outputs an MRS command and a Hi signal input to a specific address terminal. , Lo
When the vendor test mode is set by a signal obtained by combining the signals, a test input signal (test control signal) TBIN of the Hi signal is output.

An input buffer 9 and a normal / burn-in signal output circuit (data control means) 10 are connected to the sense amplifier 4. An output buffer 11 is connected to the normal / burn-in signal output circuit 10.

The input buffer 9 takes in input data at a predetermined timing, and the normal / burn-in signal output circuit 10 inverts and outputs data output when the vendor test mode is set. The output buffer 11 temporarily stores output data. Also, a refresh counter 12 is connected to the address buffer 7, and the refresh counter 12 generates an address for a refresh operation.

The circuit configuration of the normal / burn-in signal output circuit 10 will be described.

Normal / burn-in signal output circuit 10
Is composed of inverters 13 to 17, as shown in FIG.

Of the inverters 13 to 17, the inverters (first data output units) 14 and 16 are provided with control gates G1 and G2. Inverter 14,1
6 outputs an inverted signal of the input signal when the Hi signal is input to the control gate G1 and the Lo signal is input to the control gate G2, and the Lo signal is input to the control gate G1; When the Hi signal is input to the control gate G2, the output unit enters a floating state.

The input section of the inverter (control section) 13, the control gate G2 of the inverter 14, and the control gate G1 of the inverter 16 are connected so that the above-described test input signal TBIN is input.

The output of the inverter 13 is connected to a control gate G1 of the inverter 14 and a control gate G2 of the inverter 16. The input portions of the inverters 14 and 15 are connected to a main amplifier provided in the sense amplifier 5, and input data output through the main amplifier.

The output of the inverter (second data output) 15 is connected to the input of an inverter (second data output) 16, and the outputs of the inverters 14 and 16 are connected to the inverter 17. Are connected. The output buffer 11 is connected to the output of the inverter 17.

Although only one circuit configuration of the normal / burn-in signal output circuit 10 is shown in FIG. 2, actually, only the number of data D0 to Dn to be output is shown in FIG.
Circuit is provided.

Next, the operation of the present embodiment will be described.

First, when the memory 1 is subjected to the burn-in test, the memory 1 has a chip select / CS, a row address strobe / RAS,
A vendor test mode for performing a burn-in test is set by an MRS command based on a combination of four command control signals including a column address strobe / CAS and a write enable / WE, and a signal input to a specific address terminal.

The specific address terminal is, for example, an address terminal to which an address A7 is input. When a Hi signal is input to this address terminal, a burn-in test is set.

The MRS command is input to the test control circuit, and the test control circuit outputs a Hi-level test input signal TBIN to the normal / burn-in signal output circuit 10.

The Hi-level test input signal TBIN output from the test control circuit is output to a boost power supply circuit or the like. Generates boost voltage for high burn-in test. This test input signal TBIN is supplied to a normal / burn-in signal output circuit 10.
, It is possible to eliminate the need for a new additional circuit.

When the test input signal TBIN is input, a Hi signal is input to the control gate G2 of the inverter 14, the control gate G1 of the inverter 16, and the input of the inverter 13.

The output of the inverter 13 outputs a Lo signal which is an inverted signal. This Lo signal is input to the control gate G1 of the inverter 14 and the control gate G2 of the inverter 16, respectively.

Therefore, the control gate G of the inverter 14
1 and G2, a Lo signal and a Hi signal are input, respectively, and the control gates G1 and G2 of the inverter 16
Since the i signal and the Lo signal are respectively input, the inverter 14 enters a floating state, and the inverter 16
Operate as an inverter.

Data MO0 output from main amplifier
(〜MOn) is output via the inverters 15 to 17 because the inverter 14 is in a floating state (burn-in path).

Data MO0 (（MOn) is inverted by inverter 15 and again by inverter 16. Then, the signal is inverted by the inverter 17 and the data DO0 (出力 Do) is output to the output buffer 11.
n).

In this burn-in pass, the inverter 15
Since the data is inverted three times by .about.17, the data DO0 (.about.Don) output via the output buffer 11
Outputs inverted data of the written data. By reading the inverted data by the burn-in tester, it can be determined that the burn-in test mode has been set.

In the case other than the burn-in test, or when the memory 1 is not set to the burn-in test, the test input signal TBIN becomes a Lo signal, so that the inverter 14 operates as an inverter and the inverter 16 is in a floating state. , The data MO0 (〜MOn) output from the main amplifier is
The signal is output via the inverters 14 and 17 (normal path).

In the normal path, the inverter 1
The data is inverted twice by 4,17,
Data DO0 (-) output via output buffer 11
Don), the same data as the written data is output. By reading the data DO0 (〜Don) by the burn-in tester, it can be determined that the burn-in test mode has not been set.

Thus, in the present embodiment, the inverted data of the read data is output by the normal / burn-in signal output circuit 10 only when the burn-in test mode is set, so that it is easy and reliable. Can be determined that the memory 1 has been set to the burn-in test mode.

In the present embodiment, the normal / burn-in signal output circuit 1
However, the normal / burn-in signal output circuit 10 may be provided in the sense amplifier 4 or in the vicinity thereof.

Further, according to the present embodiment, the normal / burn-in signal output circuit 10 inverts and outputs the data read when the burn-in test is set. For example, FIG. As described above, the normal / burn-in signal output circuit 10a is provided after the input buffer 9.
May be provided, and when the burn-in test is set, the data before writing may be inverted and written into each memory array 2.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

In the above-described embodiment, it is determined that the burn-in test has been set when the read data is inverted data. However, for example, a newly provided specific external terminal or an input / output mask signal may be used. The input external terminal or the like may be monitored to determine that burn-in has been set.

When monitoring an external terminal to which an input / output mask signal is input, a circuit is provided which normally performs input / output data masking but does not perform input / output data masking during a burn-in test. Thus, it is determined whether the burn-in test is set.

When a new external terminal is provided,
A test input signal output from the test control circuit in the above embodiment may be output to this external terminal, and the setting state of the burn-in test may be determined based on the state of the signal.

Further, in the synchronous DRAM,
The / CAS latency (CL), which is the number of clocks from when a command is input until data is output, may be set to a latency number that cannot be set in a normal mode.

For example, when CL = 1 to 3 is used, the burn-in test can be determined by fixing CL = 4 so that CL can be obtained from the read operation.

In the above embodiment, the case where the normal / burn-in signal output circuit is provided in the synchronous DRAM has been described. However, the normal / burn-in signal output circuit is not limited to the synchronous DRAM, and may be a vendor that performs a burn-in test. Any semiconductor integrated circuit device having a test mode may be used.

[0058]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the inverted data of the read data is output only when the burn-in test mode is set by the data control means, so that the semiconductor integrated circuit can be easily and reliably provided. It can be determined that the device has been set to the burn-in test mode.

(2) In the present invention, the burn-in test can be performed efficiently according to the above (1), so that the productivity of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 shows a synchronous DR according to an embodiment of the present invention.
It is a block diagram of a memory in AM.

FIG. 2 is a circuit diagram of a normal / burn-in signal output circuit provided in a memory according to one embodiment of the present invention;

FIG. 3 shows a synchronous D according to another embodiment of the present invention.
It is a block diagram of a memory in RAM.

[Explanation of symbols]

Reference Signs List 1 memory (semiconductor integrated circuit device) 2 memory array 3 row decoder 4 sense amplifier 5 column decoder 6 column address counter 7 address buffer 8 control circuit 9 input buffer 10, 10a normal / burn-in signal output circuit (data control means) 11 output buffer Reference Signs List 12 refresh counter 13 inverter (control unit) 14 inverter (first data output unit) 15, 16 inverter (second data output unit) 17 inverter G1, G2 control gate TBIN test input signal (test control signal)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/822 H01L 27/04 T (72) Inventor Hiroshi Yoshioka 5--22, Kamimizuhoncho, Kodaira-shi, Tokyo No. 1 In Hitachi Ultra SII Systems Co., Ltd. (72) Inventor Kazuhisa Ureshino 5-22-1, Josuihoncho, Kodaira-shi, Tokyo In Hitachi Ultra LSI Systems Co., Ltd. F term (reference) 2G032 AA07 AB02 AE11 AG01 AG07 AK11 AK14 5B024 AA15 BA29 CA07 EA04 5F038 BE04 BE05 BG03 CD08 DF05 DF14 DT02 DT05 DT10 5L106 AA01 DD11 DD35 GG02

Claims (4)

[Claims] 1. A semiconductor integrated circuit device comprising: data control means for inverting data read when a test control signal is input and outputting the inverted data to an output buffer. 2. A semiconductor integrated circuit device comprising: data control means for inverting and outputting write data input via an input buffer when a test control signal is input. 3. The semiconductor integrated circuit device according to claim 1, wherein the test control signal input to the data control means is a signal output from the control circuit when a burn-in test is set. Semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein said data control means outputs a first data output section without inverting input data, A second data output unit for inverting and outputting the output data, and the first and second data output units based on a test control signal.
And a control unit for generating a control signal for performing switching control of the data output unit.