JP4423407B2 - Semiconductor test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor test apparatus capable of performing repair analysis of a memory under test (DUT) having a redundant configuration at higher speed. In particular, the present invention relates to a semiconductor test apparatus capable of performing a SCAN operation for reading and checking a fail content of an address fail memory (AFM) for storing a test result at high speed.
[0002]
[Prior art]
FIG. 1 shows a conceptual configuration diagram of a conventional memory test apparatus. The main configuration is realized by the timing generator TG, the pattern generator PG, the waveform shaper FC, the pin electronics, the logic comparator DC, the fail memory FM, and the repair analysis device 100. A failure analysis memory AFM is an element related to the present application in the fail memory FM. Since the semiconductor test apparatus is known and well known in the art, other signals and components other than the main part according to the present application, and detailed description thereof will be omitted.
[0003]
On the basis of the reference clock generated by the timing generator TG, the pattern generator PG provides the waveform shaper FC with pattern data for outputting an address signal, a test data signal, and a control signal to be supplied to the DUT. And then applied to the DUT with a predetermined amplitude via a driver provided in the pin electronics.
The DUT is controlled to write and read test data by control signals such as CE, OE, WE, CAS, and RAS. The response signal read from the data output pin of the DUT is applied to the logic comparator DC through the pin electronics comparator, where a predetermined coincidence comparison is performed by the expected value data EXP output from the pattern generator PG. The pass / fail judgment is made, and when the result is defective, the fail information FAIL is supplied to the fail memory FM. Although the number of DUTs is one example in FIG. 1, a semiconductor test apparatus having a configuration in which a large number of, for example, 32, 64, multiple DUTs are simultaneously measured is common.
[0004]
The failure analysis memory AFM in the fail memory FM has at least the same memory configuration as the DUT data width and address space, and has a high-speed storage device equivalent to or higher than the DUT access speed corresponding to the number of DUTs to be measured simultaneously. ing. For example, when the DUT is 256M bits and the number of measured data is 64, a large-capacity storage device of 256M bits × 64 is provided.
In the fail storing operation, an address signal corresponding to the read address of the DUT is received from the pattern generator PG, and the fail information FAIL from the logical comparator DC is accumulated and stored in the corresponding address position of the AFM.
[0005]
A semiconductor memory typified by a DRAM has a configuration as shown in FIG. 2 and is composed of a main cell for data storage of the DRAM, and a line-shaped spare cell called a spare row SR and a spare column SC around the main cell. When this one block is called a relief block, the semiconductor memory chip is constituted by arranging a plurality of relief blocks.
[0006]
Next, the concept of the repair method in one repair block will be described with reference to FIG. In this figure, if it is assumed that a defective cell “x” exists at the position shown in FIG. 3A, as shown in FIG. 3B, one line is replaced and repaired using one spare column SC. As a result, as shown in FIG. 3C, a non-defective chip is obtained, and the yield can be greatly improved. The actual replacement process is performed by cutting the fuse provided in the address decode circuit for one line of defective cells with a laser and cutting the fuse so that the address decode circuit to replace the spare column SC becomes effective.
[0007]
The repair analysis apparatus 100 performs repair analysis so that repair is possible with a small number of spare rows SR and a small number of spare columns SC. That is, eventually, the contents of the acquired failure analysis memory AFM are sequentially read and analyzed in a test stop state after the end of the predetermined test item. For this purpose, all addresses to be read are sequentially generated and supplied to the AFM, fail data read from the address of the AFM is received, and a failure occurs for each row address line and column address line in which the fail exists. The number of times is counted, and based on this, the row line and column line to be replaced and repaired are analyzed and specified, and the specified repair information is acquired as information for the repair processing step.
[0008]
Next, the repair principle of the conventional repair analysis apparatus 100 that enables repair with a small number of spare rows SR and spare columns SC will be described with reference to FIGS. Here, the memory that counts the number of occurrences of failure for each row address is called a row fail count memory RFCM (Row Fail Count Memory), and the memory that counts the number of failures for each column address is called column fail count memory. Memory CFCM (Column Fail Count Memory) is called, and the memory that counts the total number of failures is called total fail count memory TFCM (Total Fail Count Memory). The repair analysis apparatus 100 includes the multi-channel counting elements. 2 is called a SCAN operation, and an operation for checking which row or column address line has a line failure with respect to the RFCM and CFCM after the SCAN operation is a SEARCH operation. Call it. Furthermore, when the number of times of RFCM or CFCM failure is greater than the number of spare lines on the opposite side, the spare line on the opposite side cannot be relieved, so that line is called a line failure.
[0009]
In the example of FIG. 4, it is assumed that a failure has occurred at the position indicated by “x”, and further assumes that the number of spare rows SR to be repaired is two and the number of spare columns SC is two. To do.
FIG. 4 shows the result after the SCAN operation. That is, the CFCM side shows the state where the count values “3” and “1” are obtained at two locations, the RFCM side shows the state where the count value “1” is obtained at four locations, and the TFCM shows the count value “4”. "" Indicates the obtained state.
[0010]
Next, as shown in FIG. 5, since the count value “3” exists at one location on the CFCM side and the number of spare rows SR on the opposite side cannot be repaired with two, the line is detected as a line failure. Since the line is a relief target, the line information is stored in the fail address memory FAM.
Next, as shown in FIG. 6, since the failure occurrence “x” mark on the relevant line for which the repair is confirmed is repaired, the RFCM, CFCM, TFCM on the line is erased to erase the defective cell on the repair address. A subtraction process is performed for the rescued fail. This operation is called a DSCAN operation. As a result, the count value of FIG. 6 is obtained. If there are a plurality of line failures, the same process is repeated.
[0011]
Next, when there is no line fail, as shown in FIG. 7, this time, the address value (row address, column address) of the remaining fail is received, and a repairable combination is analyzed and obtained by arithmetic processing such as a CPU. To go. The example of FIG. 7A is an example in which a failure has occurred at six locations and no line failure has occurred. The analysis result of FIG. 7B is an example in which one fail (see FIG. 7A) cannot be repaired by two spare rows SR and two spare columns SC. FIGS. 7C and 7D are both examples. This is an example in which fail relief can be performed.
[0012]
Next, the configuration of the repair analysis apparatus 100 will be described with reference to the conceptual configuration of FIG. 8 and the internal configuration of FIG.
As shown in FIG. 8, the repair analysis apparatus 100 includes a repair analysis apparatus having the number of channels corresponding to the number of DUTs simultaneously measured. Furthermore, the relief analysis apparatus for each DUT includes a CPU unit 110 and a counter block unit (Counter Block unit) 120 having a plurality of channels corresponding to the memory configuration of the DUT. Note that the CPU unit 110 includes a CPU that performs processing using a dedicated controller and a CPU that uses a program type CPU or DSP.
[0013]
The internal principle configuration of the one-channel counter block unit 120 will be further described with reference to FIG. The main configuration includes an address generation unit 60, an address format unit 80, a row fail count memory RFCM, a column fail count memory CFCM, a total fail count memory TFCM, and a sequence control unit 40. , A fail counting unit 350, a magnitude comparator 90, a fail address memory FAM, a FAM-AP, and the like.
[0014]
The address generation unit 60 generates a row address RA and a column address CA and supplies them to the address format unit 80 to generate an analysis address AFMA for accessing the failure analysis memory AFM shown in FIG. There are two counters, RAP (Row Address Pointer) that generates a row address RA and CAP (Column Address Pointer) that generates a column address CA.
[0015]
The address format unit 80 receives the row address RA and the column address CA, generates and outputs an analysis address AFMA, and further generates addresses RFA, CFA, and TFA to be supplied to the RFCM, CFCM, and TFCM. Output. That is, the addresses are rearranged so that the fail can be counted for each relief block. Note that RFCM, CFCM, and TFCM are the fail count memories described above.
[0016]
The sequence control unit 40 generates a fail count control signal SCANMD, DSCANMD, a count control INC to the address generation unit 60, and a read / write control signal * FCMWE, * FCMOE, * FDOE to the RFCM, CFCM, TFCM. And supply.
[0017]
The fail counter 350 receives the control signals SCANMD and DSCANMD from the sequence control, and firstly performs an addition operation with the fail signal FAIL from the failure analysis memory during the SCAN operation, and secondly, the fail signal during the DSCAN operation. A subtraction operation is performed with FAIL.
[0018]
The size comparator 90 is a line fail detection, receives the number of failures RFD and CFD from the RFCM and CFCM, performs a size comparison with a numerical value that is a preset number of spare rows and spare columns, If the number of failures is greater than the number of spare lines, it is detected as a line failure, an address storage signal * FAMWE is supplied to FAM, and an address increment signal FAMINC is supplied to FAM-AP.
[0019]
The fail address memory FAM stores a line fail address LFA in which a line fail is detected. The line fail address LFA selected by switching the RFA or CFA at the occurrence of the line fail by the RCSEL signal of the multiplexer MUX. Is stored. The FAM storage address is incremented every time FAM-AP is generated and the FAM stores the line fail address.
[0020]
Returning to FIG. 8, the CPU unit 110 reads out the contents of the FAM to acquire information on the line failed line, and further reads out the contents of the RFCM, CFCM, and TFCM, and performs a predetermined repair analysis process.
[0021]
By the way, the capacity of the DUT is increasing year by year. For this reason, the processing time for repair analysis becomes longer in proportion to the increase in the number of memory cells. Moreover, since it is necessary to access the AFM shown in FIG. 1 from the repair analysis apparatus 100, the DUT test is suspended during this period. That is, as shown in FIG. 10, the memory test cannot be performed during the repair analysis, and the test is in a standby state (see FIG. 10B). If the waiting period becomes longer, the total test cycle time becomes longer, and as a result, the test cost increases.
[0022]
The SCAN operation and SEARCH operation take the longest time in the repair analysis. This is because the number of failures is counted while reading the failure presence / absence contents of all memory cells of the DUT from the defect analysis memory AFM.
[0023]
Next, a timing chart of the conventional SCAN operation is shown in FIG. 11 and will be described together with the internal principle configuration of FIG.
Assuming that the internal configuration operates in synchronization with the clock CLK, one cycle of the SCAN operation shown in FIG. 11 requires 5 clock cycles. That is, first, in cycle (CYCLE) 0, addresses are supplied from the address format unit 80 to each FCM (RFCM, CFCM, TFCM), and * FCMOE is set to the read mode, so that the fail meter from each FCM (RFCM, CFCM, TFCM) The numerical value FAIL (RFD, CFD) is read.
In cycle 1, the fail counting unit latches and holds FAIL read from the AFM. In cycle 2, +1 is added based on the presence or absence of FAIL. In cycle 3, the fail count value obtained by adding the * FCMWE signal in the write mode is written to the same address position as when reading each FCM (RFCM, CFCM, TFCM). Cycle 4 is a setup time for supplying the address of each next FCM (RFCM, CFCM, TFCM).
As described above, a series of operations (hereinafter referred to as “modify-write”) is read from the entire address space of the FCM. One cycle is lengthened by this read-modify-write, so that the SCAN operation takes time. By the way, in the entire address space, FAIL actually exists and the number to be incremented by +1 is small. In most cases, FAIL does not exist, so the read data is written and updated as it is. That is, the write operation when there is no FAIL is an unnecessary consumption time.
[0024]
In addition, after the SCAN operation for all lines is completed, a SEARCH operation for detecting a line failure is performed next. Since the line fail detected by the SEARCH operation is a line to be rescued unconditionally, the DSCAN operation is performed, and the CFCM and RFCM corresponding to the address position where the failure exists on the line fail is subjected to the subtraction process. There is a need to do. Since it is necessary to access the AFM during the processing period in which the DSCAN operation is performed, the DUT test needs to be performed in a stopped state, which causes a problem that the total test cycle time becomes long.
[0025]
[Problems to be solved by the invention]
As described above, firstly, as shown in FIG. 11, in the SCAN operation in the prior art, the write operation by the read-modify-write is always performed regardless of the presence or absence of FAIL. Since it becomes longer, the total test cycle time becomes longer.
In addition, as described above, secondly, the SEARCH operation for detecting a line failure in the prior art, and the process of subtracting the corresponding CFCM and RFCM by performing a DSCAN operation on the line in which the line failure is detected. In this SEARCH operation and DSCAN operation period, since the DUT test is performed in a stopped state, the total test cycle time is difficult.
[0026]
Therefore, the problem to be solved by the present invention is to provide a semiconductor test apparatus capable of substantially reducing the processing time related to the SCAN operation, the SEARCH operation, or the DSCAN operation for performing DUT repair analysis.
[0027]
[Means for Solving the Problems]
First, in order to solve the above-described problem, the device under test includes at least a memory and a spare cell (spare line) for repairing and replacing a defective cell of the memory, and the semiconductor test apparatus has a memory cell of the memory of the DUT. In a semiconductor test apparatus equipped with a failure analysis memory (AFM) capable of storing fail information obtained by conducting a pass / fail test for each memory cell,
A row counting memory (for example, RFCM) for storing and updating the number of occurrences of defective cells for each row address line by a read-modify-write operation is provided,
A counting memory (for example, CFCM) for a column that stores and updates the number of occurrences of defective cells for each column address line by a read-modify-write operation,
In the SCAN operation, when the failure information read from the AFM detects no failure, the read-modify-write operation of the counting memory is not performed, and only the read operation is performed and the next address is read. Means for controlling (for example, the sequence control unit 40b),
A semiconductor test apparatus having the above configuration and capable of speeding up the counting process of the SCAN operation in the repair analysis operation.
According to the above-described invention, it is possible to realize a semiconductor test apparatus capable of improving the SCAN operation so that the read-modify-write operation is performed only when FAIL exists and reducing the time of the SCAN operation in the repair analysis operation.
[0028]
12 and 13 show the solving means according to the present invention.
Second, in order to solve the above problem, the device under test is a memory device or a system LSI or the like that includes at least a memory and a spare cell (spare line) that repairs and replaces a defective cell of the memory. In a semiconductor test apparatus including a failure analysis memory (AFM) capable of storing, for each memory cell, fail information obtained by testing whether the memory cell of the DUT memory is good or not,
In the repair analysis operation performed in a state where the DUT test is temporarily stopped, the fail information stored in the AFM is read, the number of defective cells generated is counted for each row address line in the memory configuration of the DUT, and the column address When the counting operation for counting the number of occurrences of defective cells for each line is called SCAN operation,
A row counting memory (for example, RFCM) for storing and updating the number of occurrences of defective cells for each row address line by a read-modify-write operation is provided,
A counting memory (for example, CFCM) for a column that stores and updates the number of occurrences of defective cells for each column address line by a read-modify-write operation,
A row and a column for receiving count data read from each counting memory and outputting +1 addition or update data left as count data based on the presence or absence of fail information read from the corresponding AFM Counting means (for example, a fail counting unit)
In the SCAN operation, first, when the fail information read from the AFM detects “0” (that is, PASS), the read-modify-write operation for updating the storage in the counting memory is not performed. Only the read operation is performed. Second, when the fail information read from the AFM is detected as “1” (that is, FAIL), the update data added by +1 by the counting means is written into the counting memory and updated. A sequence control unit 40b for performing a read-modify-write operation,
There is a semiconductor test apparatus which has the above and is capable of speeding up the counting process of the SCAN operation in the repair analysis operation.
[0029]
Third, in order to solve the above-mentioned problem, the device under test is a memory device or a system LSI or the like that internally includes at least a memory and a spare cell (spare line) for repairing and replacing a defective cell of the memory. In a semiconductor test apparatus including a failure analysis memory (AFM) capable of storing, for each memory cell, fail information obtained by testing whether the memory cell of the DUT memory is good or not,
A dual port memory is used as a memory for counting for rows and columns (for example, RFCM, CFCM) for storing the number of occurrences of defective cells for each address line,
A means for separating and accessing the write operation and the read operation of the SCAN operation for counting defective cells in the repair analysis operation by the dual port memory, and enabling the SCAN operation in the repair analysis operation to be speeded up. There is a semiconductor test equipment.
[0030]
If the write operation and the read operation have the same address, the update data counted as fail is temporarily stored without being stored in the dual port memory, and is temporarily held when the write operation and the read operation have different addresses. There is a semiconductor test apparatus as described above, further comprising means for writing the update data that has been stored in the dual port memory.
[0031]
FIG. 18, FIG. 19 and FIG. 20 show the solving means according to the present invention.
Fourth, in order to solve the above problem, the device under test is a memory device or a system LSI or the like that includes at least a memory and a spare cell (spare line) for repairing and replacing a defective cell of the memory. In a semiconductor test apparatus including a failure analysis memory (AFM) capable of storing, for each memory cell, fail information obtained by testing whether the memory cell of the DUT memory is good or not,
In the repair analysis operation performed in a state where the DUT test is temporarily stopped, the fail information stored in the AFM is read, the number of defective cells generated is counted for each row address line in the memory configuration of the DUT, and the column address When the counting operation for counting the number of occurrences of defective cells for each line is called SCAN operation,
A row counting memory (for example, RFCM) that stores the number of occurrences of defective cells for each row address line is provided.
A counting memory (for example, CFCM) for a column that stores the number of occurrences of defective cells for each column address line is provided,
A row and a column for receiving count data read from each counting memory and outputting +1 addition or update data left as count data based on the presence or absence of fail information read from the corresponding AFM Counting means (for example, a fail counting unit)
Apply dual port memory as counting memory,
One access port of the above dual port memory is applied as a read-only port for counting data, continuously generates an analysis address AFMA, continuously reads fail information from the AFM, and corresponds to this to the read-only port. Continuously generating read addresses and continuously reading the count data, the counting means outputs update data in which the fail count value is updated based on the continuous fail information and the corresponding count data,
The other access port of the dual port memory is applied as a write-only port for continuous update data output from the counting means, and a write address that is delayed by a predetermined number of times from the read address on the read-only port side is continuous. Occurs, and the update data is continuously written and updated,
In the write update operation of the write-only port and the read operation of the read-only port, when the addresses accessed by both ports are the same address, the count data read by enabling one read operation side is used as the input data of the counting means. In response, the update data output from the counting means is held as temporary storage data, and the other write operation side prohibits the write operation,
When both ports accessed thereafter have the same address, the stored data is supplied as the input data of the counting means, and the updating is performed by counting up to a predetermined number based on the presence / absence of fail information read from the AFM by the counting means Retain the data as temporary saved data,
When the read address accessed later is different from the write address, the update data obtained by counting and updating the stored data is written to the write-only port and stored and updated.
There is a semiconductor test apparatus which has the above and is capable of speeding up the counting process of the SCAN operation in the repair analysis operation.
[0032]
Fifth, in order to solve the above-described problem, the device under test is a memory device or a system LSI or the like that internally includes at least a memory and a spare cell (spare line) that repairs and replaces a defective cell of the memory. In a semiconductor test apparatus including a failure analysis memory (AFM) capable of storing, for each memory cell, fail information obtained by testing whether the memory cell of the DUT memory is good or not,
If the address line is detected as a line failure as a result of the SEARCH operation when the SCAN operation and the SEARCH operation are performed simultaneously, the SCAN operation and the DSCAN are performed on the next address line in the row or column opposite to the line failure. Perform the operation at the same time,
There is a semiconductor test apparatus characterized in that it is possible to speed up the repair analysis operation.
[0033]
FIG. 14, FIG. 15, FIG. 16, and FIG. 17 show the solving means according to the present invention.
Sixth, in order to solve the above-described problem, the device under test is a memory device or a system LSI or the like that internally includes at least a memory and a spare cell (spare line) that repairs and replaces a defective cell of the memory. In a semiconductor test apparatus including a failure analysis memory (AFM) capable of storing, for each memory cell, fail information obtained by testing whether the memory cell of the DUT memory is good or not,
In the repair analysis operation performed in a state where the DUT test is temporarily stopped, the fail information stored in the AFM is read, the number of defective cells generated is counted for each row address line in the memory configuration of the DUT, and the column address The counting operation for counting the number of occurrences of defective cells for each line is called a SCAN operation, and when the fail count value for each row line or column address line is larger than the number of spare lines on the opposite side, the opposite side This line is called line failure because it cannot be relieved by the spare line, and the operation for checking whether there is a line failure in the row or column address line is called SEARCH operation. Count data of the memory for counting the row or column corresponding to the defective cell When called DSCAN operation subtraction processing operation for performing a target,
A row counting memory (for example, RFCM) that stores the number of occurrences of defective cells for each row address line is provided.
A counting memory (for example, CFCM) for a column that stores the number of occurrences of defective cells for each column address line is provided,
A row and a column for receiving count data read from each counting memory and outputting +1 addition or update data left as count data based on the presence or absence of fail information read from the corresponding AFM Counting means (for example, a fail counting unit)
A SEARCH operation for detecting whether there is a line fail for one of the row and the column is performed in parallel with the SCAN operation, and the fail information at each address position on the address line during the SCAN operation is set to the next address. Means for holding as a previous fail flag (e.g., a pre-fail flag) so that it can be referenced during the SCAN operation of the line;
When a line failure is detected in the address line immediately before the row or column, the count data in which the line failure is detected is cleared to zero, and the address line immediately after the opposite row or column in which the line failure is detected The fail counting operation at each of the above address positions includes simultaneous and parallel execution means for simultaneously executing the SCAN operation and the DSCAN operation in parallel and storing the update data updated in a predetermined manner in the corresponding counting memory,
There is a semiconductor test apparatus that has the above-described configuration and that can perform the SCAN operation, the SEARCH operation, and the DSCAN operation in the repair analysis operation in parallel to speed up the repair analysis operation.
[0034]
FIG. 16 shows the solving means according to the present invention.
As one aspect of the simultaneous execution means for executing the above-mentioned SCAN operation and DSCAN operation simultaneously in parallel,
For example, a fail counting unit 400, a line fail register 70, row address and column side prefail flags RFLFLG and CFLFLG for one address line, a corresponding sequence control unit 40, an address generation unit 60, and a size comparator 90 are provided. The update data is counted based on the count data read from the counting memory, the fail information read from the AFM, and the corresponding previous fail flag data.
First, when there is no previous fail flag, the count is based on normal SCAN operation. When the fail information is present, the count data + 1 update data is output, and when there is no fail information, the count data is left as it is. Output as update data,
Secondly, when there is a previous fail flag, the SCAN operation and the DSCAN operation are executed simultaneously in parallel. When the fail information is present, the count data is output as update data as it is, and when there is no fail information. The update data obtained by subtracting the count data-1 is output,
There is the above-described semiconductor test apparatus characterized by comprising the above.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
An example of an embodiment to which the present invention is applied will be described below with reference to the drawings. Further, the scope of the patent claims is not limited by the description of the following embodiments, and further, the elements and connection relationships described in the embodiments are not necessarily essential to the solution means.
[0036]
The first embodiment of the present invention improves the SCAN operation so that the read-modify-write operation is performed only when FAIL exists, and substantially reduces the processing time related to the SCAN operation. This will be described below with reference to FIG. 12 and FIG. In addition, the element corresponding to a conventional structure attaches | subjects the same code | symbol, and description of the overlapping part is abbreviate | omitted.
[0037]
FIG. 12 shows an internal configuration example of the sequence control unit 40b in the first embodiment.
The main configuration of the sequence control unit 40b is realized by multiplexers MUX10 and MUX16, a counter 12, a decoder 14, flip-flops FF21 to FF24, and a NAND gate NAND26.
[0038]
The counter 12 operates as a binary or quinary counter. That is, as a result of applying the FAIL signal to the selection control terminal S of the MUX 10 and switching the signal supplied to the load terminal LD of the counter 12, it operates as a quinary counter when there is FAIL, and as a binary counter when there is no FAIL. Operate.
[0039]
The decoder 14 supplies a signal obtained by decoding the output signal from the counter 12 to the MUX 10 and MUX 16 and the flip-flops FF 21, 22 and 23.
[0040]
The flip-flop FF21 outputs, as the * FCMOE signal, an inverted signal obtained by retiming the Q0 output signal from the decoder 14 with the synchronization clock CLK.
The flip-flop FF22 outputs an inverted signal obtained as a result of retiming the Q2 output signal from the decoder 14 with the synchronization clock CLK as the * FDOE signal.
The flip-flop FF23 supplies a signal resulting from retiming the Q2 output signal from the decoder 14 with the synchronizing clock CLK to the NAND gate NAND26, and outputs an inverted signal resulting from pulsing with the CLK as the * FCMWE signal. .
[0041]
The MUX 16 receives the FAIL signal at the selection control terminal S, and outputs the Q4 signal from the decoder 14 when there is FAIL, and outputs the Q1 signal from the decoder 14 when there is no FAIL.
The flip-flop FF 24 receives the output signal from the MUX 16 and outputs an INC signal as a result of retiming with the synchronization clock CLK.
[0042]
Therefore, according to the sequence control unit 40b having the configuration shown in FIG. 12 described above, when there is FAIL, it operates as a quinary counter, and as shown in the fail cycle of FIG. The read-modify-write operation is performed in a period of 5 clocks, and the result obtained by adding +1 by the fail counter shown in FIG. 9 is stored and updated in RFCM, CFCM, and TFCM.
On the other hand, if there is no FAIL, as shown in the pass cycle of FIG. As a result, the processing time can be shortened to 2/5. In a normal device test, since the frequency of occurrence of memory cells in which FAIL occurs is extremely low, it can be said that most of them are read operations in two clock periods. As a result, the processing capability of the SCAN operation of the present application can be obtained with a great advantage that it can be substantially 2.5 times faster than the conventional one.
[0043]
The second embodiment of the present invention uses a dual port memory as the RFCM, CFCM, and TFCM. As a result, the read and write operations are separated to shorten the operation cycle of the SCAN operation, thereby increasing the speed. This will be described below with reference to FIGS. In addition, the element corresponding to a conventional structure attaches | subjects the same code | symbol, and description of the overlapping part is abbreviate | omitted.
[0044]
FIG. 19 shows an example of the internal principle configuration of the one-channel counter block unit 120 in the second embodiment.
The main part configuration is different from the conventional component shown in FIG. 9 in that the RFCM, CFCM, and TFCM are changed to dual port memory, the internal configuration of the fail counting unit 300 is changed, and the address match detection unit 50, This is realized with a configuration additionally including flops FF1 to FF5 and an OR gate OR18.
An example of a timing chart according to the configuration of FIG. 19 is shown in FIG. As shown in FIG. 4, this timing chart is a specific example in which the column address side is an example of a 4-cell line configuration. That is, in the address PRAD output from the address format unit 80, the same address value is continuously generated for 4 cycles.
[0045]
The flip-flops FF1, FF2, and FF3 shown in FIG. 19 use the write address WAD (see FIG. 18E) obtained by delaying the address PRAD output from the address format unit 80 by 3 clock cycles in synchronization with the clock CLK. Supply to each write address port (WAn).
The flip-flop FF4 sets the read address RAD (see FIG. 18B) obtained by delaying the address PRAD output from the address format unit 80 by one clock cycle in synchronization with the clock CLK to the port (RAn) of each read address of the dual port memory. To supply.
Thereby, the timing of the write operation and the read operation of the dual port memory can be shifted by 2 clock cycles. As a result, the read operation is performed first, and the count values RRFD, RCFD, RTFD (see FIG. 18C) read from the read data port (RDn) of the dual port memory are input to the fail counter 300.
[0046]
An example of the internal configuration of the fail counting unit 300 is shown in FIG.
The fail counting unit 300 synchronizes the read count value with the FF 6 and then supplies the count value to one input terminal of the adder ADD 1 through the multiplexer MUX 1. The FAIL signal is supplied to the other input terminal at the flip-flop FF 8, A FAIL signal delayed by 3 clock cycles is supplied from FF9 and FF10, and both are added and output.
The output data of the addition result is synchronized with the flip-flop FF11 and then supplied as a WRFD, WCFD, WTFD signal (see FIG. 18F) to the write data port (WDn) of the dual port memory. Writing is updated by the * MWE signal for writing to the WE terminal (see FIG. 18J).
[0047]
However, since the dual port memory is used, if the write address is the same as the read address, and the read operation and the write operation are performed simultaneously, the read data is destroyed by the write operation, so that the read data cannot be read correctly. In order to avoid this, an address match detection unit 50 is provided.
That is, the address coincidence detection unit 50 performs a coincidence comparison between the address PRAD (see FIG. 18A) output from the address format unit 80 and the midway output address signal PWAD (see FIG. 18D) of the flip-flop FF2. If they match, that is, if the read address and the write address match, in order to prevent the read operation and the write operation at the same address, the WINH signal (FIG. 18K, L reference). As a result, the * MWE supplied to the dual port memory by the OR gate OR18 is prohibited (see N in FIG. 18), so that the write operation is not performed. Therefore, read protection of read data is normally performed.
[0048]
However, write update cannot be performed with the read protection. Therefore, the count value for which the write operation is not performed in the fail counter 300 is temporarily stored in the FF 12 by the WINH signal. Next, when a fail having the same address as the count value stored in the FF 12 is input to the fail counting unit 300, the WINH signal is synchronized with the FF 7 and supplied to the selection input terminal (S) of the MUX 1. As a result, the FF 6 The output data of the FF 12 once saved instead of the output data is selectively output and added by ADD1. Then, the correctly added count value is supplied to the dual port memory as the WRFD, WCFD, and WTFD signals, and * MWE (see FIG. 18P, Q) is also output, and normal data is written and stored.
[0049]
The set input terminals (S) of the flip-flops FF1, FF2, and FF3 are all set to “1” by a CLR signal (not shown) output from the sequence controller 40 when the SCAN operation starts. As a result, when the address matches the first address (“0”) at the start of the SCAN operation, the write operation is not prohibited due to malfunction.
Further, the sequence control unit 40 is generated so as to end when the address generation unit 60 returns to “0” after performing both RA and CA up to MAX. Thus, the write operation can be performed with the address match signal WINH set to the logical value “0” at the last address.
[0050]
Therefore, according to the configuration shown in FIG. 19 described above, the read operation and the write operation of the SCAN operation can be separated, and the read operation and the write operation can be performed continuously. This can be realized in one clock period per cell. As a result, as shown in FIG. 11, the conventional processing time is 5 clock periods, so that the processing capability of the present SCAN operation can be greatly increased by a factor of 5 compared to the conventional technology.
[0051]
The third embodiment of the present invention shortens the repair analysis time by simultaneously performing one SEARCH operation on the row or column side during the SCAN operation and the DSCAN operation. This will be described below with reference to FIGS. In addition, the element corresponding to a conventional structure attaches | subjects the same code | symbol, and description of the overlapping part is abbreviate | omitted.
[0052]
FIG. 14 shows an operation principle of the repair analysis operation in which the SCAN operation, the SEARCH operation, and the DSCAN operation are performed simultaneously. In this figure, there are three locations where defective cells exist at the intersections of the row address R1, R2 and R3 and the column address C1 (see FIG. 14A), while there are two spare spare lines for repair. Assume.
[0053]
First, it is assumed that defective cells are counted in the SCAN operation of scanning in the row address direction. At this time, as a result of first scanning the C1 line, “1” is stored in the RFCM as the number of failures for the R1, R2, and R3 lines, respectively. The number of three defective cells “3” on the C1 line (see FIG. 14B) is stored in the CCM line of the CFCM, and at the same time, is detected as a line failure because it is greater than the number of spare rows that can be repaired. . This SEARCH operation is performed simultaneously. Also, “3” is stored in the TFCM as the total failure occurrence value.
Since a line failure is detected in the C1 line, it is necessary to perform a -1 subtraction process of the DSCAN operation. The DSCAN operation is executed in parallel with the scanning operation of the next C2 line. That is, first, when moving to the next column address C2, the CFCM defective cell storage value “3” (see FIG. 14B) of the spare column C1 is cleared to 0 (see FIG. 14C), and at the same time, the C1 line is set. A line fail flag indicating that a failure has occurred is set in the FAM (see FIG. 14D), and information on the repair target line is stored.
[0054]
Here, the data storage format of the RFCM and CFCM of the present invention will be described with reference to FIG. Conventionally, the RFCM and CFCM store the number of occurrences of defective cells, but in the present invention, together with the storage of the number of occurrences of defective cells, the previous one address line (in this case, the C1 line shown in FIG. 14). 1-bit width storage area for storing a pre-fail flag indicating the presence or absence of a defective cell. In FIG. 16, the row side pre-fail flag storage for one address line is RFLFLG, and the column side pre-fail flag storage is CFLFLG.
This pre-fail flag stores the presence / absence of failure for each address of the immediately preceding line until a certain address (for example, the C2 line and R1 line in FIG. 14) is scanned. From this pre-fail flag, it can be determined whether or not each cell on the previous C1 line was defective during the next C2 line SCAN operation. As a result, if a line failure is detected, the number of failures can be subtracted if the prefail flag is found by looking at the prefail flag for each cell in the next C2 line during the SCAN.
At this time, if the fail signal FAIL read from the AFM is “0”, subtraction is performed, but if it is “1”, nothing is performed so that both the DSCAN operation and the SCAN operation can be performed simultaneously. . However, this pre-fail flag can be applied only to the line side starting SCAN. For example, in the example of FIG. 14, only the pre-fail flag stored in the RFCM is applicable to start SCAN from the row address side. Conversely, if SCAN is started from the column address side, only the CFCM pre-fail flag is applicable, and the pre-fail flag on the RFCM side has no meaning.
[0055]
In the above relief analysis operation, the advantage that one of the SEARCH operation and the DSCAN operation in the row direction or the column direction can be executed in parallel during the SCAN is obtained. As a result, the processing time related to the SEARCH operation and the DSCAN operation can be shortened. It is done. However, as shown in FIG. 15B, when a line failure is detected on the last line, since there is no next line, the same line is controlled to be scanned again. The fail signal from is processed so as to be ignored.
[0056]
Next, as an example of a configuration for realizing the above operation principle, an example of an internal principle configuration of the one-channel counter block unit 120 will be described with reference to FIG.
The main configuration is changed from the conventional component shown in FIG. 9 to a memory capable of storing the pre-fail flag for the RFCM, CFCM, and TFCM, the internal configuration of the fail counting unit 400 is changed, and the line fail register is changed. 70 is added, an output signal from the magnitude comparator 90 is added, an output signal from the sequence controller 40 is added, and an output signal from the address generator 60 is added.
[0057]
The signal additionally output by the large / small comparator 90 is an LFAIL signal indicating that a line fail has been detected in the line on the row or column side, and this is supplied to the line fail register 70 and the fail counter 400.
The signal additionally output by the address generator 60 is a CRY signal that is output when moving to the next address line of the row or column address, and supplies this to the line fail register 70 and the fail counter 400.
[0058]
The line fail register 70 receives the LFAIL signal from the large / small comparator 90 at the D input terminal, receives the CRY signal from the address generation unit 60 at the enable input terminal EN, and receives the CRY signal from the large / small comparator 90. The LFAIL signal is latched. The line fail flag LFLFLG that is the latched output is supplied to the fail counter 400, the address generator 60, and the sequence controller 40. According to this, the line fail flag LFLFLG is a flag signal indicating that a line failure has occurred in the immediately preceding line. Using this signal, 1 count subtraction of the number of defective cells in the address line on the opposite side of the line in which line failure occurred (for example, the address line on the column side when there is a line failure in the row address) Can be done inside. However, 1-count subtraction is performed only when the fail signal in the next SCAN is “0”, and if the fail signal is “1”, 1-count subtraction is not performed and is left as it is. This provides an advantage that the SCAN operation and the DSCAN operation can be executed simultaneously.
[0059]
When the address generator 60 receives the line fail flag LFLFLG from the line fail register 70 during the SCAN of the address of the last line, the address generator 60 generates the address of the same line again. Further, at this time, as shown in FIG. 15B, either one of RAMAX and CAMAX is supplied from the address generator 60 to the sequence generator. In response to this, the sequence control unit 40 supplies the * CNTINH signal for inhibiting the fail counting operation by the fail signal to the fail counting unit 400, thereby suppressing double fail counting.
[0060]
An example of the internal configuration of the fail counting unit 400 that performs the above operation is shown in FIG. The constituent elements are AND gates AND1, AND2, AND3, NAND gate NAND1, OR gate OR1, fail subtraction control register R1, subtractor SUB1, adder ADD31, flip-flops FF31, FF32, and bidirectional driver IO1. , And IO2.
[0061]
The conventional fail counting unit has three counting units on the row side, the column side, and the total side, reads the number of failures from the corresponding RFCM, CFCM, and TFCM, adds the number of occurrences of AFM failures, and again returns to the RFCM, A simple operation of storing and updating in CFCM and TFCM was performed. On the other hand, in the present invention, different operations are performed in the fail counters on the row side, the column side, and the total side. This changes depending on the setting condition of the fail subtraction control register R1, and the fail count control is different.
When the repair analysis operation shown in FIG. 14 is performed, * EN1 is logic “1” and EN2 is logic “1” in the fail subtraction control register R1 of the low-side and total-side fail counter 400 shown in FIG. It sets from control CPU so that it becomes. As a result, when there is a line fail in the column address line, the subtractor SUB1 performs a fail subtraction via AND1 when the pre-fail flag is "1" from the bidirectional driver IO2, and when FAIL is "1". When "0" and FAIL are "0", "-1" is supplied to the adder ADD31.
At this time, if there are three FAILs as shown in FIG. 15B in the last line, * CNTINH becomes logic “0”, and the FAIL signal is inhibited by AND2. The ADD 31 adds the fail count value input via the bidirectional driver IO1 and the output of the SUB1. The added value is temporarily held in the FF 31 until the input / output switching of the bidirectional driver IO1 is completed via the AND3, and then output to each FCM (RFCM, CFCM). The input / output switching of the bidirectional drivers IO1 and IO2 is performed by the * FDOE signal output from the sequence control unit 40.
[0062]
On the other hand, in the fail subtraction control register of the fail counter 400 on the column side, the control CPU sets * EN1 shown in FIG. 17 to logic “0” and EN2 to logic “0”. Thus, in the same manner as described above, when there is a line fail in the column address line, the NAND1 output is set to “0” by the LFAIL and CRY signals, and AND3 is prohibited through OR1 to set the number of failures to “0”. At this time, * EN1 is “0” as described above. The FAIL signal is output to each RFCM and CFCM as a pre-fail flag through the FF 32 and the bidirectional driver IO2.
From the above description, the configuration shown in FIG. 16 provides the advantage that the SEARCH operation and DSCAN operation of one side address (row or column address) can be performed simultaneously during one SCAN operation of the repair analysis operation. As described above, there is an advantage that the processing time for the SEARCH operation and the DSCAN operation can be substantially shortened.
[0063]
The technical idea of the present invention is not limited to the specific configuration example of the above embodiment. Furthermore, the above-described embodiment may be modified and applied as desired.
[0064]
【The invention's effect】
The present invention has the following effects in view of the above description.
As described above, according to the present invention, the SCAN operation in which the AFM is accessed to perform the repair analysis process, or the processing time related to the SCAN operation, the SEARCH operation, and the DSCAN operation can be significantly shortened. There is a great advantage that the DUT test suspension period can be greatly shortened. Accordingly, a great advantage that the throughput of the semiconductor test apparatus can be substantially improved is obtained. Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.
[Brief description of the drawings]
FIG. 1 is a conceptual configuration diagram of a semiconductor test apparatus.
FIG. 2 is a diagram illustrating a semiconductor memory chip, a relief block, and a spare cell.
FIG. 3 is a diagram illustrating the principle of repairing a defective chip with a spare cell.
FIG. 4 is a conceptual explanatory diagram showing the arrangement of defective memory cells and counting them.
FIG. 5 is a conceptual explanatory diagram illustrating detection of line failure.
FIG. 6 is a conceptual explanatory diagram illustrating a DSCAN operation.
FIG. 7 is a conceptual explanatory diagram for performing repair analysis after the DSCAN operation.
FIG. 8 is a conceptual configuration diagram of a repair analysis apparatus.
FIG. 9 is a diagram showing the internal principle of a conventional one-channel counter block unit of the repair analysis apparatus.
FIG. 10 is a diagram for explaining a total test cycle time in a semiconductor test apparatus.
FIG. 11 is a timing chart showing a read-modify-write operation of a conventional SCAN operation.
FIG. 12 shows an example of the internal configuration of a sequence control unit according to the present invention.
FIG. 13 is a timing chart showing a pass cycle in which a read-modify-write operation is not performed when there is no FAIL according to the present invention.
FIG. 14 is an operation principle diagram of performing the SCAN operation and the DSCAN operation simultaneously according to the present invention.
FIG. 15 is an explanatory diagram of a data storage format of the RFCM and CFCM according to the present invention, and a diagram for explaining a SCAN operation when a line fail is detected on the last line.
FIG. 16 is a diagram showing the internal principle of the counter block unit for one channel of the repair analysis apparatus according to the present invention.
FIG. 17 shows an internal configuration example of a fail counting unit according to the present invention.
18 is an example of a timing chart according to the configuration of FIG.
FIG. 19 is another internal principle configuration diagram of the 1-channel counter block unit of the repair analysis apparatus of the present invention.
FIG. 20 shows another internal configuration example of the fail counting unit of the present invention.
[Explanation of symbols]
ADD1, ADD31 Adder AND1, AND2, AND3 AND gates FF1 to FF12, FF21 to FF24, FF31, FF32 Flip-flop IO1, IO2 Bidirectional drivers MUX1, MUX10, MUX16 Multiplexer NAND1, NAND26 NAND gate OR1, OR18 OR gate R1 Fail Subtraction control register SUB1 Subtractor 12 Counter 14 Decoder 40 Sequence control unit 50 Address match detection unit 60 Address generation unit 70 Line fail register 80 Address format unit 90 Size comparator 100 Relief analysis device 110 CPU unit 120 Counter block unit (Counter Block unit) )
300, 350, 400 Fail counter DC logic comparator DUT Device under test FAM Fail address memory FC Waveform shaper FM Fail memory PG Pattern generator TG Timing generator RFLFLG Low side prefail flag storage CFLFLG Column side For storing pre-fail flag

Claims (2)

A device under test (DUT) has at least a memory and a spare cell (spare line) for repairing and replacing a defective cell in the memory, and a semiconductor test apparatus obtained by testing the quality of the memory cell in the memory of the DUT. In a semiconductor test apparatus including a failure analysis memory (AFM) capable of storing fail information for each memory cell,
A row counting memory for storing and updating the number of occurrences of defective cells for each row address line by a read-modify-write operation;
A column counting memory for storing and updating the number of occurrences of defective cells for each column address line by a read-modify-write operation;
In the SCAN operation, when the failure information read from the AFM detects that there is no failure, the read memory is not subjected to the read-modify-write operation, and only the read operation is performed and the next address is read. Means to
A semiconductor test apparatus that includes the above and performs counting processing of the SCAN operation in the repair analysis operation. A device under test (DUT) has at least a memory and a spare cell (spare line) for repairing and replacing a defective cell in the memory, and a semiconductor test apparatus obtained by testing the quality of the memory cell in the memory of the DUT. In a semiconductor test apparatus including a failure analysis memory (AFM) capable of storing fail information for each memory cell,
In the repair analysis operation performed in a state where the DUT test is temporarily stopped, the fail information stored in the AFM is read, the number of defective cells generated is counted for each row address line in the memory configuration of the DUT, and the column address When the counting operation for counting the number of occurrences of defective cells for each line is the SCAN operation,
A row counting memory for storing and updating the number of occurrences of defective cells for each row address line by a read-modify-write operation;
A column counting memory for storing and updating the number of occurrences of defective cells for each column address line by a read-modify-write operation;
The row data and the column data that receive the count data read from the respective count memories and output update data that is incremented by one or updated as count data based on the presence or absence of the fail information read from the corresponding AFM Counting means,
In the SCAN operation, first, when the fail information read from the AFM detects "0", only the read operation is performed without performing the read-modify-write operation for updating the storage in the counting memory , Second, when the fail information read from the AFM detects “1”, a read-modify-write operation is performed in which the update data added by +1 by the counting means is written to the counting memory and updated.
A semiconductor test apparatus that includes the above and performs counting processing of the SCAN operation in the repair analysis operation.

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