JPH02116080A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain a reading cycle test without using any external device by providing an internal clock generating circuit and an internal address generating circuit. CONSTITUTION:The title memory is provided with a clock generating circuit 6 which produces a clock at a test, a address generating circuit 7 which produces an address which is applied to a memory 10 via the clock, a control circuit 9a which controls these circuits and writing and reading of memory. Then the circuit 9a is actuated at the test by the input received from a control system input terminal 4a and the clock given from the circuit 6. The output of the circuit 7 is used as the address input of the memory 10 via the switch of a selector 8a. Then the test is carried out with the memory output received from a read output terminal 5. Thus the working of the memory 10 can be confirmed with no use of external devices.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a semiconductor memory having a built-in circuit for testing the memory.

[Prior Art] As shown in FIG. 3, a conventional semiconductor memory 1c is composed of a memory 10 and a control circuit 9C for controlling the same. Since the address input terminal 2b, write data terminal 3a and read output terminal 5 were directly connected to the outside of the semiconductor memory IC, the memory 1
To check the operation of 0, use an external device when using an LSI tester to generate address input, write data, and control system input, and compare the memory output with the expected value generated by the external device. Since the comparison is made within the same system, there is a drawback that semiconductor memory cannot be tested at an operating speed that exceeds the performance of an external device such as an LSI tester.

[Differences between the invention and the conventional semiconductor memory] In contrast to the conventional semiconductor memory described above, the present invention has an address and clock generation circuit or an address and clock as a test circuit inside the semiconductor memory.

The difference is that it includes a data generation circuit and a comparison circuit.

[Means for Solving the Problems] The semiconductor memory of the present invention includes an address generation circuit and a clock generation circuit for generating address data, clocks, etc. during testing inside the semiconductor memory. More specifically, in addition to these circuits, the memory has a selector that connects an external input to an output of an internal address generation circuit when testing the address input of the memory, and a control circuit that controls these. In addition to these circuits, a preferred embodiment of the semiconductor memory of the present invention is a data generation circuit that generates write data during testing, an expected output value of the memory, and an expected output value of the memory output and data output circuit. and a selector that connects memory write data from an external input to an output of an internal data generation circuit during testing.

[Example] Next, the present invention will be explained by examples.

FIG. 1 is a block diagram of an embodiment of the present invention. The semiconductor memory 1a has a memory 10 as its center, and has an address input terminal 2a and a data input terminal 3a as external terminals.

Control input terminal 4a, readout output terminal 5. and a clock monitor terminal 11 that outputs a clock during testing. Further, the semiconductor memory 1a includes a selector 8a that switches the address input of the memory 10 between an external input from an address input terminal 2a and an output from an internal address generation circuit 7, and a variable length ring oscillator that generates a clock during testing. It has a clock generation circuit 6, an address generation circuit 7 centered on a counter that generates an address to be added to the memory 10 based on the clock, and a control circuit 9a that controls these circuits and memory writing/reading. , memory 1
The output of 0 is directly connected to the subsequent output terminal 5.

That is, during testing, the control circuit 9a is controlled by human power from the control system input terminal 4a and the clock from the clock generation circuit 6.
is activated, and the output of the address generation circuit 7 is made the address input of the memory 10 by switching the selector 8a. Then, a test is performed using the memory output from the continuous output terminal 5. In this case, the address generation circuit 7 can also change the test pattern by changing the data combination of the generated addresses, depending on the configuration of the internal counter.

FIG. 2 is a block diagram of another embodiment of the present invention.

In this embodiment, the semiconductor memory lb has the same address input circuit as the semiconductor memory 1a of the previous embodiment, and the write data terminal 3b is manually inputted to the memory 10 via the selector 8b. A data generation circuit 12 mainly composed of a counter generates write data during a test and an expected output value of the memory 10 using a clock generated by a clock generation circuit 60 in accordance with an address generated by an address generation circuit 7. The selector 8b switches the write data input of the memory 10 from the external input of the write data terminal 3b to the output of the data generation circuit 12 during testing. The comparison circuit 14 compares the same data at the readout output terminal 5 of the memory 10 with the expected output value generated by the data generation circuit 12, and outputs a failure signal to the test result output terminal 13 when a failure occurs.

That is, during testing, the control circuit 9b is activated by the input from the control system input terminal 4b and the clock, and the selector 8a is activated.
The output of the address generation circuit 7 is switched to the address input of the memory 10, and the selector 8 is switched in synchronization with this.
b to switch the output of the data generation circuit 12 to the memory 10.
Let the data input be. Then, the test is performed by viewing the signal from the comparison circuit 14 from the test result output terminal 13.

In this embodiment, the address write data and output expected value necessary for testing the memory 10 can be generated in the semiconductor memory lb, and the output of the memory 10 and the expected value can be internally compared. There is an advantage that a self-test of the memory 10 can be performed only by inputting information.

[Effects of the Invention] As described above, the present invention has a clock generation circuit and an address generation circuit inside the semiconductor memory, thereby making it possible to perform successive cycle tests on the semiconductor memory without using an external oscillation circuit or LSI tester. Furthermore, by including a data generation circuit and a comparison circuit, self-tests for writing and reading can be performed inside the semiconductor memory. Therefore, there is an effect that a test such as an LSI test can be performed at an operating speed higher than the performance of an external device.

In particular, testing of semiconductor memories such as ultra-high-speed RAM, which operates at higher speeds than the performance of LSI testers, requires only the input of the control circuit, changing the test frequency and test pattern, and observing the output of the results of whether the memory is good or bad. This has the advantage that it can be performed using a low-speed and inexpensive LSI tester.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of another embodiment of the present invention, and FIG. 3 is a block diagram of a conventional semiconductor memory. la. 2a. 3a. 4a. 8a. 9a. 10. 11. 12. 13. 14. lb. 2b, 3b, 4b. 8b・9b.

Claims (1)

[Claims] In a semiconductor memory consisting of a memory and a control circuit that controls the memory, the test circuit for the memory includes an address generation circuit that generates an address during a test, and a clock that generates a clock during a test of the address generation circuit and the control circuit. What is claimed is: 1. A semiconductor memory characterized by having a clock generation circuit.