JPS60170946A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To perform a dynamic bias test easily by a method wherein an input changing device is built in, and an external input information and a test information are switched by a bias test command. CONSTITUTION:The command BT, to be sent to a buffer 1, is outputted at ''0'' and an input switching circuit 3 is outputted by selecting the external input information D0-Dn by applying a current, and an IC main circuit 4 begins to work. When the command BT is in ''1'' position, the circuit 3 selects and outputs dynamic bias test informations G0-Gn sent from a data generating circuit 2, and the circuit 4 is operated by the information G group. Especially, there are a number of controversial points pertaining to the electric parts used, various wiring and the like when a long hour bias test is performed on a CMOSIC in a high temperature furnace. However, according to this constitution, the test wherein an input signal is changed while a bias test is being conducted can be performed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor integrated circuit that facilitates dynamic bias testing of a semiconductor integrated circuit.

(Prior art) Conventionally, bias testing of semiconductor integrated circuits (hereinafter referred to as IC) involves applying a power supply voltage about 10% higher, fixing the input to 0" or 11", and testing several times in a high-temperature furnace. It was done by leaving it in for ten to several hundred hours.

Therefore, especially complementary MO8IC (hereinafter referred to as 0MO8IC)
That's what it means. ), due to its circuit characteristics, almost no current flows in the circuit when the input signal does not fluctuate, and a normal bias test was insufficient as a load test. Therefore, especially in the case of CMO8IC, a test that varies the input signal (hereinafter referred to as a dynamic bias test) may be performed during the bias test, but the external circuit for varying the input signal is It had many problems and required expensive circuitry.

(1) Since the number of input signals and the terminal positions differ depending on the type of IC to be tested, a dedicated mounting board is required for each type.

(2) Since a large number of signals are all supplied to the high temperature furnace from the outside, a large number of wirings are required, and the electrical components used need to withstand high temperatures for a long time.

(3) A large space is required to mount external circuits.

(Object of the invention) The object of the present invention is to solve the above-mentioned problems.
It is an object of the present invention to provide a semiconductor integrated circuit which allows dynamic competitive bias testing to be easily performed.

(Structure of the Invention) The semiconductor integrated circuit of the present invention has a dynamic bias
input switching means for switching the input signal from the external input data signal to the dynamic bias test data signal according to the output from the test command input means for manually inputting the test command; .

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

In this embodiment, the dynamic bias-test command BT
a buffer 1 as a test command input means for inputting i;
Dynamic bias test 2 and the output from buffer 1 convert the input signal into external input data signal Do-Dn.
Dynamic bias test data signal GO
- Input switching circuit 3 as input switching means for switching to Gn
It consists of the following: A main circuit 4 receives the output of the input switching circuit 3 and outputs output data signals OO to Oni.

Next, the operation of this embodiment will be explained.

First of all, under normal conditions, dynamic
The bias test command BT is set to uO'', and its output becomes UO'' and is supplied to the input switching circuit 30 control input. The input switching circuit 3 is a circuit generally known as a two-manpower multiplexer, and is a circuit that selects and outputs one of the two power inputs according to a control input. In this case, the input switching circuit 3 selects and outputs the external input data signals DO to Dn by receiving °゛0'' to the control input.
The main circuit 4 of this IC uses external input data signals DO to Dn.
Normal operation is performed according to the value of .

Next, a bias test? To do this, set the dynamic bias test command to buffer 1 to ``L'', and input switching circuit 3 in the opposite direction as before.
selects and outputs the dynamic bias test data B GO to On output from the data generation circuit Fq, 2, and the main circuit 4 outputs it from the data generation circuit 2 during the bias write test. Dynamic fist bias
The operation continues using test data No. 8 GO to Gn. The data generating circuit 2 may be a conventionally known circuit, or may be a circuit that sequentially retrieves data stored in advance using a ROM (read-only memory) while changing addresses, or may be a random circuit. It may also be a circuit that generates data.

Figures 2 and 3 show dynamic bias chiad/external input data signals DO~Dn power z t+ 1 pp
Alternatively, when the input switching circuit 3 is fixed to 110'', it is a circuit diagram showing a part of second and third embodiments in which the circuit of the input switching circuit 3 is further simplified. Although both show circuits for only one data, the same applies to other data.

Further, although both FIGS. 2 and 3 show only the input switching circuit, the other circuits are the same as in FIG. 1.

In FIG. 2, the external input data signal DO input to the AND gate 22 is 5'1'' externally during the bias last.
Therefore, when the dynamic bias test command BT is ul'', the inverted data Go of the dynamic bias test data signal GO is inverted by the NAND gate 21 and then passed through the AND gate 22 to the main circuit 4. supplied to

In FIG. 3, the external input data signal DO input to the OR gate 32 is externally fixed at 110" during the bias test, so when the dynamic bias test command BT is "al", the AND gate 31 The input dynamic bias-test data signal GO follows the On gate 32 and is supplied to the main circuit 4.

(Effects of the Invention) As described above in detail, the semiconductor integration of the present invention (b)
The circuit includes a test data signal generation means and an input switching means for switching and outputting an external input data signal and a dynamic bias test data signal output from the test data signal generation means according to a bias test command. This has the effect that a dynamic bias test can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
3 and 3 respectively represent the second embodiment of the present invention. FIG. 6 is a schematic diagram of an input switching circuit according to a third embodiment. 1...Six-valve buffer, 2...Data generation circuit, 3...Input switching circuit, 4...Main circuit, 21...NAND gate, 22 .31...
...AND gate, 32...OR gate, B
T...Dynamic Bias War Testing Order, DQ
-Dn...External input data signal, oO-Gn・
...Data signal for dynamic bias test, OO~On...≠~≠Output data signal.

Claims (1)

[Claims] The method further includes a test command input means for inputting a dynamic bias test command, and an input switching means for switching an input signal to the dynamic bias tester from an external input data signal to the dynamic bias test data signal. Features of semiconductor integrated circuits.