JPS614237A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit which can reduce the time required for testing, by carrying out an output DC test and a function test in parallel. CONSTITUTION:The semiconductor integrated circuit has (n) first output buffers 231-23n, one second output buffer 24, n selector circuits 251-25n which respectively supply the corresponding first output buffers 231-23n with either respective n-bit system output signals 1-n internally generated or a 1-bit DC test signal in accordance with first n-bit control signals, and a selector circuit 26 which supplies the second output buffer 24 with any one bit among the n-bit system output signals in accordance with the first n-bit control signals and which also supplies the second output buffer 24 with the 1-bit DC test signal in accordance with a second 1-bit control signal. Thus, a signal for a function test which should originally be outputted from a first output buffer being subjected to an output DC test is outputted from the second output buffer, whereby an output DC test and a function test are carried out in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor integrated circuits, particularly digital semiconductor integrated circuits, and relates to improvements for reducing the time required for functional tests and output DC tests.

[Technical Background of the Invention and Problems Therewith] Tests for determining the quality of digital semiconductor integrated circuits include Urakashi current test, input DC test, output DC test, function test, and AC test. Among these, the output DC test tests the voltage and current characteristics of the output buffer that supplies internal signals to the signal output terminal, and the overt test tests the logic a capability of the internal circuit. Output D in digital semiconductor integrated circuit
The C test is conducted with the output signal in two states: 1'' level and torque level.

- Conventionally, in semiconductor integrated circuits (hereinafter referred to as ICs) that have not been designed to facilitate DC testing, the output signal during the performance test is , temporarily suspend this functional test and
I'm trying to do a test. Since the signal output terminal is randomly set to torque or torque during the function test, the execution of the function test is stopped many times during the DC test, making it impossible to perform a satisfactory function test. In order to cope with this, conventionally, a test pattern dedicated to the output DC test is prepared and the test is performed. However, in this case, a disadvantage arises in that more testing time is required. That is, the time from D1 to D in this case is the test sequence time t 1 for the DC test, D, C test time 2
The time is the sum of n·t2 (t2 is the time required for the torque of one output terminal or DCC soot at the torque, n is the total number of output terminals), and the function test time t3.

For this reason, in the past, designs have been made to facilitate DC testing in order to shorten the testing time.

FIG. 4 is a circuit diagram showing the configuration of only the output circuit section of a conventional TC designed to facilitate the DC test.

In the figure, 111 to 11n are signal output terminals.

Each of these signal output terminals 111 to 11. The output signals of six inverters 121 to 12n are guided as output buffers. The inverters 121 to 12n are supplied with a signal selected by a corresponding one of the selection circuits 135 to 13n. The above selection circuit 13-13. are supplied with each of the internal system output signals 1 to n and a DC control signal, and depending on the logic level of the DC test signal, the system output signal or the DC control signal is supplied.
The control signal is selectively output to the corresponding inverter 12.

As exemplified by one selection circuit 131, each of the selection circuits 13 is composed of an AND GO 1 15 and two NO GO I 16.17.
3 is a timing chart showing the operation of the circuit shown in FIG. The circuit shown in FIG. 4 switches the system output signal and the DCIIJ control signal according to the logic level of the DC test signal, supplies them to each inverter 12, and outputs them from each output terminal 11, thereby performing functional tests 1 to 1. and D of each inverter 12
It is designed to perform a C test.

That is, this IC enters the output DC test mode by first setting the DC test signal to the torque level. D
When the C test signal becomes a trubel, the AND gate 15 is disabled in each selection circuit 13, and the NOR gate 16 is enabled. As a result, each selection circuit 13 selects a DC control signal.

Next, in this state, a pulsed DC control signal having a time necessary for the DC test is supplied to each selection circuit 13.

According to which DCM all signal, each output terminal 1
1 is alternately set to trubel and trubel according to the output signal of the inverter 12. For example, output terminal 11
In order from 1 to 11, the DC test is performed in the Trubel state and in the Trubel state. In this DC test, a power supply in a tester (not shown) is connected to each output terminal 11, and when the output signal is torbel or torbel, the current flowing through this power line is measured, and the measured value becomes the specified value. This is a test to see if it is true or not. When this DC test is completed for all output terminals, the DC test signal is set to L level to enter the functional test mode. In this mode, in each selection circuit 13, the NOR gate 16 is disabled and the AND gate 15 is enabled. As a result, each selection circuit 13 selects a system output signal. That is, in this case, each output terminal 1
1 outputs internal system output signals 1 to n, and these signals are supplied to a tester (not shown) to perform a logic performance test. The test time in this case is the sum of the DCC soot time 2n-t2 and the function test time t3. This test time is shortened by the test sequence time t1 compared to the IC which is not designed to facilitate C testing as described above.

By the way, I
At C, the tester side a at the time of the DCC soot
T" Output terminal 0 number 11 response" 10 Prepare power supply 01
1. The time required for this DC test, 2n-t2, is 2.t2.
It can be done. However, some recent ICs have an extremely large number of output terminals, about several hundred, and a tester equipped with a corresponding number of power supplies is extremely expensive and impractical. Therefore, conventionally one or two
．． It is common practice to test an IC using a tester equipped with three test power supplies, and as the number of output terminals increases, the time required for testing increases.

In this way, in the past, the output DC test was performed independently from the functional tests 1 to 1, so the test time and
In particular, there is a drawback that the output DC test and the functional test take a long time.

[Objective of the Invention] This invention has been made in consideration of the above-mentioned circumstances, and its purpose is to perform the output DC test and the functional test in parallel, thereby reducing the time required for these tests compared to the conventional method.
An object of the present invention is to provide a semiconductor integrated circuit that can shorten the time required for processing.

[Summary of the Invention] In order to achieve the above object, the present invention includes n first output buffers and one second output buffer,
Supplying either one of the internally generated n-bit system output signals and the 1-bit DC test signal to the corresponding first output buffer based on the n-bit first control signal. n selection circuits for supplying any one bit of the n bit system output signal to the second output buffer based on the first control signal of the n bits; a selection circuit for supplying the one-hit DC test double signal to the second output buffer based on a second control signal to the PITSU 1, the first output buffer being subjected to an output DC test; The output IDC test and the function test are performed in parallel by outputting from the second output buffer the signal for the function test that should originally be output from the second output buffer.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of only an output circuit section of a semiconductor integrated circuit according to the present invention. In the figure, 211 to 21n and 22 are signal output terminals, respectively.

Corresponding output signals from inverters 231 to 23n serving as output buffers are led to each of the signal output terminals 211 to 21n. Further, an output signal of an inverter 24 serving as an output buffer is led to the signal output terminal 22. The inverters 231 to 23. is supplied with a signal selected by a corresponding one of the selection circuits 251 to 25rL. The inverter 24 is supplied with a signal selected by a selection circuit 26. The selection circuits 251 to 25. , the corresponding one of the internal n-bit system output signals 1 to n is directly connected to the DC
The control signal directly outputs the corresponding one of the n-bit test signals 1 to n to each inverter 271 to 27 . Furthermore, the inverters 215 to 2
The corresponding one of the output signals of 7/I is sent to each inverter 2.
They are each supplied via 8 to 28n, respectively. Further, the selection circuit 26 is supplied with the output signals of the inverters 28 to 28n, the DC control signal and the normal signal.

Each of the selection circuits 251 to 25A selectively outputs the corresponding system output signal or DC control signal to the corresponding inverter 23 according to the logic level of the corresponding test signal 1 to n. 25 are a system output signal and an inverter 27, respectively.
The AND gate 31 is supplied with the output signal of the inverter 28 in parallel, the AND gate 32 is supplied with the D CIII m signal and the output signal of the inverter 28 in parallel, and the output signals of both AND gates 31 and 32 are supplied in parallel. It is made up of a Noah gate 33.

The selection circuit 26 sends one of the system output signals 1 to n to the inverter 24 depending on the logic level of the test signals 1 to n, or the DC control signal depending on the logic level of the normal signal. This selection circuit 26 selects and outputs n analogues 1-411 to 41n to which each of the corresponding system output signal f and the corresponding output signal of the inverter 28 is supplied in parallel, and the DC AND gate 42t:3 to which a control signal and a normal signal are supplied in parallel and these AND gates 4°1! or 4
It is composed of a NOR gate 43 to which the output signals of 1n and 42 are supplied to the normal 5IJ.

Next, the operation of the circuit configured as described above will be explained using the timing chart shown in FIG.

First, the normal signal is set to H level, and all test signals @1 to n are set to L level. Since each test signal 1 to n is set to L level, the output signals of inverters 271 to 27n are set to H level, and the output signals of inverters 281 to 28n are set to L level, and each selection circuit 2
51 to 25n, each one of the AND gates 3
1 is enabled and the respective other AND gate 32 is disabled. As a result, the n-bit system output signals 1 to n are output to these selection circuits 251 to 25n, respectively, and the output buffer inverter 231.
Output terminals 211 to 2 via terminals 211 to 23, respectively.
I am guided by 1. Therefore, at this time, a tester (not shown) performs a functional test using the n-bit system output signals 1 to n outputted from the output terminals 211 to 21n.

Also, at this time, since the output signals of the inverters 28 to 28n are all at L level, the AND gates 411 to 41n in the selection circuit 26 are all inhibited. On the other hand, since the normal signal is at the 1'' level, another AND gate 42 in this selection circuit 26 is enabled. In this state, the DC control signal is
If the output signal of the AND gate 42 is set alternately to the L level and the H level, the output signal of the AND gate 42 is correspondingly set to the L level and the H level, and the output signal of the NOR gate 45 that follows is set to the H level and the L level alternately. be done. That is, input signals to the inverter 24 as an output buffer are alternately set to H level and L level, and output signals corresponding to the respective input levels are output from the output terminal 22. Therefore, at this time, a tester (not shown) performs a DCC scan when the output signal of the inverter 24 is at L level and H level.

Once the DCC cycle of the inverter 24 is completed,
Next, the normal signal is set to L level, and only the test signal 1 is set to H level. By setting the normal signal to the L level, the output signal of the AND gate 42 in the selection circuit 26 is always set to the L level regardless of the level of the DC control signal. On the other hand, when the test signal 1 is set to H level, the output signal of inverter 271 is set to L level, and the subsequent output signal of inverter 281 is set to H level. As a result, within the selection circuit 251, one AND gate 31 is disabled and the other AND gate 32 is enabled. Therefore, the selection circuit 251 selectively outputs the DC control signal instead of the system output signal 1. If the DC control signal is set alternately to L level and H level in this state, the output signal of AND gate 32 will also be set to L level and H level correspondingly, and the output signal of 33 are alternately set to H level and L level. That is, input signals of inverter 231 as an output buffer are alternately set to H level and L level, and output signals corresponding to the respective input levels are output from output terminal 211. Therefore, at this time, the tester (not shown)
The output signal of the inverter 231 performs DCC processing in the L level and H level states.

The above inverter 23. When the DC test is being performed, the analogues 1 to 411 in the selection circuit 26 are made operable by the output signal of the inverter 281. Therefore, the system output signal 1 that should originally be output from the output terminal 211 where the DC test is currently being performed is
It is outputted from the output terminal 22 via the AND gate 411, NOR gate 43 and inverter 24 in the selection circuit 26, and since the system output signals K to N are also output during this DC test, also at this time. Functional testing can be performed using the n-bit system output signal.

Thereafter, test signals 2 to n are sequentially set to H level in the same way, and D4 is set during the H level period of each test signal.
CIIJ 1111 signal alternately L level and I''
A DC test is performed on the inverter 23 of the bit corresponding to the test signal set to the H level.

In parallel with this, the output terminal 21 where the DC test is performed
The system signal that should originally be output from the selection circuit 2
A functional test is performed using the n-bit system output signals 1 to n by outputting them from the output terminal 22 via the input terminal 6.

If the function test has not yet been completed at the time when the DC test for all inverters 23 has been completed, the second
As shown in the timing chart in the figure, only a functional test is then performed. Furthermore, if the functional test has already been completed when the DC test is completed, the DC test and functional test are completed at this point.

In this way, in the IC of this embodiment, when performing a DC test on one of the n output terminals 21, the system output signal that should originally be output from this output terminal 21 is
Output from one output terminal 22 provided in advance,
Since the n-bit system output signal is always output, DC tests can be performed in parallel with functional tests. Therefore, the time required for the test can be set to the longer of the functional test and the DC test.If the time required for the functional test and the DC test are the same, the death time will be 11 hours. It can be approximately half the cost of conventional ICs designed to facilitate DC testing.

Incidentally, the number of test signals used in the circuit of the above embodiment is required to correspond to the number of output terminals 211 to 21n, and the number of test signals is greater than one DC test signal in the case of the circuit of FIG. However.

These signals can be generated in between using a circuit such as that shown in FIG.

That is, FIG. 3 is a circuit diagram showing the configuration of a control circuit that generates the n-bit test signals 1 to n, the OC control signal, and the normal signal. In the figure, input terminal 5
1 is supplied with a system reset signal from outside the IC.

The system reset signal supplied to the input terminal 51 is (m-+-1) via two inverters 52 and 53.
The bit binary counter 54 is supplied as a reset signal. The DC control signal supplied to yet another input terminal 55 is supplied as a clock signal to the binary counter 54 via an inverter 56, and is also supplied to the internal counter via the inverter 56 and another inverter 57. It is supplied to each of the selection circuits 25 and 26 as a DC control signal. The (m+1) bit count signal of the binary counter 54 is supplied to a decoder 58 in parallel. The decoder 58 generates the n-bit test signals 1 to n whose H level period is sequentially shifted from the (m+1)-bit count signal of the binary counter 54, and also generates the normal signal having a predetermined period. .

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications are possible. For example, in the above embodiment circuit, a case has been described in which the selection circuit 25.2G is configured with an AND gate or a NOR gate, but it goes without saying that this may be configured using other gate circuits.

[Effects of the Invention] As explained above, according to the present invention, the output DC test and the functional test are performed in parallel, so the time required for these tests can be reduced compared to the conventional method. The circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of the output circuit section of a semiconductor integrated circuit according to the present invention, FIG. 2 is a timing chart of the above embodiment circuit, and FIG. 3 shows signals used in the circuit shown in FIG. 1. FIG. 4 is a diagram showing a control circuit, FIG. 4 is a circuit diagram of a conventional semiconductor integrated circuit, and FIG. 5 is a timing chart thereof. 21.22... Signal output terminal, 23.24... Inverter (signal output means), 25... Selection circuit, (first
selection means), 26... selection circuit (second and third selection means), 27.28... inverter.

Claims (5)

[Claims] (1) n first signal output means and one second signal output means, and either one of each internally generated n-bit system output signal and 1-bit DC test signal, n first selection means for guiding the corresponding first signal output means based on the n-bit first control signal; and n-bit system output based on the n-bit first control signal. a second selection means for guiding any one bit of the signal to the second signal output means; and a second selection means for guiding any one bit of the signal to the second signal output means; A semiconductor integrated circuit comprising: third selection means leading to output means. (2) The semiconductor integrated device according to claim 1, wherein each of the n first signal output means and the one second signal output means is constituted by an output buffer having a signal inversion function. circuit. (3) a first AND circuit in which each of the n first selection means output-controls the system output signal of the corresponding bit according to the logic level of the first control signal of the corresponding bit; and a second AND circuit that controls the output of the DC test signal according to the logic level of the first control signal of the corresponding bit, and the output signals of the first and second AND circuits are parallel. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is comprised of an OR circuit supplied to the circuit. (4) The second selection means includes n AND circuits that control the output of each of the n-bit system output signals based on each of the n-bit first control signals, and The semiconductor integrated circuit according to claim 1, comprising an OR circuit to which output signals of the product circuit are supplied in parallel. (5) The semiconductor integrated circuit according to claim 1, wherein the third selection means includes an AND circuit that controls output of the 1-bit DC test signal based on the second control signal. circuit.