JPH01237474A - Scanning test circuit for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable the test of a circuit related to an input-output of a bus line without letting an excessive current flow, by a method wherein only data held in one set of data latch means are outputted to the bus line at the time of a scanning test. CONSTITUTION:FF circuits 1-3 which are data latch circuits have scanning function respectively. An output of the FF circuit 1 is supplied to a combination circuit 6 other than the FF circuits. Outputs of four FF circuits 2 in one set are supplied in parallel to four bus lines 9 through bus drive circuits 81-84 respectively. In the case when an ordinary operation is executed in such a circuit as having the above construction, a signal of 'L' level, for instance, is supplied to a bus control terminal 12. Thereby an output of the FF circuit 3 is selected in each of switching circuits 111-114 and a signal is supplied to the circuit 8 corresponding thereto. Thereby the outputs of the FF circuits 2 in four sets each comprising four of these circuits are outputted in parallel to the four bus lines 9 through the circuits 81-84 selected in accordance with the respective outputs of the FF circuits.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Field of Industrial Application) This invention provides a scan test circuit for a semiconductor integrated circuit device;
In particular, the present invention relates to a scan test circuit for a semiconductor integrated circuit device having a bus line.

(Prior Art) Large-scale semiconductor integrated circuit devices (hereinafter referred to as LSI) often incorporate a scan test circuit for checking circuit operation. What is this scan test?
By reconfiguring the wiring so that all data latch circuits such as flip-flop circuits installed inside I are in series, and serially supplying test data from the ends of the data latch circuits that are in series. The initial value of each data latch circuit is set, and then the entire LSI is operated to compare the output data from the output terminal and the data latch circuit with expected values to determine whether the LSI is good or bad.

However, in conventional LSIs having bus lines, there is a problem in that such a scan test cannot be performed on circuits related to the bus lines.

FIG. 4 is a circuit diagram showing the configuration of a conventional LSI scan test circuit having a bus line. This LSI is provided with, for example, four bus lines 41. 42.4
8 and 44 are flip-flop circuits each having a scan function. Each of these flip-flop circuits 42.
43 and 44 are provided with a normal data input terminal and output terminal Q, a serial input terminal SL, and a serial output terminal SO, respectively, and as shown in the figure, the serial output of the previous flip-flop circuit or the subsequent flip-flop circuit is provided. All the flip-flop circuits are wired in series to make the circuit serial. Then, the serial input terminal SI of the flip-flop circuit 42 at the frontmost stage
is connected to the scan-in terminal 45, and the serial output terminal SO of the flip-flop circuit 44 at the last stage is connected to the scan-out terminal 46.

The outputs of some of the flip-flop circuits 42 are supplied to combinational circuits 47 other than the flip-flop circuits, and the outputs of the flip-flop circuits 43, which are made up of four flip-flop circuits, are supplied via each bus drive circuit 48. The four lotus lines 41 are each supplied in parallel.

Each of the bus drive circuits 48 is composed of four clocked inverters 49, and the clocked inverters 49 in each of the bus drive circuits 48 are controlled by the outputs of the four AND gate circuits 50 and their inverted signals. It is now possible to do so. One input terminal of each AND gate circuit 50 is connected in parallel to the bus control terminal 51, and the other terminal is connected to the output terminal Q of the flip-flop circuit 44.

When performing a scan test, use the scan-in terminal 45.
Initial values of each flip-flop circuit 42.48° 44 connected in series are set by inputting test data virtually. Next, when the entire LSI is operated, the data output from the output terminal 52 of the combinational circuit 47 is compared with the expected value, and the contents of the flip-flops connected in series are read out from the scan-out terminal 46 and the expected value is compared to

By the way, when performing this scan test, conventionally,
By supplying a “L” level signal to the bus control terminal 51 and setting the output of each AND gate circuit 50 to “L” level, the output states of all clocked inverters 49 in all bus drive circuits 48 are controlled. It is set to high impedance. The reason for this is that the outputs of the clocked inverters 49 in different bus drive circuits 48 connected to the same bus line 41 are not necessarily at the same level, and when they reach different levels, there is an excessive This is because a current flows. Therefore, during a scan test, the output state of all clocked inverters 49 in all bus drive circuits 48 is set to high impedance to prevent the above-mentioned excessive current from flowing.

Incidentally, normally, a large number of gate circuits (not shown) to which signals on the bus are supplied are connected to the bus line. Therefore, in the past, it was only possible to test circuits related to outputs to these bus lines and inputs from the bus lines, and defects caused by these circuits could not be discovered.

(Problem to be solved by the invention) As described above, in the scan test circuit of a semiconductor integrated circuit device having a conventional bus line, data is not output on the bus line during the scan test. The disadvantage is that it is not possible to test all inputs and outputs.

The present invention has been made in consideration of the above circumstances, and its object is to provide a scan test circuit for a semiconductor integrated circuit device that is capable of testing circuits related to bus lines and bus lines.

[Structure of the Invention] (Means for Solving the Problems) A scan test circuit for a semiconductor integrated circuit device according to the present invention provides a scan test circuit for a semiconductor integrated circuit device having a plurality of bus lines. A plurality of sets of data latch means are provided for each set of data latch means, and the data held in each set of data latch means is transferred to the plurality of buses based on a control signal. An output control unit that outputs data in parallel on the line and an output control unit provided corresponding to each set of data latch means during a scan test are sequentially selected, and the data held by each data latch means is transferred to the plurality of data latch means. and control means for outputting on the bus line.

(Function) By outputting only the data held in one set of data latch means on the bus line during a scan test, the circuits related to the input/output of the bus line can be tested without causing excessive current to flow between the power supplies. It can be performed.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of a scan test circuit according to the present invention. 1 and 23 are flip-flop circuits each having a scanning function. Each of these flip-flop circuits 1, 2, and 3 is provided with a serial input terminal Sl and a serial output terminal SO in addition to the normal input terminal D1 and output terminal Q, and as shown in the figure, the previous flip-flop circuit All the flip-flop circuits are connected in series so that the serial output of the flip-flop circuit becomes the serial input of the subsequent flip-flop circuit. The serial input terminal SI of the first-stage flip-flop circuit 1 is connected to the scan-in terminal 4, and the serial output terminal SO of the last-stage flip-flop circuit 3 is connected to the scan-out terminal 5.

The outputs of some of the flip-flop circuits 1 are supplied to combinational circuits 6 other than the flip-flop circuits. This combinational circuit 6 is provided with a plurality of input/output terminals 7.

In addition, four flip-flop circuits 2, each consisting of four flip-flop circuits,
The outputs of are respectively supplied in parallel to the four bus lines 9 via the respective bus drive circuits 81 to 84.

Each of the above-mentioned bus drive circuits 81 to 84 is composed of four clocked inverters 10, and the clocked inverters 10 in each of these bus drive circuits 8, to 84 are output from each of the four switching circuits 111 to 114. It is now controlled by. A signal from the bus control terminal 12, an output from each of the flip-flop circuits 3, and an output from the bus output control signal generation circuit 13 are input to each of these switching circuits 111 to 114, respectively. Each of the switching circuits 111 to 114 supplies a signal corresponding to the output of the flip-flop circuit 3 or the output of the bus output control signal generation circuit 13 to the corresponding bus drive circuit 8 based on the signal of the bus control terminal 12. do.

The bus output control signal generation circuit 13 includes four D-type flip-flop circuits 14, which are connected in series in multiple stages, and the output of the last stage is fed back to the front stage. ~144. These four flip-flop circuits 14. ~14
4, the clock signal supplied to the clock terminal 15 is input in parallel. Further, the first stage flip-flop circuit 141 is set based on the data supplied to the preset terminal 16, and the remaining flip-flop circuits 142 to
14,1 is reset based on data supplied to terminal 16.

Then, each of the four flip-flop circuits 14° to 1
44 outputs BCI to BC4 are each of the four switching circuits 11 mentioned above.
1 to 114.

When performing normal operation in a circuit with such a configuration, a signal of, for example, L" level is supplied to the bus control terminal 12. As a result, each switching circuit 11 selects the output of the flip-flop circuit 3, and the corresponding bus drive circuit 8
are supplied with complementary signals. As a result, the outputs of the four sets of flip-flop circuits 2 are connected to the four bus lines 9 via the bus drive circuits 81 to 84 selected according to the output of each flip-flop circuit 3. Output in parallel.

When performing a scan test, use scan-in terminal 4.
data for initial setting from flip-flop circuits 1 and 2.
．． 3 in sequence. And bus drive circuit 8. Data is set to four sets of flip-flop circuits 2, each consisting of four flip-flop circuits 2 to which 84 are connected.

In addition, in this case, the lotus control terminal j2
For example, a control signal of "H" level is supplied to. As a result, in each of the switching circuits 1 to 114, the output of the bus output control signal generation circuit 13 is selected and output instead of each flip-flop circuit 3.

Also, during this scan test, use the preset terminal]6
data is supplied to the terminal, and a clock signal is sequentially supplied from the clock terminal 15. When the first clock signal is supplied to the clock terminal 15, first the flip-flop circuit 141 is set, and the other flip-flop circuits J42 to J, l are set.
L is reset. Thereafter, as shown in the timing chart of FIG. When supplied, the bus drive circuit 81 operates, and the contents of a set of flip-flop circuits 2 connected to the bus drive circuit 8 are output onto the bus line 9.

As a result, data is output from the terminal 7 of the combinational circuit 6 via a gate circuit (not shown) to which the signal on the bus line 9 is supplied. Therefore, by comparing the output data at this time with the expected value, the status of the bus line itself and the gate circuits connected to the bus line can be tested, and defects caused by these circuits can be discovered. .

Furthermore, at this time, the other control signals BC2 to BC4 are all set to the "L" level, and the output states of the bus drive circuits 8□ to 8□ to which these control signals are supplied are set to high impedance. Therefore, there is no fear that current will flow between the power supplies between the operating bus drive circuit 81 and the other bus drive circuits 82-8,1.

After reading the contents of the set of flip-flop circuits 2 to which the hash drive circuit 81 is connected, a clock signal is supplied to the clock terminal 15 again. As a result, as shown in FIG. 2, only the control signal BC2 generated by the bus output control signal generation circuit 13 becomes "H" level, and this signal B
By supplying C2 via the switching circuit 112, the bus drive circuit 8□ operates, and the contents of a set of flip-flop circuits 2 to which this bus drive circuit 82 is connected are output onto the bus line 9. A test similar to the one above is performed.

Hereinafter, by sequentially supplying clock signals as shown in the timing chart of FIG.
In the order of CI, . . . , the control signals are set to the 'H' level, and the bus drive circuits 83, 8, 1, 81, .

In this way, in the scan test circuit of the above embodiment, the output of the flip-flop circuit connected to the bus line is output on the bus line for testing. Can test circuits. Moreover, the output of any one of the plurality of sets of flip-flop circuits connected to the bus line is selected by the hash drive circuit and outputted onto the bus line.
In the other sets of flip-flop circuits, the output state of the bus drive circuit is kept in a high impedance state, so that it is possible to prevent excessive current from flowing between the power supplies during testing.

FIG. 3 is a circuit diagram showing a specific configuration of the switching circuit 11 and one clocked inverter 10 in the bus drive circuit 8 to which the output thereof is supplied in the circuit of the above embodiment. The switching circuit 11 is an inverter 2], two AND gate circuits 2
2.23 and an OR gate circuit 24.

The output of the flip-flop circuit 3 is connected to one input terminal of an AND gate circuit 22, and the signal supplied to the bus control terminal 12 is connected to the other input terminal of the AND gate circuit 22 via an inverter 21. Further, the output of the bus output control signal generation circuit 13 and the signal supplied to the bus control terminal 12 are supplied to one and the other input terminals of an AND gate circuit 23. The outputs of both AND gate circuits 22 and 23 are supplied to an O'R gate circuit 24, and the output of this OR gate circuit 24 is supplied to the bus drive circuit 8.

On the other hand, the clocked inverter 10 in the bus drive circuit 8 is at the power supply potential V. two P-channel MO3 transistors 3 each connected in series between C and ground potential VSS
1.32 and N-channel MOS transistor 33.34
It consists of The output signal from the switching circuit 11 is supplied to the gate of the transistor 31 via an inverter 35 provided in common to the four clocked inverters provided in each bus control circuit.

Further, the output of the corresponding flip-flop circuit 2 is supplied to the gates of the transistors 32 and 33. Furthermore, the output signal from the switching circuit 11 is supplied to the gate of the transistor 34.

Here, when the signal at the bus control terminal 12 is at the "L" level, the switching circuit 11 selects the output of the flip-flop circuit 3. On the other hand, the signal at terminal 12 is “H”
” level, the switching circuit 11 selects the output from the bus output control signal generation circuit 13. When the signal at the bus control terminal 12 is at the “H” level, that is,
Bus output control signal generation circuit 13 during scan test
When the output from the AND gate circuit 23 and the OR gate circuit 24 is at the "H" level, the outputs from the AND gate circuit 23 and the OR gate circuit 24 are at the "H" level, and the transistors 31 and 34 of the clocked inverter 10 in the bus drive circuit 8 are turned on. . Therefore, at this time, clocked inverter 10 becomes operable. On the other hand, the output of the bus output control signal generation circuit 13 is “L”.
In the case of "level", the outputs of the AND gate circuit 23 and the OR gate circuit 24 become "L" level.

At this time, the clocked inverter 1 in the bus drive circuit 8
0 transistors 31 and 34 are both turned off,
The output state becomes a high impedance state.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications are possible. For example, in the above embodiment, the case where four bus lines were provided in the LSI was explained, but in general, in a jSI that has a bus line in which about 10,000 gate circuits are integrated,
There are 16 to 32 bus lines. Therefore, when implementing this invention in such an LSI,
A number of clocked inverters corresponding to the number of bus lines may be provided in the bus drive circuit. In addition, the number of bus drive circuits only needs to be provided according to the LSI.
In this case, the control signals generated by the bus output control signal generation circuit 13 may be generated in accordance with the number of bus drive circuits.

[Effects of the Invention] As described in detail above, according to the present invention, in a semiconductor integrated circuit device having a bus, it is possible to test circuits related to the bus line and the bus line.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a scan test circuit according to the present invention, FIG. 2 is a timing chart of the circuit shown in FIG.
FIG. 3 is a circuit diagram showing the configuration of a part of the circuit of FIG. 1, and FIG. 4 is a circuit diagram showing the configuration of a conventional scan test circuit. 1.2, 3.14+~144...Flip-flop circuit, 4...Scan-in terminal, 5...Scan-out terminal, 6...Combination circuit, 7...Output terminal, 8
1 to 8, ... bus drive circuit, 9 ... bus line, 1
0...Clocked inverter, 111-114...
Switching circuit, 12... bus control terminal, 13... bus output control signal generation port, 15... clock terminal, 16...
・Preset terminal.

Claims (1)

[Scope of Claim] In a semiconductor integrated circuit device having a plurality of bus lines, a plurality of sets of data latch means each holding test data supplied from the outside during a scan test; an output control section that is provided for each data latch means and outputs the data held in each set of data latch means to the plurality of bus lines in parallel based on a control signal; A semiconductor integrated circuit device comprising control means for sequentially selecting output control units provided corresponding to the means and outputting data held in each data latch means onto the plurality of bus lines. scan test circuit.