JPS63235874A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable evaluation of performance per test unit, by providing a switch at the front stage of a test unit for testing by a scan design to control a clock of a latch circuit so arranged to be a shift register. CONSTITUTION:To apply an input signal for testing of a test units 11 into which a logic circuit is divided, input side latch circuits 60a and 60b so arranged to be a shift register are provided on the input side of the test units 11 while output side latch circuits 61a and 61b are provided on the output side of the test units 11 to receive response output of the test units 11 to be compared with an expected value. Switches 12a and 12b are provided between the test units 11 to be compared with an expected value. Switches 12a and 12b are provided between the test units 11 and the latch circuits 60a and 60b separately to simultaneously input multiple bits of output signals from corresponding latch circuits 60a and 60b into multiple bits of input of individual test units 11. Then, clocks of latch circuits 61a and 61b are controlled with the switch 12a and 12b to prevent accidental inflow of data into the test units 11 thereby enabling evaluation of performance per test unit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having an auxiliary circuit for enabling performance evaluation of a semiconductor integrated circuit.

[Conventional technology]

Conventionally, level sensitive scan design (hereinafter L
(abbreviated as SSD) consists of two design methods. One of them is level sensitive, which attempts to normalize variations in AC characteristics, and consists of a latch circuit using a multiphase clock.

Another scan design is to use a serial shift register to set an arbitrary value to a storage element within an LSI (considered a latch in this case) from an external terminal, or to observe the result. It consists of the constructed design method.

FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit device of this kind. In the figure, 1 is a primary input, 2 is a shift-in terminal, 3 is a clock A, 4 is a clock B, and 5 is a block diagram showing a conventional semiconductor integrated circuit device.
is system black, ri, 6a.

6b is a shift register configured Sea 1 Sochi circuit (hereinafter SR
7 is a shift mode switching signal, 8 is a test unit, 9 is a test pattern input terminal, and 10 is an output terminal to a comparator.The circuit to be tested can be tested by using a latch. It can be divided into combinational circuits as a unit.

Next, the operation will be explained.

First, give an initial value to primary human power 1. The mode of 5RL6a is switched by the shift mode switching signal 7, and then a test pattern is set from the shift-in terminal 2. Among them, input the shift clock in the order of clock A4 and clock B5 and set the value to 5RL6a, and then 5R.
Switch the operation mode of L6a from shift mode to normal mode, input system clock 5 and take in data to 5RL6a, switch mode of 5RL6a again from normal mode to shift mode and input clock B5. By sequentially inputting the shift clock of clock A4 and taking out the value of 5RL6a, performance evaluation, that is, whether test unit 8 is malfunctioning, can be performed by comparing the data obtained in this way with the expected output value. to decide.

[Problem that the invention seeks to solve]

Conventional semiconductor integrated circuit devices are configured as described above, so when performing a scan design test on a semiconductor integrated circuit, even while setting values in 5RL6, the data of the bits that have already been set will be included in the test unit. It ends up. Also,
It was possible to evaluate the circuit from the outside, but it was not possible to evaluate the inside of the circuit.

This invention was made in order to solve the above-mentioned problems, and provides a semiconductor integrated circuit device that can control the input of test data when testing semiconductor integrated circuits using scan design and perform evaluation on a test-by-test basis. The purpose is to obtain.

[Means for solving problems]

The semiconductor integrated circuit device according to the present invention is provided with a switch at the front stage of each test unit so that inputs can be input simultaneously to a plurality of input signal lines in each test unit. Further, an inverted signal of the expected output is inputted in advance to the latch on the output side.

[Effect]

The semiconductor integrated circuit device according to the present invention can prevent data from inadvertently flowing into the test unit by arranging the switch at the front stage of the test unit.

In addition, by putting the inverted data of the expected output into the latch circuit on the output side of the shift register configuration, after a certain time,
Compare the signal output from the test unit with the expected output. If the signal has already reached the latch circuit after a certain period of time, the expected output will be the same value. If the signal has not reached the latch circuit, an inverted signal value has been entered, so the test unit Performance can be evaluated.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, which has test units each having a 2-bit person and an output line.

Components in FIG. 1 that are the same as those in FIG. 2 are given the same reference numerals and their explanations are omitted. In FIG.
L, 61a, 61b are output side SRL, 12a, 12b
is a switch. 13 is 5RL61a, 61 on the output side
This is a clock control line placed at the clock input terminal of .b.

Next, the operation will be explained.

In a conventional test device, if the same signal value is input while setting a value in SRL, the signal value of the previous stage will flow into the test unit.

However, in this embodiment, such an inflow can be prevented by providing the switches 12a and 12b.

In addition, since the output-side 5RLs 61a and 61b contain the inverted signal of the periodic output, the input-side SRL switch is set to 1.
Turn on 2a and 12b at the same time, and after a certain time (1), 5R
Assuming that the clock control line 13 is changed to catch data at L61a and 61b, compare that data with the expected output, and if the data reaches the test unit output after t time, the expected output has been output. If the expected performance is not obtained due to a failure or a design defect and the data does not reach the output per test unit after t time, an inverted signal of the expected output is output, and this allows evaluation of the quality of the test unit.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device according to the present invention, in order to test by scan design, a switch is provided at the front stage of the test unit and the clock of the latch circuit having a shift register configuration is controlled. This has the effect of making performance evaluation possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional semiconductor integrated circuit device. In the figure, 60a, 60b, 61a, 61b are latch circuits (SRL), 11 is a test unit, 12a, 12b
is a switch, and 13 is a clock control a line. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) A semiconductor integrated circuit device including a logic circuit, the input side having a shift register configuration provided on the input side of each test unit in order to apply a test input signal to the test units into which the logic circuit is divided. A latch circuit, an output latch circuit with a shift register configuration provided on the output side of each test unit to receive the response output of each test unit to be compared with the expected value, and a latch circuit between each test unit and each input latch circuit. 1. A semiconductor integrated circuit device comprising: a switch for simultaneously inputting a plurality of bits of output signals from a corresponding input-side latch circuit to the plurality of bits of input in each test unit. (2) The semiconductor integrated circuit device according to claim 1, wherein each of the output side latch circuits receives data from a corresponding test unit in accordance with the timing of a clock control signal. (3) The semiconductor integrated circuit device according to claim 1, wherein each of the output-side latch circuits receives an inverted signal of the expected output from the corresponding test unit prior to evaluation of the corresponding test unit. .