JPS62267678A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress an increase of the number of elements by connecting storage elements of a circuit by a scan path, driving all circuits by level sensitive, and also, constituting the storage element of one piece of latch. CONSTITUTION:All shift register latches SRL connected by a shift path SP are constituted of one piece of latch. The adjacent latches are operated by different clocks. The SRL 5 which becomes an input of some logic circuit which becomes a test unit, and the SRL 7 which does not become an input yet are connected alternately by one piece each. Also, the SRL 6 which has been an output of the logic circuit, and the SRL 7 which does not become an output yet are connected alternately by one piece each. In this way, setting of an input pattern, and fetching of an output pattern can be executed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuits, and particularly to reduction of the number of elements in a repercussive scan design (hereinafter referred to as L8SD) circuit. It is.

[Conventional technology]

The configuration of a conventional LSSD circuit will be explained with reference to FIG. In the LSSD circuit, the storage elements in the non-LSSD circuit are
Shift-register latch (hereinafter referred to as S) with latches
(referred to as RL) vo: Therefore, the circuit is made up of several logic circuits 1:
Testing is facilitated by dividing the circuit and executing the circuit test for each logic circuit unit C2. 151.161 in Figure 4 is SRL, (41 is SRL151
．． This is a logic circuit that is tested using SRL (61).SP is a shift path that connects SRL.

An example of the configuration of SRL151.161 used in FIG. 4 is shown in Figure I. (9) is an overall diagram of the SRL configuration, αυ is a latch. SM is a mode switching signal, which controls whether to take in a shift input signal or a data input signal. sr is a shift input signal, DO is a data input signal, QO is a data output signal, and SO is a shift output signal.The shift input signal S is taken in through the shift path SP, and the shift out output SO becomes the shift input signal for the next SRL through the shift path SP. In order to make the exchange of signals through the shift path level sensitive, the 8RL has a configuration C including two latches and is driven by clocks T1.O whose phases do not overlap.

Next, the operation will be explained. In normal operation, the mode switching signal CM is set to O so that the data input DO is taken into the SRL. In this case, the shift input signal sr does not participate in the operation at all.

When performing a test, first the mode switching signal SM is set to 1 and the shift input signal SI is taken in. Logic circuit (4) to be tested through shift path SP
5RL (51 two-person kabatan) is set as the input for 1. The pattern is a logic circuit (411m input, output is 5RL16
1: Incorporated. This result is taken out through shift path SP and the logic circuit (4) is tested. S.R.L.
When setting data to 151 through shift path SP, or when taking out data from 8 RL (51 through shift path SP), CS RL has two latch recesses, αυ, to make the operation level sensitive.
These operate with clocks Tl, 0 whose phases do not overlap.

[Problem that the invention seeks to solve]

As shown above, in the conventional LSSD circuit, all memory elements must be composed of two latches in order to transfer data to the SRL and retrieve data from the SRL in a level-sensitive manner.l) Number of elements increases (~20%
There was a problem with this.

This invention was made in order to solve the above-mentioned problems, and it is possible to connect the memory elements of a circuit with a scan path and configure the memory element with a single latch while driving the entire circuit in a level-sensitive manner. An object of the present invention is to obtain a semiconductor integrated circuit device in which an increase in the number of elements is suppressed.

[Means for solving problems]

In the semiconductor integrated circuit device according to the present invention, each SRL connected by a shift path is configured with one latch, and adjacent latches are operated with different clocks. You can set the input button and change the output pattern by alternately connecting latches that are not configured as output, and alternately connecting latches that are output from the logic circuit and latches that are not configured as output. This makes it possible to take out the

[Effect]

This circuit is a semiconductor integrated circuit with a shift path design that uses a level-sensitive drive and connects shift paths so that all memory elements can be configured with one latch, thereby suppressing the large increase in the number of elements due to LSSD. It has become a device.

〔Example〕

An embodiment of the present invention will be described below based on FIG.

In Figure 1, (11 is a logic circuit, (21 is an SRL, sp is a shift path connecting SRLs,
SIO of the external terminal is a shift-in signal, and SOO is a shift-out signal output to the external terminal. (31 is the entire circuit. In this way, the circuit has SRL,
The logic circuit (is divided into two, and the test is performed on this divided combinational circuit unit i: To be done 1: Become.

The shift path is as shown in the figure (:, so that the SRL that is the input of a logic circuit that is a certain test unit and the other latches (for example, 5RL that is the input of another logic circuit) are alternated. is tied to

Figure 2 shows an enlarged view of this situation. (41 is one of the logic circuits in Figure 1, +i+ , (61, (71
is the SRL in Figure 141 (same SRL as 21, (51
is S RL which is the input of the logic circuit (41), +61 is S RL which is the output of the logic circuit (41), and (71 is SRL which is neither the input nor the output t: of the logic circuit (4)).

Shift path SP becomes an input to logic circuit (4)! 3RL
t51 and otherwise S RL 17), the output is 8
RL (6) and other 5R17) one by one (
Two are tied. SI is a shift-in signal, and SO is a shift-out signal. TI and T2 are clock signals whose phases do not overlap.

FIG. 3 shows an example of the configuration of the SRL used in the $1 chart, 1% 2 chart. (8) is an overall diagram of 5FIL. (9
) is a latch, SM is a shift mode selection signal for selecting either a data signal or a shift-in signal as a signal to be taken into latch +91, DO is a data input signal, and QO is a data output signal. The number of latches in the SRL consists of only one.

Next, operation 1: will be explained. In normal operation, the shift mode selection signal SM is O (N). At this time, SRL
1m takes data input and shift input has no effect on operation.

The operation during the test will be explained with reference to FIGS. 2 and 3.

The logic circuit (4) is tested here.

When the shift mode selection line SM is set to 1, the shift input signal is taken into the latch. Since the SRLs connected by the scan path are driven by clocks whose phases do not overlap, input data is set to the SRL 151 through the shift path SP in a level-sensitive manner. Input data is logic circuit (4 eyes, 2 people, output is SRL f61
When the result is taken in, the result is similarly taken out through the shift path sp, and it is determined whether or not there is a failure in the logic circuit (4).

In the above example, the input of the SRL is controlled by an AND gate and an inverter gate as shown in FIG. 3, but other logic circuits may be used. In addition, in the above example, the human clock was also used as the shift operation clock and the system operation clock, and the SRL contained only one clock, but by separating the shift operation clock and system operation clock, RL += Two clocks may be input.

〔Effect of the invention〕

As described above, according to the present invention, since it is an LSSD circuit, the SRL can be configured with one latch, which has the effect of reducing the number of elements in the LSSD circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the circuit configuration of an embodiment of the present invention seen from the whole circuit, FIG. 2 is a partially enlarged circuit diagram, and FIG. 3 is a circuit diagram showing an example of the configuration of the SRL used in FIG. 2. FIG. FIG. 4 is a circuit diagram showing an example of the configuration of a conventional LSSD circuit, and FIG. 5 is a circuit diagram showing an example of the configuration of the SRL shown in FIG. 4. +I+...Logic circuit, (2)...Shift register latch (SRL), t41...Logic circuit serving as a test unit, (51...SRL serving as an input to the logic circuit serving as a test unit, (6j...SRL that is the output of the logic circuit that is the test unit, (7),...SRL that is not the input or output of the logic circuit that is the test unit, 181.
...SRL, SP...shift pass, S knee...shift input signal, So-...shift output signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a semiconductor integrated circuit device that has a scan path for circuit testing and drives the circuit in a level-sensitive manner, the memory element in the circuit is composed of a single latch with shift input and shift output functions, and the shift path alternately connects latches that are the input of a logic circuit that is a test unit and latches that are not input to that logic circuit, and also connects latches that are the output of a logic circuit that is a test unit and its logic. A semiconductor integrated circuit device characterized in that it is constructed by alternately connecting latches that do not serve as outputs of the circuit.