JPS6373169A - Logic integrated circuit device - Google Patents

Abstract

PURPOSE:To decrease the number of pins by one pin, by using one pin of data input pins as a multiplex input pin at the time of normal operation, and directly connecting the shift input signal line of a shift register for circuit tests to said pin. CONSTITUTION:When a test pattern is inputted into a shift register 5, the test pattern is also inputted to an inner circuit 1 through an input terminal of the circuit 1, to which a multiplex input pin 6 is connected. since the input terminal is the input terminal of a data type, there is no problem. When the circuit 1 is tested, a clock signal at a clock input pin A is kept at L until the test results are latched in shift register latches 4a-4c. Input through a shift input terminal 7a is inhibited. At the time of normal operation, the clocks of the clock input pins A and B are always L. Therefore, input through the terminal 6a is inhibited. Even if an exclusive use pin is not provided for the shift input, there is no problem in the operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic integrated circuit device, and particularly to a large-scale integrated circuit device using a scan canvas method [Prior Art] FIG. It is a block diagram showing the concept of a logic integrated circuit device using the conventional scan path method, and FIG. 4 shows shift register latches (hereinafter abbreviated as SRL) (4a) to (4h).
FIG. 5 is a block diagram showing a configuration example of a serial shift register (5).

In Figure 3, +11 to (3) are internal circuits, (5) is a serial shift register constituted by SRL (4a) to (4h), (8a) to (8e) are system input pins, (9a) to (9c) is a system output pin.

The configuration of the serial shift register (5) using the SRL of FIG. 4 is as follows.

In Figure 3 or Figure 5, 5RL (4a) in the first stage
Connect its data input terminal (■) to the system input pin (6a), and connect the data output terminal (Q2) to the next stage's 5RL (4b).
) to the data input terminal (1). Thereafter, connections are made in the same manner, and the data output terminal (Q2) of the final stage S RL (4h) is connected to the shift output terminal (7). Each SR
L (4a) to (4h) shift clock input terminal (
A).

(B) are connected in common.

In addition, in FIG. 3, the clock input pin (cl)
.

(C1) are respectively S RL (4a) = (4d),
S RL (4e) to (4h) clock input terminal (C)
connected to. System input pin (8a) is S RL
The system input pins (8b) to (8C) are respectively input to the input terminals of the internal circuit (1), and the data input terminals (D) of SRL (4a) to (4c) are connected to the data input terminals (D) of (4d). are connected to the output terminals of internal circuit +11, respectively.
The output terminals (Ql) of L (4a) and (4b) are respectively input terminals of the internal circuit (2), and SRL (4c)
, (4d) output terminals (Ql) are each SRL
S RL is connected to the input terminal (0) of (4f) and (4e).
The input terminals (D) of (4g) and (4h) are respectively connected to the output terminals of the internal circuit (2).
The output terminals (Ol) of 4h) are connected to the input terminals of the internal circuit (3), and the system output pins (9a) to (9c) are connected to the output terminals of the internal circuit (3), respectively.

Next, the operation will be explained. In the following description, clock input pins (A), (B), (C), (C1), (C
(a), (b), and (b), respectively.
(c), (c+).

It is called (C snow).

First, the S RL (41) shown in FIG. 4 has two modes, a system operation mode and a shift register operation mode. ) is latched into the latch circuit (L, ), and the data output terminal (Q, )
Output from. At this time, clock signals (a), (b
) is kept at "L", and the data from the data input terminal (summer) is not related to the output. Conversely, in the shift register operation mode, the clock signal (C) is kept at "L", and the data from the data input terminal (D) is not related to the output, but the data from the data input terminal (1). , the zero-order clock signal (b) is latched into the latch circuit (Ll) with the clock signal (a) and output from the data output terminal (Ql).
Then, the content of the data launched in the latch circuit (Ll) is latched in the latch circuit (L2), and the data output terminal (
C2).

However, here, the clock signals (a) and (b) are non-overlapping with each other.

As described above, in FIG. 3, in the system operation mode, each SRL receives the clock signal (C,) or (ci).
In the shift register operation mode, the SRL as a whole functions as a serial shift register (5) controlled by clock signals (a) and (b).

Now, the system OI circuit test can be realized by the following procedure.

(i) Testing the shift register (5): Input the test pattern from the shift input pin (6a), and S RL (4
The normal operation of the shift register (5) is confirmed by observing the test result at the shift output pin (7) via a) to (4h).

(ii) Testing of internal circuit (11): Manually input a test pattern to system input pins (8b) to (8c), and transmit test results of internal circuit 111 to SRL (4a) to (4c) using clock signal (cl). Latch and then use the shift register (5) and observe the test result at the shift output pin (7).

(iii) Test of internal circuit (2): Internal circuit (2)
A test pattern is input from the shift input and pin (6a) to S RL (4a) and (4b), which provide input to the internal circuit (2). The test result is sent to S RL (4
g), (4h) and use the shift register (5) to observe the test result at the shift output pin (7).

(iv) Testing of internal circuit (3): Similar to the testing method of internal circuit (2), but the test results are directly observed at system output pins (9a) to (9c).

[Problem that the invention seeks to solve]

Since a logic integrated circuit device using the conventional scan path method is configured as described above, the shift input pin to the shift register is a test-only pin and is not used during normal operation. If there are many pins, the chip size will increase, and the number of pins will be limited due to the puff cage problem, and if there is a pin dedicated to testing, the number of other input/output pins will be overwhelmed.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a logic integrated circuit device using a scan path method in which the number of pins is reduced by one compared to the conventional device.

[Means for solving problems]

The logic integrated circuit device according to the present invention has one pin as a multiple input pin, which is used for normal data input and is also connected to a shift input terminal of a test shift register.

[Effect]

Input data to the shift register in this invention is selectively taken in by an external control signal, so
When data is input from the multiple input pin during normal operation, this data is not taken into the shift register by the control signal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the system input pin (8e) and shift input pin (6a) in Figure 3, which shows an example of a conventional circuit, are used as a shared multiplex input pin (6). However, in this case, the system input pin ( 8e) is a data type input pin. The configuration of FIG. 1 other than this is the same as the configuration of FIG. 3.

In FIG. 1, it will be shown below that even with the above configuration, the essential operation is the same as that of the conventional example shown in FIG.

When inputting a test pattern to the shift register (5), the test pattern is input manually through the input terminal of the internal circuit +I+, which is also connected to the internal circuit (11) and the multiple input pin (6). This is not a problem since it is a data type input terminal.

When testing internal circuit +11, the test result is SRL
The clock signal (a) is kept at ``L'' until it is latched by the shift input terminal (6).
Input from a) is prohibited.

During normal operation, clocks (a) and (b) are always “L”.
”, input from the shift input terminal (6a) is prohibited.

As described above, the same operation as before can be obtained without providing a dedicated pin for shift input.

In the above embodiment, the SRL shown in FIG. 4 was used as the memory circuit constituting the shift register, but it has the same function as in FIG. 4 (the input terminal to be input into the memory circuit can be selected by an external control signal). Similar effects can be obtained using the same means as in the above embodiment with other circuit configurations as long as the above-mentioned function is provided. - An example is shown in FIG.

Note that, of course, even if the number of internal circuits and storage circuits and the overall configuration are different from those in FIG. 1, the same effect can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, one of the data input pins during normal operation is made into a multiplex pin, and the shift input signal line of the shift register for circuit testing is directly connected to that pin, so that the circuit is configured. This has the effect of reducing the number of pins by one pin compared to the conventional one without increasing the number of elements.

[Brief explanation of the drawing]

IF diagram is a block diagram showing a logic integrated circuit device using a scan path method according to an embodiment of the present invention, FIG. 3 is a block diagram showing a conventional example, and FIGS. 2 and 4 are logic diagrams of shift register scratching. FIG. 5 is a block diagram showing the structure of the shift register. (11 to (31) are internal circuits, (4a) to (4h) are shift register launches, (5) are shift registers, (A)
, (B), (CI). (C1) is the Cronk input pin, (6) is the multiplexing pin, (
7) is a shift output pin. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 @4TI! J Figure 5 Procedural amendment (voluntary) 20 Name of the invention Logic integrated circuit device 3, Person making the amendment Relationship to the case Moriya Shiki, representative of the patent applicant 4, Agent 5, Invention of the specification subject to amendment Detailed Explanation Column, Drawing 6, Contents of Amendment (1) Figures 1 and 2 in the drawings are corrected as shown in the attached sheet. (2) The specification shall be amended as follows. Figure 1

Claims (2)

[Claims] (1) A logic integrated circuit device that includes a plurality of internal circuits and a plurality of memory circuits interconnected with the internal circuits, and configures a shift register for testing the internal circuits by connecting the individual memory circuits in series. In particular, a logic integrated circuit device characterized in that an external input pin is connected to a predetermined input terminal of a predetermined internal circuit, and the external input pin is connected to a shift input terminal of the shift register. (2) The logic integrated circuit device according to claim 1, wherein the input terminal of the internal circuit is a data input terminal.