JPS63218878A - Testing circuit - Google Patents

Abstract

PURPOSE:To facilitate a test in a desired circuit part and to shorten a time for the test, by combining a plurality of parallel registers which can select an input. CONSTITUTION:A testing circuit is constituted by parallel registers 10, 20 and 30 comprising scan latch circuits 11-1n, 21-2n and 31-3n respectively, and a signal inputted to a terminal (a) or (b) is outputted selectively by a control signal C(C1-C3). Test data inputted to a terminal I1-In are taken in a circuit part 2a through the register 10 and subjected to processing therein, and then they are outputted to a terminal O1-On through the registers 20 and 30. As a result, it becomes possible to input the test data in parallel to a desired circuit part and to output processed data in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test circuit incorporated into a circuit for testing each circuit part constituting a circuit such as an LSI.

[Prior Art] As the design of circuits such as LSIs becomes more complex, the testing thereof also becomes more complex. In such a case, a test circuit may be installed between each circuit part constituting the circuit, so that tests can be suitably performed for each circuit part.

FIG. 2 shows a conventional test circuit of a scan register type installed between each circuit section to test each circuit section.

When testing a circuit, this test circuit is designed so that test data can be input into a desired circuit section, data processed by that circuit section can be output, and the output data can be verified. When not in use, the entire circuit consisting of a plurality of circuit parts is capable of normal operation.

In FIG. 2, a circuit portion 1a forming a circuit.

2a and 3a each have 0 input terminals 11.21°3
It has 1 and 0 output terminals 12, 22, and 32.

The test circuit includes a first circuit portion 1a and a second circuit portion 2.
n scan latch circuits 9 arranged between the ~
9o, and n scan latch circuits 9°1.9o arranged between the second circuit portion 2a and the third circuit portion 3a. ~9
It is composed of 2n.

This scan latch circuit 9. ~9□. has a first input terminal a, a second input terminal b1, a control lI terminal C1, and an output terminal d, and by the control signal C input to the control terminal C, -C1 the first input terminal a The signal input to the second input terminal d or the signal input to the second input terminal d is selectively output to the output terminal d.

This scan latch circuit 9. ~9□. The configuration is shown in Figure 3.

This scan latch circuit is composed of a multiplexer 7 consisting of an inverter 4 and two transmission gates 5 and 6, and a latch circuit 8. In this multiplexer 7, when the control signal C input to the control terminal C is at the "L" level, the transmission gates 1 to 5 are in the on state and the transmission gate 6 is in the off state, so that the first input terminal The signal @DI input to a is transferred to the latch circuit 8.

On the other hand, when the control signal C is at the rHJ level, the transmission gate 5 is turned off and the transmission gate 6 is turned on, so that the signal D I 2 input to the second input terminal is transferred to the latch circuit 8. .

The latch circuit 8 is a master-slave type latch circuit synchronized with the clock signal φ, and the clock signal φ is rLJ.
When the clock signal φ is at the rHJ level, the data DI from the multiplexer 7 is taken in, and when the clock signal φ is at the rHJ level, the taken in data DI is output and held. That is, when the control signal C is at the rLJ level, this scan latch circuit receives the signal D1 . When the control signal C is at the rHJ level, the signal D2 inputted to the second input terminal is taken in.

In FIG. 2, the first to nth scan latch circuits 9. The first input terminals a of ~9° are respectively connected to the output terminals 12 of the first circuit part 1a, and the output terminals d are respectively connected to the input terminals 21 of the second circuit part 2a and are respectively connected to the next scanning stage. It is connected to the second input terminals of the latch circuits 92.about.96+1.

(n+1)th stage to 2nth stage scan latch circuit 9°+
, ~9zn are respectively connected to the output terminals 22 of the second circuit portion 2a, and the output terminals d are respectively connected to the input terminals 31 of the third circuit portion 3a. In addition, the output terminals d of the (n+1)th to (2n-1)th stage scan latch circuits 9 Ill to 9□11-1 are the second input terminals of the scan latch circuits 9n and 92n of the next stage, respectively. connected to.

Also, all scan latch circuits 9. The control terminals C of -97 are commonly connected, and the control signal C is input to this control terminal C. The input terminals 11 of the first circuit part 1a are respectively connected to data input terminals I, .about.I. The output layer elements 32 of the circuit portion 3a are connected to data output terminals 01 to oo, respectively.

Next, the operation of this test circuit will be explained.

The operation of this test circuit is such that the control signal C is "1-
'' level, and a shift mode when the control signal C is at the rHJ level.

In operation mode, all scan latch circuits 9, ~9
□ is in a state to receive the signal input manually to the first input terminal 2a, so the data input in parallel from the data input terminals ■, ~In is input to the first circuit section 18, The data processed in the first circuit portion 1a is transferred to the second circuit portion 2a via scan latch circuits 9I to 9o. The data processed by this second circuit portion 2a is sent to scan latch circuits 9zn~911°-
The data transferred to the third circuit section 3a via the circuit section 321 and processed by this circuit section 321 is sent to the data output terminals 0. ~O
output from n in parallel. That is, in the operating mode, circuit portions 1a, 2a.

The entire circuit consisting of 3a sequentially performs normal data processing in synchronization with the zero check signal φ. In shift mode, all scan latch circuits 9, to 9211 are in the second
Since the signal being input to the input terminal of 9. ~9zn constitute one shift register. Therefore, the first stage scan latch circuit 9. The serial data 81 inputted to the second input terminal of is synchronized with the clock signal φ to the scan latch circuits 9□ to 9□ of the next stage. , and is output as output data SO from the output terminal d of the scan latch circuit 9211 at the final stage. By combining these two operations, it becomes possible to test each circuit section.

For example, a case will be described in which the second circuit portion 2a is tested.

First, by setting the control signal C to the rHJ level, this test circuit is put into shift mode, and test data for testing the second circuit portion 2a is transferred to the first stage scan latch circuit 9. Serial input is input from the second input terminal of the 1st to nth scan latch circuits 9. ~
I can pay it to 9o.

Next, by setting the control signal C to the rLJ level, this test circuit is put into the operation mode, and the output data of the second circuit portion 2a is transferred to the (n+1)th to 2nth stage scan latch circuits 9°, . . . 925. Then, switch to shift mode again and scan latch time 'a9. Ya,~92. The data taken in is outputted to the outside from the output terminal d of the final stage scan latch circuit 9zn by a shift operation, and this data is verified.

[Problems to be Solved by the Invention] In the conventional test circuit described above, test data for testing each circuit section is serially input and processed by each circuit section. : Since the Teddy had to be taken out serially, there were problems such as the test time becoming long and the preparation of test data becoming complicated.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a test circuit that can shorten test time and facilitate testing.

Means for Solving Problem E] The test circuit according to the present invention is composed of a plurality of parallel registers incorporated between each circuit section. Each of the parallel registers is composed of a counting scan latch circuit. Each of the scan latch circuits has a first input terminal, a second input terminal, a control terminal, and an output terminal, and the first input terminal or the second
The signal input to the input terminal of the control terminal is selectively output to the output terminal according to the signal input to the control terminal. The first input terminal of each scan latch circuit in each of the parallel registers is connected to the output terminal of the circuit section, the second input terminal is connected to the input terminal of the circuit section, and the output terminal is connected to the output terminal of the circuit section. Connected to the input terminal of the circuit part. Furthermore, the control terminals of each of the scan latch circuits are commonly connected to each parallel register.

[Operation] In the test circuit according to the present invention, the signal input to the first input terminal of the scan latch circuit is taken in and output by the signal input to the control terminal of the scan latch circuit constituting each parallel register. Alternatively, it is possible to select for each parallel register whether the signal input to the second input terminal is taken in and output.

In the parallel register whose first input terminal is selected, each scan latch circuit takes in and outputs data processed by the circuit portion connected to the input side of the parallel register.

In the parallel register whose second input terminal is selected, each scan latch circuit receives the output of each scan latch circuit of the other parallel register connected to the input side of the parallel register via the circuit section. Output with . That is, when the second input terminal is selected, data input to that parallel register does not go through the circuit portion connected to the input side of that parallel register.

[Actual 11i 1 example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows three circuit parts 1a constituting one circuit.

2a and 3a, a test circuit according to the present invention is incorporated between these circuit parts.

Each circuit portion 1a, 2a, 3a is composed of, for example, a combinational logic circuit, and has zero input terminals 11,
21.31 and zero output terminals 12°22.32.

The test circuits each include n scan latch circuits 1.
~1. ．． 2. ~2. ．． 3. It consists of three parallel registers 10.20.30 of ~3°. Each of the 1F latch circuits 11 to 1n, 2. ~2. ．． 3. ~3o
is a first input terminal a1 a second input terminal b, a control terminal C
1 and an output terminal d, and by a control signal C input to the control l terminal C, the first input terminal a
Alternatively, the signal input to the second input terminal d is selectively output to the output terminal d.

This scan latch circuit 1. ~1. ．． 2. ~2°, 3.
The configuration of 3o to 3o is exactly the same as that shown in FIG. 3, and when the control signal C is at the rLJ level, it is input to the first input terminal a in synchronization with the output signal φ. The signal is captured and output, and the control signal C is
At HJ level, the second
The signal input to input terminal a of is taken in and output.

The first parallel register 10 is arranged between the first circuit part 1a and the second circuit part 2a, and the second parallel register 20 is arranged between the second circuit part 2a and the third circuit part 3a. The third parallel register 30 is arranged on the output side of the third circuit portion 3a.

Each input terminal 11 of the first circuit portion 1a is a data input terminal I, .about.1 . It is connected to the. first parallel register 10
A first input terminal a of each scan latch circuit 1, to 1o constituting the circuit is connected to each output terminal 12 of the first circuit portion 1a, and a second input terminal a is connected to the data input terminal (2) and ~I, respectively. Each scan latch circuit 1. ~11. The output terminal d of is connected to each input terminal 21 of the second circuit portion 2a.

Further, the first input terminal a of each scan latch circuit 2I to 2o constituting the second parallel register 20 is connected to each output terminal 22 of the second circuit portion 2a,
The second input terminal S is connected to each scan latch circuit 1. ~1o are connected to output terminals d, respectively. And each scan latch circuit 2.
The ~2° output terminals d are respectively connected to respective input terminals 31 of the third circuit part 3a.

Roughly speaking, the first input terminal a of each scan latch circuit 31 to 3n constituting the third parallel register 30 is connected to each output terminal 32 of the third circuit portion 3a, and the second input terminal a is connected to each output terminal 32 of the third circuit portion 3a. The terminals are connected to each scan latch circuit 2. which constitutes the second parallel register 20. ~2. are connected to the output terminals d of the respective terminals. And each scan latch circuit 3
Output terminals d of 1 to 3 are connected to data output terminals O4 to On, respectively.

Each scan latch circuit 1. ~1. ．． 2. ~2°, 3. ~
The control terminal C of 3o is connected to each parallel register 10.20.30.
They are commonly connected, and control signals C2, Ct, and C- are applied to each independently.

Next, the operation of the test circuit shown in FIG. 1 will be explained.

The operation of this test circuit is divided into an operation mode and a test mode.

The operation mode is control signal C,,C2.

C5 is all fixed at the rLJ level. At this time, each scan latch circuit 1. ~1n, 2. ~2+
1.3. ~311 takes in the data input to the first input terminal a and outputs it to the output terminal d, so the data input terminal check ~1. The data input to 0. is sequentially processed by circuit parts 1a, 2a, 3a and then sent to data output terminals 0. ~Oo is output. That is, the circuit portion 1a,
2a.

The entire circuit consisting of 3a performs data processing sequentially in synchronization with the OFF signal φ.

In the test mode, one of the control signals C, C2, and C3 is fixed at the rLJ level.

For example, when testing the second blood path section 2a, the control signals C, , C, are set to the rHJ level and the control signal C2 is set to the rLJ level. At this time, the scan latch circuits 1 and 1n take in the data input to the second input terminal and output it to the output terminal d.
The test data input to the second circuit portion 2a is input to the second circuit portion 2a. In addition, the scan latch circuit 2. ~2o is the first
Since the data input to the input terminal a of the scan latch circuit 2. ~2° and output to output terminal d. Furthermore, scan latch circuit 3. ~3. captures the data input to the second input terminal O and outputs it to the output terminal d, so the data output to the output terminal d of the scan latch circuits 21 to 2 is transferred to the data output terminals O5 to oo. is output from.

In this way, the test data input to the data input terminals I, ~I0 is taken into the second circuit portion 2a via the first parallel register 10, and
After being processed by a, the data output terminal 0, via the second parallel register 20 and the third parallel register 30,
~O0. Therefore, in this test mode, equivalently, one stage of parallel registers is installed in the front stage of the second circuit portion 2a, and two stages of parallel registers are installed in the rear stage.

As described above, according to this test circuit, test data can be input in parallel to a desired circuit part, and data processed by that circuit part can be output in parallel, making it easy to test each circuit part. It is also possible to shorten test time.

Note that each of the circuit portions 1a, 2a, and 3a is not limited to a combinational logic circuit, but may be a pipeline-configured circuit that operates in synchronization with a clock signal.

Further, the scan latch circuit is not limited to the circuit shown in FIG. 3, but may have any configuration as long as it has a function of selecting an input signal based on a control signal.

[Effects of the Invention] As described above, according to the present invention, a parallel register is configured using a plurality of scan latch circuits that can select inputs, and a test circuit is configured using a plurality of parallel registers. This allows test data to be input in parallel to a desired circuit section, and data processed by that circuit section to be output in parallel. This simplifies the creation of test data and makes it easy to test each circuit section. , Also, testing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a test circuit according to the present invention, FIG. 2 is a circuit diagram of a conventional scan register type test circuit, and FIG. 3 is a circuit diagram showing the configuration of a scan latch circuit. . In the figure, la, 2a, and 3a are circuit parts, 11.21
．． 31 is an input terminal, 12.22.32 is an output terminal, 1.
~1n, 2. ~2r1.3. ~3° is a scan latch circuit, a is a first input terminal, b is a second input terminal, C is a control terminal, d is an output terminal, and 10, 20, and 30 are parallel registers. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa 4: Impar 7 5. s Transmission System 3 Engagement 7; Marketing Procedure 7 8 ゛rat + Reimbursement Procedures Amendment (Voluntary) Showa Year Month Day 2, Title of Invention Test Circuit 3, Representative of the person making the amendment Moriya Shiki 4, Agent 5, Detailed explanation of the invention column 6 of the specification to be amended, Contents of the amendment (1) r3a on page 3, line 15 of the specification is ``respectively'' and r3a is a combination, for example. It is composed of logic circuits, each of which is corrected to ``. (2) Change "L level" on page 5, line 9 of the specification to ""
Corrected to "H" level. (3) Change "H level" on page 5, line 11 of the specification to "
Corrected to "L" level. (4) "Connected through the circuit part" on page 11, line 13 of the specification is corrected to "connected."that's all

Claims (3)

[Claims] (1) A test circuit that is installed between a plurality of circuit parts constituting a circuit and can test each circuit part, which is a test circuit that is installed between each circuit part. each of the parallel registers is comprised of a plurality of scan latch circuits, and each of the scan latch circuits has a first input terminal, a second input terminal, a control terminal, and an output terminal. The signal input to the first input terminal or the second input terminal is selectively output to the output terminal according to the signal input to the control terminal, and each scan latch circuit in each parallel register The first input terminal is connected to the output terminal of the circuit section, the second input terminal is connected to the input terminal of the circuit section, and the output terminal of each scan latch circuit is connected to the output terminal of the other circuit section. The test circuit is connected to the input terminal, and the control terminal of each scan latch circuit is commonly connected to each parallel register. (2) The test circuit according to claim 1, wherein each of the circuit portions is constituted by a combinational logic circuit. (3) The test circuit according to claim 1, wherein each of the circuit portions is a circuit that operates in synchronization with a clock signal.