JP2556594B2 - Multiply-sum operation circuit tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A test device for testing a plurality of product-sum operation circuits formed in an LSI, which is provided for the purpose of performing a test of a product-sum operation circuit in a short time. Two types of input data are commonly applied to the sum operation circuit, and each of these product sum operation circuits performs a product operation of two input data by a multiplier inside each of them, and next to the time when the product operation is completed. Subtracting the product operation result of the product-sum operation circuit of and the product operation result of its own product-sum operation circuit with an adder, and the product operation result of one product-sum operation circuit
It is configured to output the product operation result and the subtraction result next to each product-sum operation circuit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device that tests a plurality of product-sum operation circuits formed in an LSI.

With the recent demand for higher integration and higher functionality of LSIs, mounting of LSIs having a plurality of product-sum operation circuits on one chip is required. LS with multiple product-sum operation circuits of this type
I is, for example, digital filter, FFT, image signal processing, DCT
Used for etc. Therefore, there is provided a configuration using a plurality of conventional product-sum operation circuits for one unit.

Among them, the test of the multiplier, which requires a very large number of test patterns, occupies a considerable part of the time for testing all the functions of the LSI, and it is required to shorten the test time.

[Prior Art] FIG. 5 is a block diagram showing a configuration example of a conventional product-sum operation circuit. The two input data DAin and DBin are once held in the registers 1 and 2, respectively. Multiplier 3 uses these registers
The data held in 1 and 2 is read and DAin x DBin is multiplied. The multiplication result is temporarily held in the register 4. The multiplication result held in the register 4 is externally read out as TDout, and also input to one input of the adder (ADD) 5. The adder 5 adds this input and the value held in the register 6, stores the result in the register 6 again, and outputs the output as the product-sum operation result Cout.

When a plurality of such product-sum operation circuits are formed on an LSI and an attempt is made to test these product-sum operation circuits, the result is as shown in FIG. The numbers shown in the signal lines in the figure are
The bit line of a signal line is shown. In the figure, MSU1 to MSU4 are all product-sum operation circuits 10 and show a case where four product-sum operation circuits 10 are tested. Two data DAin and DBin are commonly input to the product-sum operation circuit 10, and the product-sum operation circuit 10
The middle multiplier (see 3 in FIG. 5) multiplies these two data.

The result is output from each of the product-sum operation circuits 10 as TD1 to TD4. All of the output multiplication results are input to the multiplexer (MUX) 11. The multiplexer 1
1 includes select signals SEL1 to SEL4 from outside the LSI, and any one of MSUI to MSU4 is selected by these select signals and output as a multiplication result TDout.

The output multiplication result TDout is pulled out from the pin to the outside of the LSI. The extracted value is compared with the separately prepared expected value, and it is checked for each MSU whether or not the multiplication is correctly performed.

FIG. 7 is a timing chart showing the operation of the conventional test circuit. As DAin, as shown in (a), A1, A2,
A3 and A4 are input, and as DBin, B1, as shown in (b),
B2, B3, B4 are input. These two types of data are MSU1 to MS
As a result of being commonly input to U4, the multiplication results TD1 to TD4 output from these MSUs are output as shown in (c).
In the figure, the multiplication results are shown as AB1 to AB4, respectively. All of these multiplication results are stored in the multiplexer 11.

To the multiplexer 11, 4-bit select signals SEL1 to SEL4 as shown in (d) to (g) are input. For example, if MUS1 is selected as shown in (g),
SEL1 becomes active, MSU1's multiplication result TD1 is output from multiplexer 11, and if MSU2 is selected as shown in (f), SEL2 becomes active and MSU2's multiplication result TD
2 is output. In this case, the output of the multiplexer 11 is the strobe signal synchronized with the change of the input data.
It is compared with the expected value prepared in advance as TDout.

[Problems to be Solved by the Invention] In the conventional method, a multiplexer 11 for data selection is provided for testing, and a select signal SEL1 from the outside is provided.
~ SEL4 is designed to test separately. Generally, the test pattern of the multiplier requires about 3000 patterns in the case of 16 bits × 16 bits in order to check whether or not the multiplication operation is correct. Therefore,
In the case of the four circuits shown in FIG. 6, about 12000 patterns, which is four times that, are required. Therefore, if the number of LSI test patterns does not fall within the limit, or if the number of LSI test patterns does not fall within the limit, the test time becomes long, which hinders mass productivity.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a test apparatus for a product-sum operation circuit that can test the product-sum operation circuit in a short time.

[Means for Solving the Problems] FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 20 is a plurality of multiply-accumulate operation circuits (MSUs).
Four units from 1 to MSU4 are provided, but any number may be used. All the circuits shown in the figure are provided in the LSI. Two input data DAin and DBin are commonly input to these MSUs 20. Further, these MSUs 20 have a signal TEST indicating that they are in the test mode. That is,
The LSI enters the test mode only when the test signal TEST is active.

Each MSU is adjacent to its own MSU (MS on the left side of its own in the figure)
U) is given the multiplication result, the multiplication result given from the neighbor and the multiplication result of self are subtracted, and the result is given to each MS.
Output from U as ZF1 to ZF3. The rightmost MSU is “vacant” because there is no MSU to the right of itself. Therefore, the output of the subtraction result does not exist for MSU4. If you want to obtain the subtraction result from MSU4, you can feed back TDout which is the output of MSU1 to MSU4. The cumulative addition results are output from each MSU as CO1 to CO4.

[Operation] Each product-sum operation circuit 20 inputs the two input data DAin and DBin
Is multiplied. Then, it subtracts the multiplication result of itself from the multiplication result given from the product-sum operation circuit 20 on the right side of itself, and outputs the result as ZF1 to ZF3. Subtraction result is 0
In this case, for example, the signals ZF1 to ZF3 are designed to be "1". If these subtraction results do not become 0, it means that either the multiplier of itself or the multiplier in the product-sum operation circuit 20 on the right of itself is erroneous.

MSU1 outputs its own multiplication process as TDout, but this TDout matches the expected value, and all signals ZF1 ~
If ZF3 is "1", the operation is normal from MSU1 to MSU3. If it is normal, this time, the input data is changed and the same operation is performed. TDout for all patterns
Is the expected value and all signals ZF1 to ZF3 are “1”
Indicates that the multipliers from MSU1 to MSU3 are normal.

However, even if any one of ZF1 to ZF3 is “0” during the test.
If this happens, one of the MSUs will have a multiplier that does not perform multiplication normally, and this LSI will be discarded. As described above, according to the present invention, the product-sum operation circuit can be tested in a short time.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a timing diagram showing the operation of the principle diagram of FIG. In the figure, (a) is a data input DAin, and (b) is a data input DBin. MSU1 to MSU4 receive both of these input data, and the multiplier inside thereof multiplies the two input data and gives the result to the MSU on the left side of itself. The multiplication result of the two data that are sequentially input is output in synchronization with the strobe signal. On the other hand, the multiplication result TDout is output from MSU1 at the left end as shown in (c).

Here, in the multiplication of input data A1 and B1, MSU1 and MS
If a multiplication error occurs in one of U2, the subtraction of both multiplication results will not be 0, so ZF1 will be set to "0" as shown in the figure.
Then, the abnormality of the multiplication result is notified to the outside. In this case, if TDout is correct, it means that the multiplier of MSU2 is defective.

FIG. 3 is a configuration block diagram showing an embodiment of the product-sum calculation circuit used in the present invention. The same parts as those in FIG. 5 are designated by the same reference numerals. In the figure, 30 is an adder for adding two inputs, 31 is the multiplication result TDin of the MSU on the right side of itself.
And both inputs of sum of products held in register 6,
Select one of these inputs to add
It is a multiplexer that puts into one input of 30. Adder
The multiplication result of the multiplier 3 is input to the other input of 30.

The adder 30 and the multiplexer 31 contain a TEST signal designating a test mode. The selector 31 selects the external data TDin to be compared with the multiplication result when the TEST signal is “1”. When the TEST signal is "1" and the carry-in input Cin of the first stage of the adder 30 is entered, the adder 30 operates as a subtractor that subtracts the external input TDin from the output of the register 4.

Reference numeral 32 is a NOR gate that receives the output of the adder 30 by the number of bits and takes the NOR, and 33 is a register that holds the output of the NOR gate 32. A signal ZFi from the register 33, which indicates whether the self multiplication result and the external multiplication result match.
Is output. The operation of the circuit thus configured will be described below.

First, when testing the LSI, the TEST signal becomes "1". Therefore, at this time, the multiplexer 31 has an external input (adjacent MSU
TDin enters one input of the adder 30, and the output of the register 4 (multiplier 3) is input to the other input of the adder 30.
Multiplication result of) is entered. At this time, the adder 30 uses the register 4
It functions as a subtractor that subtracts the external input TDin from the contents of.

Therefore, if the multiplication result of its own multiplier 3 and the adjacent MSU
If the multiplication results of are equal, the output of the adder 30 becomes 0. That is, all bits become 0. As a result, the output of the NOR gate 32 becomes "1" and is held in the register 33. The register 33
The value held in is output as the comparison result signal ZFi.
In this case, ZFi = 1, so the operation of the multiplier is normal.

At this time, the self multiplication result held in the register 4 is output to the outside as TDout. This TDout becomes the external input TDin of the MSU on the left. The same test will be performed on the MSU to the left of the self.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. In the embodiment shown in the figure, the ZF signal output from each MSU is put into one OR gate 40, and the comparison result signal ZF is output from the OR gate 40. In the LSI test, it does not matter which of the built-in MSUs is defective (because the MSU is 1
If even one individual becomes defective, the LSI will of course be discarded.) It is only necessary to know that at least one MSU is defective.

Therefore, if any of the MSUs has a defect, the ZF signal becomes "1", and it notifies the outside that the LSI is defective. Moreover, with such a configuration, the number of external pins of the LSI is only TDout and ZF, which is advantageous in the LSI design.

In the above description, the case where four MSUs are provided is taken as an example, but the present invention is not limited to this, and an arbitrary number of MSUs is provided.
The same can be applied to the case where is provided.

[Effects of the Invention] As described above in detail, according to the present invention, each product-sum operation circuit (MSU) multiplies two pieces of input data DAin and DBin, and outputs its own multiplication result and its own right neighbor. By performing subtraction with the multiplication result given from the product-sum calculation circuit and outputting the result for each product-sum calculation circuit, the product-sum calculation circuit can be tested in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a timing diagram showing the operation of the principle diagram, FIG. 3 is a block diagram showing an embodiment of a product-sum operation circuit used in the present invention, and FIG. FIG. 5 is a block diagram showing another embodiment of the invention, FIG. 5 is a diagram showing a configuration example of a conventional product-sum operation circuit, FIG. 6 is a block diagram showing a test method of a conventional product-sum operation circuit, and FIG. It is a test timing diagram of a conventional example. In FIG. 1, 20 is a product-sum calculation circuit.

Claims (2)

(57) [Claims] 1. A plurality of product-sum operation circuits (20) are commonly applied with two types of input data, and these product-sum operation circuits (20) each have two input data by a multiplier. And the product operation result of the adjacent product-sum operation circuit (20) when the product operation is completed and the product operation result of its own product-sum operation circuit are subtracted by the adder, A test apparatus for a product-sum operation circuit, which is configured to output a product operation result of the sum operation circuit (20) and a product operation result next to each product-sum operation circuit (20) and a subtraction result. 2. The logical sum of the subtraction results output from each of the product-sum operation circuits (20) is output together with the product operation result of the one product-sum operation circuit. Test apparatus for the product-sum operation circuit described.