JPS63293645A - Trouble detecting device - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to shorten the test time by comparing the data obtained when an LSI to be tested is actuated by a prescribed number of steps with the expected value for execution of the detection of the trouble and the decision of the quality of the LSI. CONSTITUTION:The logical value of the result of addition set to a signal level obtained on an internal data bus DB is previously obtained as the expected value when an LSI to be tested is actuated by a prescribed number of steps. Then the actuation steps similar to those set when the expected value is obtained are actually carried out with the LSI. The data emerging on the signal lines DL1-DLn are added together by a parallel adder ADD in each actuation step. The addition result data obtained when the actuations of the prescribed number of steps are through are stored in a memory means MM. This test data is compared with said expected value for detection of the troubles of the LSI as well as the decision of the quality the LSI.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a technology for testing LSIs themselves and logic circuits, as well as a technology for detecting their failures. be.

[Prior art]

Conventionally, various methods have been provided as failure detection technology for LSI logic and wiring, depending on the nature of the LSI to be tested and the purpose of the test. Handbook J
As described in P730 to P732,
A compact test method uses pseudo-random numbers as input patterns and compresses the resulting output to determine pass/fail, and sequential circuits in the circuit can be connected in series in accordance with the test mode settings. By operating it as a shift register, it is possible to use the LSSD (Level Sensitive Scan Design) method in which all internal circuits are treated as combinational circuits.

[Problem that the invention seeks to solve]

By the way, the above-mentioned compact testing method requires a random pattern generator, a data compressor, etc., and cannot obtain a sufficient fault coverage rate with a complicated sequential circuit such as a processor. Further, in the LSSD method, a predetermined sequential circuit must be configured in advance so that it can be treated as a combinational circuit in a test mode. Therefore, when the above-mentioned technology is adopted as a test method for determining whether LSI is good or bad, both test methods are complicated, and especially in the case of the former, failure may occur for LSIs including sequential circuits such as processors. There is a problem in that the detection rate is low, and in the latter case, the circuit configuration for testing is complex, and it is useless to use it only to screen the acceptability of the LSI itself or various logic circuits. There are too many.

SUMMARY OF THE INVENTION An object of the present invention is to provide a failure detection device that can perform a test for determining whether an LSI is good or bad with a simple configuration.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, data on signal lines through which data is propagated sequentially according to a predetermined cycle is sequentially added by an adding means such as a parallel adder without overflowing, and the addition result is stored by a storage means such as a D-type latch circuit. The data is sequentially updated and stored at a timing corresponding to the data propagation cycle on the signal line.

[For production]

According to the above-mentioned means, by comparing the data obtained from the storage means with the expected value when the LSI to be tested is operated for a predetermined number of steps, it is possible to detect a failure of the LSI, that is, to judge whether it is good or bad. The present invention is intended to accomplish an LSI pass/fail screening test with a simple configuration and in a short time.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The failure detection device shown in FIG. 1 is applicable to, but is not particularly limited to, a built-in LSI such as a microprocessor, a microcomputer, or a digital signal processing processor such as a voice synthesis LSI or an image processing LSI.

In FIG. 1, DB is an internal data bus included in an LSI with a built-in failure detection circuit, and is composed of zero signal lines DLl to DLn, although this is not particularly limited. Although not particularly limited, the internal data bus Dr3 is connected to various functional blocks depending on the functions of the LSI, such as a program counter, stack pointer, address pointer, etc. in the case of a microprocessor, although not particularly shown. Various address control registers, various dedicated/general-purpose registers for operation control, instruction registers for command control, accumulators, temporary registers, logical operation units, etc. are combined. Furthermore, in the case of a digital signal processor, in addition to the above-mentioned functional blocks, a program memory, a data memory, an input/output circuit, etc. are combined depending on the function of the LSI. Therefore, when the LSI is operated, the program for that operation and the LSI are
In response to machine cycles, predetermined data such as calculation system data and control system data is propagated to the internal data bus DB.

In FIG. 1, ADD is an adding means for adding data on signal lines DLl to DLn, and is constituted by, for example, a parallel adder in which n stages of full adder circuits FAl to FAn are connected in a loop.

That is, each of the full adder circuits FA to FAn receives addition input data supplied from the negative pair of data input terminals Da and Db, and carry information (carry information) supplied from the carry input terminal Ci. Based on this, the sum and carry information of the set of input data is calculated, and the sum data is output from the data output terminal S, and the carry information corresponding to the result of the addition is output from the carry output terminal CO. They each have the same configuration so as to output. One data input terminal Da of each full adder circuit FA□ to F A n is connected to the corresponding signal line DL□ to DLn, respectively.
is coupled to the carry output terminal Co of the full adder circuit in the previous stage.
is coupled to the other data input terminal Db of the full adder circuit in the next stage, and the addition result data output terminal S of the full adder circuit in the previous stage is coupled to the carry input terminal Ci of the full adder circuit in the next stage. The carry output terminal CO of the final stage full adder circuit is feedback-connected to the data input terminal Db of the first stage full adder circuit, and the addition result data output terminal S of the final stage full adder circuit is the carry output terminal of the first stage full adder circuit. Input terminal Ci
, so that the added data is not lost on the way even if the number of connected stages of the full adder circuit is limited.

In FIG. 1, MM is a storage means that sequentially updates and stores the output of the parallel adder ADD as the addition means, and for example, the respective full adder circuits FA to FAn constituting the parallel adder ADD. It is composed of a plurality of D-type flip-flop circuits DFF□ to DFFn that latch the addition result data output from the data output terminal S of. Although not particularly limited, each of the flip-flop circuits DFF1 to DFFn includes a parallel input terminal DP and a serial input terminal Ds, and the parallel input terminal Dp is an addition result data output terminal of the corresponding full adder circuits FAl to FA n. The serial input terminal Ds is connected in series to the data output terminal Q of an adjacent flip-flop circuit. Each flip-flop circuit DFF1 to D
Alternative selection between parallel input and serial input in FFn is controlled by parallel input clock signal PCLK and serial input clock signal 5CLK. That is, each flip-flop circuit DFF to DF
Parallel input is allowed to Fn in response to a high level period of parallel input clock signal PCLK, and serial input is allowed in response to a high level period of serial input clock signal 5CLK. Here, when storing the addition result data obtained by the parallel adder circuit ADD, the serial input clock signal 5CLK is always fixed at a low level, but the parallel input clock signal PCLK at that time is set to a high level. The change timing is not particularly limited, but it corresponds to the bus cycle of the internal data bus DB, and in each bus cycle, the result of addition of data determined on the internal data bus DB is successively latched, and the latched data is transferred to the bus cycle. It is possible to update it every time. In addition, the serial input clock signal 5CLK is applied in a predetermined cycle when data stored in the series n-stage flip-flop circuits DFF to DFFn is read out to the outside of the LSI through one external terminal (not shown). controlled at a high level.

Next, the operation of the above embodiment will be explained.

To perform a pass/fail judgment test on an LSI incorporating the failure detection device of this embodiment, first, when the LSI to be tested is operated for a predetermined number of steps, the logic of the addition result to the signal level sequentially obtained on the internal data bus DB is Obtain the value in advance as the expected value. At that time, the addition logic is parallel adder A
It is assumed that the addition logic of DD is followed. Then, the LSI actually executes the same operation steps as when calculating the expected value. Then, in each operation step, the data actually appearing on each signal line DL to DLn is transferred to the parallel adder A.
The addition results are sequentially added by DD, and the addition results are input in parallel to the flip-flop circuits DFF to DFFn every high-level period of the parallel input clock signal PCLK according to the bus cycle corresponding to each operation step. DFF□ to DFFn
The addition result data obtained sequentially according to the bus cycle is sequentially updated and held.

At the same time as a predetermined operation step is completed, the parallel input clock signal PCLK is fixed to a low level, and the addition result data at the time when the predetermined number of steps are completed is stored in each flip-flop D constituting the storage means MM.
Saved in FF to DFFn. In this state, when the serial input clock signal 5CLK is set to high level in a predetermined cycle, the flip-flops DFF to DF
The test result data stored in Fn is 1 (not shown).
The data is read out as serial data via external terminals. By comparing the test result data read externally with the above expected value, the LS
Failure detection of I, that is, pass/fail judgment is performed.

According to the above embodiment, the following effects can be obtained.

(1) The data on the signal lines DL to DLn, through which data is propagated sequentially according to a predetermined bus cycle, is sequentially added without overflowing in the parallel adder ADD, and the addition result is sent to the D-type flip-flop circuit DF'. By inputting data in parallel to F, through DFFn, and sequentially updating and storing them at timings corresponding to the above bus cycles, the information obtained from the above-mentioned flip-flop circuits DFF1 through DFFn is input when the LSI under test is operated for a predetermined number of steps. By comparing the final addition result data with the expected value, it is possible to judge whether the LSI is good or bad. Therefore, the data collation for the good or bad judgment can be performed in a short time, and the efficiency of selecting good or bad LSIs can be improved. can be improved.

It should be noted that even if a failure occurs in the LSI, there is a possibility that the collected addition result data obtained in the storage means MM coincidentally coincides with the normal expected value depending on the nature of the failure. As the number of bits of data sampled increases exponentially, this is rarely a problem, and to ensure fault detection,
The failure detection test may be performed multiple times using different operation steps.

(2) Since the circuit configuration required to acquire test data for determining the quality of the LSI is only the addition means ADD and the storage means MM, the circuit configuration for this purpose can be extremely simplified.

(3) Multiple D-type flip-flop circuits DFF1 to D that can sequentially shift and output latch data serially
When the storage means MM is configured by FFn, the number of external terminals for outputting the addition result data to be compared with the expected value to the outside is only one, and in particular, the internal data bus D
In an LSI such as a dedicated processor in which B is not open to the outside of the LSI, the number of external output terminals for addition result data can be minimized.

Although the invention made by the present inventor has been specifically described above based on Examples, the present invention is not limited to the above-mentioned Examples, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, a case has been described in which the latch data of the storage means MM is serially outputted to the outside via a dedicated external terminal, but the invention is not limited to this.
In an LSI whose internal data bus is open to the outside, the addition result data may be output in parallel to the outside via the internal data bus in response to the test mode, or the parallel An output terminal may be specially provided, and the adder circuit is not limited to a full adder circuit, but may be changed to a half adder circuit.

In that case, it is sufficient to connect a plurality of half adder circuits in a loop while ignoring the carry input terminal of the full adder circuit shown in FIG. It is not limited to the configuration used, and it is possible to change to an appropriate storage element that can update and sequentially store input data. Furthermore, the timing of inputting data to the storage means is not limited to a configuration that corresponds one-to-one to the bus cycle of the data bus as in the above embodiment, but may be set as appropriate in relation to the required failure detection rate. Can be done.

In the above explanation, the invention made by the present inventor is mainly applied by being built into an LSI such as a microprocessor, a microcomputer, or a digital signal processing processor such as a voice synthesis LSI or an image processing LSI, which is the field of application in which the invention is based. I explained the case where
The application is not limited to this, but can also be applied to failure detection devices that are connected to external terminals of LSIs that are internally connected to various signal lines such as data buses, address buses, and control signal lines. can.

The present invention can be applied to at least conditions for determining the quality of an LSI itself or a predetermined logic circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, data on signal lines through which data is propagated sequentially according to a predetermined cycle is sequentially added by an adding means such as a parallel adder without overflowing, and the addition result is stored by a storage means such as a D-type latch circuit. By sequentially updating and storing the data at a timing corresponding to the propagation cycle of data to the signal line, and comparing the data finally obtained from the storage means with the expected value when the LSI under test is operated for a predetermined number of steps, By being able to detect failures in the LSI, that is, to determine whether it is pass or fail, it is possible to simplify the circuit configuration for pass/fail screening tests of LSIs.
Shortening of test time can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a failure detection device according to the present invention. DB...internal data bus, DLl to DLn...signal line, ADD...parallel adder, FA engineering to FA
n...Full adder circuit, MM...Storage means, DFF to DFFn...D type flip-flop circuit, PCLK
...Clock signal for parallel output, 5CLK...Clock signal for serial output.

Claims (1)

[Scope of Claims] 1. The invention comprises an adding means for adding data on signal lines through which data is sequentially propagated according to a predetermined cycle, and a storage means for sequentially updating and storing the output of the adding means. Characteristic failure detection device. 2. The above-mentioned adding means is a parallel adder that inputs data in parallel from multiple signal lines and adds them. 2. A failure detection device according to claim 1, characterized in that the signal is fed back to an adder circuit. 3. The storage means is composed of a plurality of D-type flip-flop circuits that latch the added data outputted from the respective adder circuits constituting the parallel adder in response to the propagation cycle of data to the signal line. 3. The failure detection device according to claim 2, wherein the failure detection device is: 4. The failure detection device according to claim 3, wherein the plurality of D-type flip-flop circuits are capable of serially shifting and outputting latch data.