JP2616125B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit having a data bus and a test circuit for the semiconductor integrated circuit.

[Conventional technology]

FIG. 3 is a configuration diagram showing an LSI test system to which a conventional test circuit is applied. In the figure, 1a, 1b, 1c are functional blocks, 2 is a bus line composed of a plurality of bits, 3
Is a conventional test circuit, 10 is a clock generator, 11 is a control signal generator, A is a scan data input terminal, B is a scan data output terminal, C is a test external data output terminal comprising a plurality of bits, and D is a plurality of bits. E is an external data input terminal, E is a test control terminal consisting of a plurality of bits, F
Is a signal line for transmitting the test mode signal TM, G is a signal line for transmitting the test source instruction signal SS composed of a plurality of bits, H is a signal line for transmitting the test destination instruction signal DS composed of a plurality of bits, and I is a signal line. A signal line for receiving and transmitting test clock signals φ _{T1 to} φ _T5 . Also,
φ _M is a master clock to configure the system clock, φ
_S is a slave clock constituting the system clock.

FIG. 4 is a schematic configuration diagram of a functional block.
In the figure, 4a and 4b are processing circuits, 5 is a master-slave flip-flop, 6a to 6e are data latches, 7 is a tri-state output circuit, 8a to 8f are OR circuits, and 9a and 9b are AND circuits.

 Next, the operation will be described.

Normally, in the non-test mode, the test clock signal φ _T1
~φ _T5 becomes "L" level, the test mode signal TM is also "L" level. In this state, each functional block operates in synchronization with the system clock phi _M and phi _S. Also,
Each functional block is controlled by control signals c1 and c2, a bus destination instruction signal DS, and a bus source instruction signal SS. The control signals are not limited to c1 and c2, but are given as many as necessary for each functional block. Here, c1 and c2 are used for simple explanation.

In the non-test mode, first, in synchronization with the system clock φ _M, in accordance with the destination indication signal DS, data latch 6d fetches the data DI on the bus line 2. At the same time, data latches 6a and 6c take in control signals c1 and c2, respectively. Data captured by data latch 6d
DI, after being processed in the processing circuit 4a in accordance with the output signal of the data latch 6a and 6c, taken into the data latch 6e in synchronism with the system clock phi _S. Data fetched into the data latch 6e is processed by processing circuit 4b, in accordance with the source instruction signal SS, output to the bus line 2 in synchronism with the system clock phi _out. Data processing is performed by repeating the above operation in each functional block one after another.

In the test mode, the clock generator 10 receives the test mode signal TM, and sets all the system clocks φ _M , φ _S , φ _out to “L” level. At this time, the function blocks 1a ~
Externally test any one of 1c. First, the test mode signal TM is set to “H” level by the signal CNT of the test control terminal E, and the function of the master-slave flip-flop 5 is switched to the scan shift register. Data latch any data SI from scan data input terminal
Set to 6a, 6b. At this time, test clock signals φ _T1 and φ _T4 are used. Then, using the test clock signal phi _T2, incorporating the control signal c2 to the data latch 6c. Further, data is input from the test external data input terminal D to the first
Output terminal is output as data DO via the (not shown) (see FIG. 3) to the bus line 2, by using the test clock signal phi _T3 and destination instruction cardiac signal DS, Fig. 4 to the data latch 6d of Set the data DI shown in. The data processed by the processing circuit 4a is latched using φ _T4.
6e and further processed by the processing circuit 4b. The output of the processing circuit 4b is output as data DO onto the bus line 2 by using the source instruction signal SS and the test clock signal phi _T5. The test circuit 3 outputs data on the bus line 2 to the external test output terminal C.

As described above, the functional blocks 1a to 1c in FIG. 3 are individually tested.

[Problems to be solved by the invention]

Since the conventional LSI test system is configured as described above, the system clocks φ _M , φ _M
S and φ _out are stopped, and test clock signals φ _{T1 to} φ
There was a problem that _T5 had to be given and the number of external pins increased.

The present invention has been made in view of such a point,
An object of the present invention is to provide a semiconductor integrated circuit capable of testing without inputting a test clock signal from outside.

[Means for solving the problem]

In order to achieve such an object, the present invention has a multi-bit bus line, means for taking in data on the bus line, processing the data, outputting the processed data to the bus line again, and a master-slave flip-flop. In a semiconductor integrated circuit having a functional block and a test circuit, the test circuit includes a test control terminal for receiving a multi-bit test control signal from the outside, and a function of a master-slave flip-flop according to the test control signal. A test mode signal terminal for outputting a test mode signal for switching from the data latch to the scan shift register;
Types of clock stop signals, that is, a first clock stop signal for stopping a clock of a master side latch of a master-slave type flip-flop and a second clock stop signal for stopping a clock of a data latch for taking in data on a bus line And outputting a third clock stop signal for stopping the clock of the data latch that fetches data in synchronization with the master clock among the data latches other than the master-slave flip-flop and the data latch that fetches data on the bus line. First, second, and third clock stop signal terminals, a first output terminal for outputting externally applied data to a bus line according to a test control signal, Output to the second
Output terminal.

[Action]

The three types of clock stop signals in the semiconductor integrated circuit according to the present invention are controlled by a test control signal from an external pin, and are provided with a master-slave flip-flop, a data latch for taking in data on a bus line, a master-slave flip-flop and a bus-line The data latches that take in data in synchronization with the master clock among the data latches other than the data latch that takes in the data are stopped.

〔Example〕

One embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram showing an LSI test system to which an embodiment of a semiconductor integrated circuit according to the present invention is applied. In FIG. 1, 1a, 1b and 1c are functional blocks, 2 is a bus line composed of a plurality of bits, 3 is a test circuit, 10 is a clock generator, 11 is a control signal generator, A is a scan data input terminal, and B is A scan data output terminal; C, a test external data output terminal as a second output terminal composed of a plurality of bits; D, an external data input terminal composed of a plurality of bits;
Is a test control terminal composed of a plurality of bits, F is a signal line for transmitting a test mode signal TM output from a test mode signal terminal (not shown), and G is a test source indication signal SS composed of a plurality of bits. A signal line, H is a signal line for transmitting a test destination instruction signal DS composed of a plurality of bits, and J is a signal for transmitting a first test clock stop signal SSTOP output from a first clock stop signal terminal (not shown). Line, L is a signal line for transmitting a second clock stop signal DSTOP output from a second clock stop signal terminal (not shown), and K is a third signal line output from a third clock stop signal terminal (not shown).
Signal line for transmitting the clock stop signal CSTOP. Also, phi _M master clock which constitutes the system clock, phi _S slave clock which constitutes the system clock, the phi _out a timing clock which constitutes the system clock used to output data to the bus line 2.

FIG. 2 is a schematic configuration diagram of a functional block.
In the figure, 4a and 4b are processing circuits, 5 is a master-slave flip-flop, 6a to 6e are data latches, 7 is a tri-state output circuit, and 9a to 9d are AND circuits.

 Next, the operation will be described.

Normally, in the non-test mode, the first to third clock stop signals SSTOP, DSTOP, and CSTOP are at the “H” level, and operate in synchronization with the system clocks φ _M and φ _S just as in the conventional case. Perform data processing.

In the test mode, the first to third clock stop signals SSTOP, DSTOP, and CSTOP are controlled by the signal CNT input to the test control terminal E so that they are all at “L” level. At this time, the system clocks φ _M , φ _S , φ _out continue to be output at any timing. In this state, in the data latches 6a to 6e of FIG. 2, all clocks are stopped, and no new data is taken. To operate the master-slave flip-flop 5 including the data latches 6a and 6b as a scan shift register from this state, the test mode signal TM is set to "H" level, and the first clock stop signal SSTOP is set to "H" level. , Arbitrary data SI is set from the scan data input terminal A.
Next, the test mode signal TM is set to "L" level, the first clock stop signal SSTOP is set to "L" level, the third clock stop signal CSTOP is set to "H" level, and the control signal c2
Is set in the data latch 6c.

Data can be set in the data latch 6d by setting the bus destination instruction signal DS and the second clock stop signal DSTOP to "H" level. Data set in the data latch 6d is processed by processing circuit 4a, it is set in the data latch 6e in synchronism with the slave clock phi _S system. The data set in the data latch 6e is further processed by the processing circuit 4b and becomes an input to the tri-state output circuit 7.

Function output block 1a~1c to retrieve to the outside, since it is outputted onto the bus line 2 in synchronism with the system clock phi _out by a source instruction signal SS bus "H" level, the bus line 2 Test data 3 above
Through the test data output terminal C to the outside.

As described above, one of the functional blocks 1a to 1c
One can be tested externally.

In the above embodiment, the test external data input terminal, the test external data output terminal, and the test control terminal are provided, but terminals not used in the test mode may be used. Further, a part of data to be processed may be provided from a master-slave type flip-flop.

Further, the signal line G of the bus source instruction signal SS and the signal line H of the bus destination instruction signal DS do not need to be provided exclusively, and a control circuit or control line used during normal operation may be used.

〔The invention's effect〕

As described above, according to the present invention, since the system clock is used at the time of the test, it is not necessary to provide a terminal for a test clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a test system to which an embodiment of a semiconductor integrated circuit according to the present invention is applied, and FIG. 2 is a block diagram showing functional blocks constituting the system of FIG. FIG. 3 is a block diagram showing a test system to which a conventional LSI test circuit is applied, and FIG. 4 is a block diagram showing functional blocks constituting the system of FIG. 1a, 1b, 1c ... Function block, 2 ... Bus line, 3 ...
Test circuit, 4a, 4b Processing circuit, 5 Master-slave flip-flop, 6a to 6e Data latch, 7
... tri-state output circuit, 9a to 9d ... AND circuit, 10 ...
... Clock generator, 11 ... Control signal generator, A ... Scan data input terminal, B ... Scan data output terminal
C: External data output terminal for test, D: External data input terminal, E: Control terminal for test, F, G, H, J, K, L ...
Signal line.

Claims (1)

(57) [Claims] 1. A test circuit comprising: a bus line of a plurality of bits; means for fetching data on the bus line, processing the data, and outputting the processed data to the bus line again; and a master-slave flip-flop; A test control terminal for receiving a test control signal of a plurality of bits from outside, and a function of a master-slave flip-flop from a normal data latch to a scan shift register according to the test control signal. A test mode signal terminal for outputting a test mode signal for switching to a first mode, a first clock stop signal for stopping a clock of a master-side latch of the master-slave flip-flop according to the test control signal, Data to be imported A second clock stop signal for stopping a clock of the latch, and a clock of a data latch for capturing data in synchronization with a master clock among data latches other than the master-slave flip-flop and a data latch for capturing data on a bus line A first, a second, and a third clock stop signal terminal for outputting a third clock stop signal for stopping the clock signal; and a second for outputting externally applied data onto the bus line according to the test control signal. And a second output terminal for outputting data on the bus line to the outside in accordance with the test control signal.