JPH05128898A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To simply operate a test without increasing the number of an external terminals. CONSTITUTION:When a test mode is selected by a signal inputted to a terminal 22, the terminal 21 side is selected by a selector 200 and simultaneously the terminals DO1-DOn-1 sides are selected by the selectors 201-20n. When a test signal TSi is inputted to the terminal 21, the TSi is sent to the terminal DI0 of a memory 10 through the selector 200, and the TSi is inputted to the memory 10 by a shift clock inputted to the terminal SI. Then, the TSi is transferred through the memory 10 and outputted from the terminal DO0 and inputted to be fed back to the selector 201. When the next shift clock is inputted to the terminal SI, the output data of the selector 201 is inputted into the memory 10 and outputted from the terminal DO1, and is inputted to be fed back to the selector 202 and inputted into the memory 10. By repeating such operation, the test signal TS0 is outputted from the terminal DOn of the memory 10 to the terminal 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to first-in first-out (Fir)
st In First Out (hereinafter referred to as FIFO)
Type memory and last in first out
The present invention relates to a semiconductor memory device that writes and reads data in the order of a memory such as t Out, hereinafter referred to as LIFO) type memory, and more particularly to a semiconductor memory device having a test mode function.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of the configuration of a FIFO memory which is one of conventional semiconductor memory devices. The FIFO memory 10 has data input terminals DI _{0 to} DI _n for inputting (n + 1) -bit input data,
Data output terminals DO _{0 to} DO _n for outputting (n + 1) -bit output data, a shift-in clock terminal SI for inputting input data, a shift-out clock shift for outputting output data Out-clock terminal SO, input ready terminal IR that outputs a signal indicating whether input is possible, output ready terminal OR that outputs a signal indicating whether output is possible, and reverse-phase master reset terminal for resetting all in memory MR _N (where N represents the reverse phase).

Further, a plurality of cascaded data latch circuits 11-0, each of which is composed of a latch circuit of each (n + 1) bit, is provided.
11-m are provided, and the data latch circuit 1 at the first stage thereof is provided.
Data input terminal DI to the input side of the 1-0 ₀ -DI _n are connected, the data output terminal DO ₀ to DO _n to the output side of the data latch circuit 11-m of the final stage is connected. Further, an input control circuit 12 that controls the input of data to the data latch circuits 11-0 to 11-m of a plurality of stages.
And a data output control circuit 13 that controls the output of data, and controls the transfer of data between the data latch circuits 11-1 to 11-m between the input control circuit 12 and the output control circuit 13. A plurality of stages of register control circuits 14-1 to 14-m are connected in series by a control signal CS for controlling. Reverse phase master reset terminal MR _N is input control circuit 12 are connected to the output control circuit 13, and a register control circuit 14-1 to 14-m.

An input ready terminal IR and a shift-in clock terminal SI are connected to the input control circuit 12, and a latch signal L is sent to a data latch circuit 11-0 by a shift clock from the shift-in clock terminal SI.
Give H and register control circuit 1 of the first stage
It has a function of supplying the control signal CS to 4-1. A shift out clock terminal SO and an output ready terminal OR are connected to the output control circuit 13,
It has a function of giving a control signal CS to the register control circuit 14-m based on the shift clock input from the shift-out clock terminal SO to control the output of data. Multi-stage register control circuit 1
4-1 to 14-m are cascade-connected to each other based on the control signal CS, and give a latch signal LH to each of the data latch circuits 11-1 to 11-m to supply the data latch circuits 11 to 11-m.
It is a circuit that controls the transfer of -1 to 11-m.

In this FIFO type memory 10, the input control circuit 12 operates in synchronization with the shift clock input from the shift-in clock terminal SI, and the data latch circuit 11-0 in the first stage operates the data input terminal DI _0.
To enter the input data from ~DI _n. The register control circuits 14-1 to 14-m are synchronized with the shift clock input from the shift-in clock terminal SI.
Outputs a latch signal LH, and the input data input to the first stage data latch circuit 11-0 is sequentially transferred to the right stage toward the last stage data latch circuits 14-1 to 14-m. Go Each time a shift clock is input from the shift-out clock terminal SO, the input data is sequentially input from the data latch circuit 11-m at the final stage to the data output terminals DO _{0 to} D _0.
Are sequentially output to O _n.

Conventionally, when performing a function test of the FIFO memory 10 of this type, for example, the data input terminals DI _{0 to} D _0.
The test signals of “0” and “1” are input to I _n , it is determined whether the signals output from the data output terminals DO _{0 to} D O _n match the input test signals, and the FIFO memory 10 good or defective products were tested.

[0007]

However, the conventional semiconductor memory device has the following problems. For example, a conventional FIFO memory 10, when incorporated as part of an integrated circuit, the test it, data input terminal DI ₀ -DI _n and a data output terminal DO ₀ to DO _n
All of the above are drawn out to the outside, and the function test of the memory is performed using the drawn out external terminals, so that there is a problem that the number of external terminals increases due to the addition of the test function.

In order to solve the increase in the number of external terminals, it is possible to perform a test operation according to a test program including the peripheral circuit of the FIFO type memory 10 built in the integrated circuit. It is relatively easy to perform a test including the peripheral circuit of the FIFO type memory 10. However, it is difficult to create a test program that obtains the test result of only the FIFO memory 10 from the test result. Even if a test program that can test only the FIFO memory 10 is created, it is necessary to create a program that takes into consideration the relationship with the peripheral circuits, which complicates the test program itself and complicates the test operation. The problem arises that Therefore, it is difficult to test the semiconductor memory device relatively easily and in a short time without increasing the number of external terminals so much.

The present invention solves the problem of the conventional technique that it is difficult to perform a test operation relatively easily without increasing the number of external terminals so much that the semiconductor memory with a test mode function is solved. A device is provided.

[0010]

In order to solve the above-mentioned problems, a first invention has i (where i is a positive integer) data input terminals and i data output terminals, and shifts In a semiconductor memory device for writing i-bit input data to the data input terminal and reading i-bit output data from the data output terminal in order by a clock, the (i-1) -bit input data and the (I
-1) Bit output data is selected by a selection signal and input to the (i-1) data input terminals, respectively, and (i-1) first selectors, and the rest. There is provided one second selector which selects one of 1-bit input data and a test signal by the selection signal and inputs the selected one to the remaining one data input terminal. Furthermore, a test signal input terminal for externally inputting the test signal, a test signal output terminal for externally outputting the remaining 1-bit output data, and a test mode selection terminal for externally inputting the selection signal are provided. ing.

According to a second aspect of the present invention, in place of the test signal input terminal of the first aspect, a test signal generating circuit for generating the test signal based on the shift clock and inputting the test signal to the second selector is provided. There is.

[0012]

According to the first aspect of the invention, since the semiconductor memory device with a test function is configured as described above, if the test mode is selected by the selection signal, the input sides of the first and second selectors are switched. When a test signal is input to the test signal input terminal from the outside, the input signal is input to the FIFO type memory via the second selector by the shift clock and is output from the data output terminal of the FIFO type memory to output the first signal. Is fed back to the selector side of, and is fed to the FIFO type memory with a shift clock.
By repeating such an operation, a test signal is output from the data output terminal of the FIFO memory, and the test signal is output to the outside from the test signal output terminal. Therefore, by comparing the input test signal with the output test signal, the quality of the FIFO memory can be determined.

According to the second invention, when the test mode is selected by the selection signal, the second selector selects the output of the test signal generating circuit and the first selector operates to select the input data. To do. Then, when the shift clock is input to the test signal generation circuit and the FIFO memory, the test signal is output from the test signal generation circuit, and the test signal is output to the FIFO through the second selector.
The data is input to the O-type memory, output from the data output terminal of the FIFO-type memory, and fed back to the first selector side.

Next, when the shift clock is input to the test signal generation circuit and the FIFO type memory, the test signal generated from the test signal generation circuit is input to the FIFO type memory via the second selector and at the same time, The output of the data output terminal input to the selector 1 is input and output from the data output terminal of the FIFO type memory. By repeating such operations, a test signal is output from the data output terminal of the FIFO memory, and the test signal is output to the outside via the test signal output terminal. Therefore, by comparing the test signal output from the test signal generation circuit with the test signal output from the test signal output terminal, a functional test of the FIFO memory can be performed. Therefore, the above problem can be solved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram showing the configuration of a FIFO memory with a test mode function, which is one of the semiconductor memory devices according to the first embodiment of the present invention. Elements that are common to the elements of 1 are assigned the same reference numerals. This FIFO type memory with a test mode function is provided in, for example, an integrated circuit, and has the same (n + 1) -bit FI as in FIG.
Comprising a FO memory 10, the (n + 1) to the data input terminal DI ₀ -DI _n bits having two inputs and one output which is switched output by the selection signal SL is performed (n + 1) number of selectors 20 ₀ to 20 _n Each output side of is connected respectively. Furthermore, a test signal T of "0" or "1" is externally applied.
A test signal input terminal 21 for inputting S _i , a test mode selection terminal 22 for externally inputting a selection signal SL for selector switching, and a test output from the n-th bit data output terminal DO _n of the FIFO memory 10. A test signal output terminal 23 for outputting the signal TS _o to the outside is provided outside the integrated circuit, respectively.

0th bit selector (second selector)
20 ₀ selects either the 0th bit input data D ₀ supplied from the internal circuit in the integrated circuit or the test signal TS _i input from the test signal input terminal 21 by the selection signal SL. , A circuit for inputting to the 0th bit data input terminal DI ₀ of the FIFO memory 10.
Of the selectors (first selectors) 20 _{1 to} 20 _n of the 1st bit to the _nth bit, the selector 20 of the 1st bit
₁ selects one of the 1-bit input data D ₁ supplied from the internal circuit and the 0-bit output data of the data output terminal DO ₀ by the selection signal SL,
This is a circuit applied to the first bit data input terminal DI ₁ .

Similarly, the n- _th selector is connected to the n-th bit, and the n- _th selector 20 _n is supplied from the internal circuit.
Either one of the input data D _n of the bit and the output data of the data output terminal DO _n-1 of the (n-1) th bit is selected by the selection signal SL, and the data input terminal DI _n of the nth bit is selected. Entered in. The n-th bit data output terminal DO _n is connected to the test signal output terminal 23 provided outside.

Next, each operation of the normal operation mode (a) and the test operation mode (b) of FIG. 1 will be described.

(A) Normal operation mode When the normal operation mode is selected by the selection signal SL supplied to the test mode selection terminal 20, each selector 20 ₀
˜20 _n is the input data D _{0 to} D supplied from the internal circuit
Select _n to select the data input terminal D of the FIFO memory 10
I supplied respectively to _{0 ~DI n.} Therefore, if a shift clock is input from the shift-in clock terminal SI,
Input data D ₀ to D _n is the data input terminal DI ₀ -DI _n
After being input to, will be transferred to the FIFO memory 10 to the sequential data output terminal DO ₀ to DO _n direction, performs a normal FIFO operation in the same manner as conventional FIG.

(B) Test operation mode When the FIFO memory 10 is set to be empty, the shift-out clock terminal SO is set to "0", and the test operation mode is selected by the selection signal SL, the 0th bit is set. The selector 20 _o selects the test signal input terminal 21 side, and the selectors 20 _{1 to} 20 _{n of} the 1st bit to the nth bit are the data output signal DO _n side of the 0th bit to the (n-1) th bit. Select each.
Supplying test signal TS _i to the test signal input terminal 21 is sent via the selector 20 _o 0-th bit to 0-th bit of the data input terminal DI _o.

When the shift clock is input to the shift-in clock terminal SI, the test signal TS _i is input to the 0th bit data input terminal DI _o , and the FIFO type memory 10
The data is transferred to the 0th bit data output terminal DO _o . Since the FIFO memory 10 is empty, when the test signal TS _i is transferred to the 0th bit data output terminal DO _o , it is output from the data output terminal DO _n to 1
It is sent to the selector 20 ₁ of the bit position.

Next, when a shift clock is input to the shift-out clock terminal SO and the shift-in clock terminal SI, the FIFO memory 10 is emptied by the shift-out clock terminal SO, and the data of the selector 20 ₁ is stored in the shift-in clock terminal SI. The data is transferred from the data input terminal DI ₁ to DO ₁ and sent to the second bit selector 20 ₂ . At the same time, the data of the test signal TS _i is transferred from the data input terminals DI ₀ to DO ₀ , and the selector 2
Sent to 0 ₁ .

When such an operation is repeatedly executed,
By inputting the (n + 1) th shift clock to the shift-in clock terminal SI and inputting the nth shift clock to the shift-out clock terminal SO, the test signal TS _o is output from the _n-th data output terminal DO _n to the outside. It is output to the test signal output terminal 23. Therefore, if the match / mismatch between the test signal TS _o and the input test signal TS _i is detected, the quality of the FIFO memory 10 can be determined.

FIG. 3 shows a timing chart in the case of 4 bits. As described above, in the first embodiment, by providing the test signal input terminal 21, the test mode selection terminal 22 and the test signal output terminal 23 regardless of the number of bits of the FIFO memory 10, A functional test of the FIFO memory 10 can be performed with only three terminals. Therefore, the test operation can be performed easily and accurately without increasing the number of external terminals as in the conventional case.

Second Embodiment FIG. 4 shows an F with test function showing a second embodiment of the present invention.
FIG. 2 is a block diagram of a configuration of an IFO type memory, and elements common to those in FIG. 1 are designated by common reference numerals. In this FIFO memory with a test function, the test signal input terminal 21 of FIG. 1 is omitted, and instead the test signal generation circuit 3 is used.
0 is set. The test signal generation circuit 30 is, for example, a T-type flip-flop (hereinafter referred to as T-FF) having a clock terminal CLK, a reset terminal R, and an output terminal Q.
The clock terminal CLK is connected to the shift-in clock terminal SI of the FIFO type memory 10, the reset terminal R is connected to the test mode selection terminal 22, and the output terminal Q for outputting the test signal TS _i is 0 bit. It is connected to the input side of the eye of the selector 20 _0. next,
Each operation of (a) normal operation mode and (b) test operation mode of FIG. 3 will be described.

(A) Normal operation mode When the normal operation mode is selected by the selection signal SL input to the test mode selection terminal 22, the selectors 20 ₀ to
Since 20 _n selects the input data D _{0 to} D _n side and the test signal generation circuit 30 is reset, the normal FIFO operation is performed as in FIG.

(B) Test operation mode The test operation mode is selected by the selection signal SL input to the test mode selection terminal 22, the FIFO memory 10 is set to empty, and the shift-out clock terminal SO
Is set to, for example, “0”, the reset state of the test signal generation circuit 30 is released by the selection signal SL. When the shift clock is input to the clock terminal CLK of the test signal generation circuit 30 and the shift-in clock terminal SI of the FIFO memory 10, the test signal TS _i is output from the output terminal Q of the test signal generation circuit 30, and the test signal TS is output. _i is input to the 0th bit data input terminal DI ₀ through the 0th bit selector 20 ₀ . And F
The data is transferred in the IFO type memory 10 and output from the 0th bit data output terminal DO ₀ . This output data is sent to the first bit selector 20 ₁ as in FIG. 1, and is sent to the first bit data input terminal DI ₁ of the FIFO memory 10 via the selector 20 ₁ . Further, the output of the output terminal Q of the test signal generation circuit 30 is inverted due to the change of the shift clock input to the shift-in clock terminal SI.

Next, the shift clock is input to the shift-out clock terminal SO of the FIFO memory 10 and the shift clock is input to the clock terminal CL of the test signal generating circuit 30.
When input to the shift-in clock terminal SI of the K and FIFO type memory 10, the 0th bit data output terminal DO ₀
The first data output from the first bit is input from the first bit data input terminal DI _{1 and} is output from the first bit data output terminal DO ₁ , and at the same time, the inverted signal of the first input test signal TS _i is 0th bit data input terminal D from output terminal Q through 0th bit selector 20 ₀
Input from I ₀ , 0th bit data output terminal DO ₀
Is output from.

When the same operation is repeatedly executed, (n +
1) Shift clock is shifted in clock terminal SI
To the shift-out clock terminal SO, and the n-th bit data output terminal DO _n outputs the test signal TS _o and the test signal output terminal 23 outputs the test signal TS _o to the outside. ..

FIG. 5 shows a timing chart in the case of 4 bits. As described above, in the second embodiment, no matter how many bits the FIFO memory 10 has, the function test is performed only by the externally provided test mode selection terminal 22 and test signal output terminal 23. Is possible. Therefore, the test operation can be easily performed without increasing the number of external terminals as compared with the conventional case. Moreover, since the test signal generation circuit 30 is provided in place of the test signal input terminal 21 of the first embodiment, the number of external terminals can be reduced by one and the test signal generation circuit 30 can generate the test signal TS _i . Since it can be generated, it is not necessary to input the test signal TS _i from the outside.

The present invention is not limited to the above embodiment, and various modifications can be made. Examples of such modifications include the following. (I) In FIGS. 1 and 3, the output of the 0th bit data output terminal DO ₀ is changed to the 1st bit data input terminal D
Input to I _1, as inputs the output of the first bit of the data output terminal DO ₁ to the data input terminal DI ₂ of the second bit, ₀ sequential data output terminal DO from the lower bit to a higher bit to DO _{n The} connection structure is such that the output of _-1 is fed back to the input side of the FIFO memory, but the order of the connection is not particularly limited and can be changed to any connection structure.

(Ii) Test circuit generation circuit 30 of FIG.
Consists of T-FF, D-type FF, JK-type F
Even if it is configured by various circuits such as F, a latch circuit, and a gate combination circuit, the same operation and effect as those of the above embodiment can be obtained.

(Iii) FIFO memory 1 of the above embodiment
Although 0 has been described as an example of the conventional circuit shown in FIG. 2, the FIFO memory 10 can be modified into various circuit configurations. Further, in the above embodiment, the F with test function is used.
Although the IFO type memory 10 has been described, by adding the test function as in the above embodiment to another semiconductor memory device such as a LIFO type memory or the like, it is possible to obtain substantially the same operation and effect as in the above embodiment.

[0034]

As described in detail above, according to the first invention, the first and second selectors, the test signal input terminal, the test signal output terminal, and the test mode selection terminal are provided. Regardless of the number of bits of the semiconductor memory device, a functional test can be performed only with the externally provided test signal input terminal, test signal output terminal, and test mode selection terminal. Therefore, the test operation can be performed easily and accurately without increasing the number of external terminals as in the conventional case.

According to the second invention, since the test signal generating circuit is provided in place of the test signal input terminal of the first invention, substantially the same effect as that of the first invention can be obtained. Moreover,
Since the test signal input terminal is omitted, the number of external terminals can be reduced, and since the test signal is generated by the test signal generation circuit, it is not necessary to input the test signal from the outside and the test can be performed more easily.

[Brief description of drawings]

FIG. 1 is an F with a test function showing a first embodiment of the present invention.
It is a block diagram of a configuration of an IFO type memory.

FIG. 2 is a configuration block diagram of a conventional FIFO type memory.

FIG. 3 is a timing chart in the case of 4 bits in FIG.

FIG. 4 is an F with a test function showing a second embodiment of the present invention.
It is a block diagram of a configuration of an IFO type memory.

FIG. 5 is a timing chart in the case of 4 bits of FIG.

[Explanation of symbols]

10 FIFO type memory 20 ₀ Second selector 20 _{1 to} 20 _n First selector 21 Test signal input terminal 22 Test mode selection terminal 23 Test signal output terminal 30 Test signal generation circuit

Claims (2)

[Claims] 1. An i-number (where i is a positive integer) data input terminal and an i-number data output terminal, and writing of i-bit input data to the data input terminal in order by a shift clock. In a semiconductor memory device for reading i-bit output data from the data output terminal, one of the (i-1) -bit input data and the (i-1) -bit output data is selected by a selection signal. The (i-1) number of first selectors which respectively select and input to the (i-1) number of data input terminals, and one of the remaining 1-bit input data and the test signal are selected. A second selector that is selected by a signal and is input to the remaining one data input terminal; a test signal input terminal that inputs the test signal from the outside; The semiconductor memory device of the output data test signal output terminal for outputting to the outside, characterized in that the test mode select terminal for inputting from outside the selection signal, is provided. 2. The semiconductor memory device according to claim 1, further comprising a test signal generation circuit that generates the test signal based on the shift clock and inputs the test signal to the second selector, in place of the test signal input terminal. A semiconductor memory device provided.