JP2002005997A - Self-synchronous type logic circuit having testing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a self-synchronous type logic circuit having a testing circuit allowing an easy scanning test. SOLUTION: Each of scanning test-capable resistors 105, 106, 107 is provided with a pipeline data transmitting function for transmitting parallel data of multiple-bit and a function for transmitting the contents of a test serially in a testing time. Scanning test-capable self-synchronous signal control circuits 101, 102, 103 switch an acknowledge signal into transmission of a test clock signal in the testing time for performing the test easily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a self-synchronous logic circuit having a test circuit, and more particularly to a large-scale integrated circuit (LSI) of a logic circuit having a self-synchronous pipeline.
The present invention relates to a self-synchronous logic circuit having a test circuit for testing.

[0002]

2. Description of the Related Art A logic circuit for performing pipeline data processing in synchronization with a clock signal is usually configured as a logic circuit LSI. These logic circuit LSIs are becoming faster, larger in scale and smaller in size year by year, and as a result, wiring lengths are increased, wiring widths are reduced, wiring thicknesses are reduced, and wiring intervals are reduced. The parallel capacitance between the series resistance of the wiring and another wiring is increasing. For this reason, the rounding of the signal waveform and the delay are increasing, but this effect varies greatly depending on the difference in the length of the wiring. For this reason, for example, if a latch circuit that synchronizes at the rising edge of a clock signal is randomly arranged on the entire chip, it is difficult to make the wiring lengths to all the flip-flops constituting the latch circuit uniform, and the same phase Transmission of a single clock signal is becoming more difficult.

In order to avoid this problem, a tree structure in which clock buffer circuits are arranged so that clock signals are distributed so as to have equal delays over the entire chip is adopted. This involves a multi-stage clock buffer circuit. The cost and design difficulty are increasing, for example, when necessary.
Therefore, a logic circuit having a self-synchronous pipeline which synchronizes registers at each stage of the pipeline with each other and does not require a single clock signal for synchronization is under study.

A logic circuit having such a self-synchronous pipeline is disclosed, for example, in Japanese Patent Application Laid-Open No. 8-65139.
And JP-A-9-251058.

FIG. 4 is a block diagram showing an example of such a self-synchronous data transmission line. In FIG. 4, registers 601, 602, and 603 form a pipeline for sequentially transferring a data path input from the previous stage to the next stage, and a combinational circuit 108 is provided between the output of the register 601 and the input of the register 602. The combination circuit 109 is connected between the output of the register 602 and the input of the register 603. The combination circuits 108 and 109 process data output from the registers 601 and 602 in the preceding stage, respectively, and are configured by a combination of only basic gate circuits without having a circuit for holding an internal state such as a flip-flop. I have.

The self-synchronous signal control circuits 604, 605 and 605 correspond to the registers 601, 602 and 603, respectively.
A self-synchronous signal control circuit 604 outputs a clock signal to a corresponding register while performing handshake with each other. Each of the registers 601, 602, and 603 outputs the held data to the next stage when a clock signal is given from the corresponding self-synchronous signal control circuit.

FIG. 5 is a specific block diagram of the self-synchronous signal control circuit shown in FIG. In FIG. 5, a transfer request signal CI from a preceding stage is input to a CI input terminal 701, and an RO output terminal 702 returns an acknowledge signal indicating that the transfer request signal CI has been received to the preceding stage. The CP output terminal 703 sends out a clock pulse for storing data in a register in response to a transfer request by a transfer request signal CI from the preceding stage. The CO output terminal 704 provides a transfer request signal from the preceding stage to the next stage, and the RI input terminal 705 receives an acknowledge signal indicating that the transfer request signal from the CO output terminal 704 has been sent to the next stage.

Further, the self-synchronous signal control circuit includes a flip-flop 706, a 4-input NAND gate 707, and a flip-flop 708. Flip-flop 706 holds a transfer request acceptance state, flip-flop 708 holds a transfer request state to the next stage, and NAND gate 707.
Synchronizes flip-flops 706 and 708. Transfer request signal CI is input to the S input terminal of flip-flop 706, and transfer request signal CI is supplied to NAND gate 70.
7 is also provided to one input. Flip-flop 7
The Q output signal 06 is supplied to one input terminal of the NAND gate 707, and the Q inverted output signal of the flip-flop 706 is output to the RO output terminal 702. RI input terminal 7
05 input to the NAND gate 707
Input and the reset input of flip-flop 708. The output signal of NAND gate 707 is applied to the reset input of flip-flop 706 and the set input of flip-flop 708. The Q output of flip-flop 708 is output to CP output terminal 703, and its Q inverted output is applied to CO output terminal 704 and also to NAND gate 707.

FIG. 6 is a time chart for explaining the operation of FIGS. 4 and 5. Next, the operation of the conventional self-synchronous data transmission path will be described with reference to FIGS. The transfer request signal CI shown in FIG. 6B is input at the “L” level to the CI terminal of the first-stage self-synchronous signal control circuit 604 in the pipeline shown in FIG. Processing data shown in FIG. 6A is input to the input terminal D. This register 601 has a plurality of D-type flip-flops arranged in parallel.
Input data is taken in synchronism with the rise of the clock pulse from the corresponding self-synchronous signal control circuit 604 and held. By receiving the transfer request CI signal,
The flip-flop 706 holding the transfer request acceptance state shown in FIG.
Transfer request signal CI shown in FIG.
The acknowledge signal shown in FIG.
Returned by level. Thereby, transfer request signal CI returns to "H" level, and NAND gate 70 shown in FIG.
7 becomes "L" level as shown in FIG. 6D, and the flip-flop 70 holding the transfer request to the next stage.
8 is set, the flip-flop 706 is reset, and the RO signal to the preceding stage returns to “H” level.

When flip-flop 708 is set, the clock signal applied to register 601 attains the "H" level as shown in FIG. 6 (e), and register 601 takes in data at the rising edge of the clock pulse. Data is output from the output terminal Q as shown in FIG. The output data is input to the combination circuit 108. Also, the self-synchronous signal control circuit 604
A transfer request signal CO to the next stage shown in FIG. This pulse signal is input to the self-synchronous signal control circuit 605 constituting the second stage pipeline shown in FIG.
When the RO signal from the self-synchronous signal control circuit 605 at the stage is 1
6 (i) to 6 (m) are generated in a similar manner, and the data processed by the combinational circuit 108 is stored in the second register. The signal is latched by 602, output from the Q output, and input to the combinational circuit 109.

The same operation is performed by the self-synchronous signal control circuit 60.
5, 606, and the data processed by the combinational circuit 109 is latched by the third-stage register 603 and output to the data bus.

As described above, a required number of pipeline processing circuits shown in FIG. 4 are connected in cascade, and a series of pipeline processing can be performed by repeating these operations. These operations are generally called data transmission by a handshake method.

On the other hand, in order to perform the same data processing by clock synchronization processing, it is necessary to apply a single clock for synchronizing the same phase to all the registers of the processing circuit. It will take a tree structure to distribute. However, when the circuit configuration shown in FIG. 4 is adopted, a single clock for synchronizing the signals in the same phase is not connected, and there is no increase in the size of the clock signal generation circuit and increase in the design difficulty. In addition, a large amount of data processing can be performed on the pipeline.

[0014]

Generally, a test signal is input to all logic circuits before shipment of an LSI, and a test is performed to confirm that the circuits are generated without failure and operate properly. Normal operation is performed by a logic circuit for performing pipeline data processing having a self-synchronous circuit for synchronizing pipeline registers in an LSI or a logic circuit for performing synchronization with a single clock signal and performing pipeline data processing. In order to make sure that all the input values are applied to the circuit inputs for each combinational circuit sandwiched by each pipeline register, It is necessary to input the combination and compare the output value with the expected value.

However, when the number of stages of the pipeline register is large, there is no means for giving an arbitrary input value to the input of the combinational circuit in the intermediate stage and no means for finding the value of the output value in the intermediate stage. It is extremely difficult to test all the combinations of inputs to produce all the states of the combinational circuit at the intermediate stage from the input stage of the circuit, and to extract the result, and the failure detection rate is low.

In such a case, in a general circuit driven by a single clock, an input is switched to a register during a test and a shift operation is performed, so that input of arbitrary test data and reading of a register value as a test result are performed. The scan test method to be performed may be adopted.

FIG. 7 is a block diagram showing an example of a logic circuit according to a conventional scan test technique. 7, a pipeline is formed by scan test corresponding registers 105, 106, and 107, a combinational circuit 108 is connected between scan test corresponding registers 105 and 106, and a combination circuit is provided between scan test corresponding registers 106 and 107. The circuit 109 is connected. The scan data SDI is input to the scan data input terminal during the test, the scan test enable signal STE for switching between the scan mode and the capture mode is input to the scan test terminal during the test, and the captured test result is input to the scan data output terminal. It is output as scan data SDO.

FIG. 8 is a circuit diagram showing the internal configuration of the scan test corresponding registers 105, 106 and 107 shown in FIG.

In FIG. 8, D-type flip-flops 121, 122, 123... 12n constituting a register are provided in parallel, and selectors 111, 112 are provided in front of these D-type flip-flops 121, 122, 123. , 113... 11n are provided. The serial data SI and the first bit D0 of the parallel data are input to the first-stage selector 111, and one of the inputs is output to the corresponding D-type flip-flop 121 by the SE signal for switching.

The second-stage selector 112 receives the Q output of the first-stage D-type flip-flop 121 and the second bit D1 of the parallel data, and inputs one of them to the D-type flip-flop 122 by the SE signal.
Similarly, the Q output of the D-type flip-flop 122 and the third bit D2 of the parallel data are input to the third-stage selector 113, and one of them is sent to the corresponding D-type flip-flop 123 by the SE signal. Output. Hereinafter, the selector 11n and the D-type flip-flop 12n up to the n-th stage are similarly configured.

When the SE signal for switching attains the "L" level, the selectors 111, 112, 113... 11n are respectively switched to the parallel data side, and the D-type flip-flops 121, 122, 123. , D2,... D
n is output as it is.

On the other hand, when the SE signal is switched to the "H" level during the test, the selector 11 outputs serial data, and the selectors 112, 113... 11n are D-type flip-flops 121, 122, 123.
(N-1) is output to the corresponding D-type flip-flop 1
, 12n, and operates as a shift register for sequentially shifting serial data. By connecting the SI terminal and SO terminal of such a register capable of scan test in series, and inputting an operation clock, an arbitrary external value can be input to the pipeline register via the scan data input terminal. , And the test result can be output from the scan data terminal SO. However, in a logic circuit having a self-synchronous pipeline based on a handshake method that does not use a clock signal as shown in FIG. 4, a scan test as shown in FIG. The circuit cannot be adopted.

Therefore, a main object of the present invention is to provide a self-synchronous logic circuit having a test circuit capable of easily performing a scan test.

[0024]

According to the present invention, there are provided registers for holding a plurality of bits of parallel data and constituting a pipeline, and provided in correspondence with each of the registers, in response to a transfer request from a preceding stage by a transfer control signal. The transfer permission is given to the previous stage, the data is output from the register of the previous stage, the data is held in the corresponding register, and the transfer is requested to the next stage and held in the register when the transfer permission is given from the next stage. In a self-synchronous logic circuit including a self-synchronous signal control circuit that performs data flow processing by transferring data to a register at the next stage, the register includes a data transfer that transfers a plurality of bits of data in parallel during normal operation and a data transfer during a test. It has a function to transfer the contents serially, and the self-synchronous signal control circuit switches the data transfer signal to the test clock signal transmission during the test. And wherein the Rukoto.

Therefore, it is not necessary to wire a clock for a test, and a logic circuit having a self-synchronous pipeline capable of easily performing a scan test can be realized.

Means for inputting a test clock signal instead of permitting transfer by the transfer signal of the self-synchronous signal control circuit at the time of testing; means for invalidating the transfer request signal;
A means for supplying a test clock signal to a control signal of the pipeline register is included.

Furthermore, the register outputs a plurality of bits of parallel data from the corresponding flip-flop at the time of data transfer and a flip-flop which is provided corresponding to each of the plurality of bits of parallel data. , And a selector for outputting data serially.

[0028]

FIG. 1 is a block diagram of a self-synchronous logic circuit having a test circuit according to an embodiment of the present invention. In FIG. 1, a scan test corresponding register 10
Numerals 5, 106 and 107 constitute a pipeline register, which is configured in the same manner as in FIG. Then, parallel data composed of a plurality of bits is input to D inputs (D0 to D
n) The scan data SDI for the test is input to the terminal, and is input to the SI input terminal. The scan test enable signal STE is supplied to each scan corresponding register 105,
The signals are input to SE input terminals 106 and 107. The scan test enable signal STE switches to the scan mode when testing the scan test correspondence registers 105, 106, and 107, and switches to the capture mode during normal operation.

That is, the selectors 111, 111 shown in FIG.
11n, the parallel data or serial data is converted into D-type flip-flops 121, 1
12n are switched by the scan test enable signal STE. S of each scan test corresponding register 105, 106, 107
The captured test signals are sequentially output to the O terminal,
Terminal SO of the final stage scan test corresponding register 107
The test result output from scan data output SDO
Is output as

A combination circuit 108 is connected between the output of the scan test corresponding register 105 and the input of the scan test corresponding register 106, and outputs the scan test corresponding register 106 and the scan test corresponding register 107.
A combination circuit 109 is connected between the input and the input.

The scan test corresponding self-synchronous signal control circuits 101, 102, and 103 are provided corresponding to the scan test corresponding registers 105, 106, and 107, respectively. , 103 are the transfer request signal CI from the previous stage, the acknowledge signal RO to the previous stage, and the transfer request signal CO to the next stage in the same manner as the self-synchronous signal control circuits 604, 605, and 606 described in FIG. , An acknowledge signal RI from the next stage is input and output, and a scan clock switching signal SCK is input. The scan clock switching signal SCK switches the clock signal connection method between the normal operation and the test operation.

FIG. 2 is a specific circuit diagram of the scan test-compatible self-synchronous signal control circuits 101, 102, and 103 shown in FIG. 2, a transfer request signal CI from a previous stage is input to a CI input terminal 201, and an RO output terminal 202 outputs an acknowledge signal RO to the previous stage. C
P output terminal 203 outputs the clock signal to a corresponding scan test register. The CO terminal 204 outputs a transfer request signal CO to the next stage, the acknowledge signal RI from the next stage is input to the RI input terminal 205, and the scan clock switching signal SCK is input to the terminal 211.

Further, the scan test-compatible self-synchronous signal control circuits 101, 102, and 103 include flip-flops 206 and 208, a 4-input NAND gate 207, and selectors 209 and 210, respectively. Flip-flop 2
06 and 208 and the NAND gate 207 correspond to the flip-flops 706 and 708 and the NAND gate 707 shown in FIG. The selector 209 switches the test clock signal input from the next stage via the RI input terminal 205 during the test to output the test clock signal to the preceding stage as an RO signal.

The selector 210 switches the clock signal input through the RI input terminal to which the RO signal of the next stage is input during the test to output the clock signal to the register through the CP terminal 203. That is, when the “L” level signal is input to the SEL terminal, the selectors 209 and 210 output the signal input to the input terminal A from the output terminal Y,
When an “H” level signal is input to the SEL terminal, the signal input from the output terminal Y to the input terminal B is output.
These selectors 209 and 210 can be realized with a simple circuit configuration by a known technique such as a multiplexer.

FIG. 3 is a time chart for explaining the specific operation of FIGS. 1 and 2.

Next, a specific operation of the embodiment of the present invention will be described with reference to FIGS. During normal operation, scan test enable signal STE sets scan clock switching signal SCK to both "L" levels. Then, the selectors 209 and 210 shown in FIG.
Since the output Y is connected to the A side, the circuit configuration is the same as that of the conventional self-synchronous signal control circuit shown in FIG. As a result, the RI signal is output as the output of the selector 104 shown in FIG. 1, so that the operation is the same as that of the conventional example described based on FIG. 1, and the detailed description is omitted here.

Next, the operation at the time of the test will be described.
During the test, scan clock switching signal SCK is set to “H” level. On the other hand, the scan test enable signal STE is a signal for switching between the scan mode and the capture mode at the time of the test. When the scan test enable signal STE is set to “H” level as shown in FIG. , 107 are in the scan mode, and when set to the “L” level, they are in the capture mode. When the scan clock switching signal is set to “H” level, output terminals Y of selectors 209 and 210
Outputs the signal input to the input terminal B. Therefore, the RI signal output from the next-stage RO output terminal and input to the RI input terminal 205 is directly output from the RO output terminal 202 by the selector 209 and input to the previous-stage RI input terminal. Further, the signal input to the RI input terminal 205 is
The data is output from the output terminal 203 in the same manner.

This means that the selector 104 shown in FIG.
The scan test clock signal STC is output from the output terminal and input to the RI input terminal of the scan-compatible self-synchronous signal control circuit 103, so that all the scan test-compatible self-synchronous signal control circuits 101, The scan test clock signal is transmitted to 102 and 103, and the scan test clock signal STC is simultaneously output to the CP signal for controlling the data fetch and latch of the scan test corresponding registers 105, 106 and 108 which are pipeline registers. . As a result, regardless of the CI signal, all the scan test correspondence registers 105, 106, and 107 operate in synchronization with the scan clock signal.

Next, the scan test corresponding register 10
Operations of 5, 106 and 107 will be described.

In the normal operation, the scan test enable signal STE is at "L" level,
Reference numeral 4 indicates that the signal input to the input terminal A is output from the output terminal Y. Therefore, data D0 to Dn are input in parallel to D-type flip-flops 121 to 12n forming the pipeline register shown in FIG. 8, and these data are latched at the rise of clock signal CLK, and output from each output terminal Q. Is done.

Next, at the time of a test, the scan test enable signal STE is set to "H" level as shown in FIG. Therefore, the selector 11 shown in FIG.
1 to 11n output the signal input to the input terminal B to the output terminal Y
Output from Thus, the D-type flip-flops 121 to 12n constituting the pipeline register do not take in data in parallel, but shift serial scan data for testing the combinational circuit 108 shown in FIG. Each D-type flip-flop 121-
12n will be transferred.

When scan data, which is serial data, is input from the input terminal SI, synchronization is established at the rise of the scan test clock signal STC, and the scan data is transferred to the D-type flip-flops 121 to 12n one after another. As shown in FIG. 3D, the data is transferred from the output terminal SO to a D-type flip-flop constituting a pipeline register of the next stage. From the output terminal Q of each of the D-type flip-flops 121 to 12n, successive scan data is output to the combinational circuit. Thereafter, the transfer is similarly continued, and the scan data is loaded into the D-type flip-flops constituting all the pipeline registers.

When serialized test signals are sequentially input from the scan data input terminal SI as the scan data, the test signals are transferred to the D-type flip-flops 121 to 12n,
Test signals are output to 8, 109. FIG.
As shown in (h), the transfer of the test signal is continued until the necessary test signal is input to all the scan test correspondence registers 105, 106, and 107. Note that FIG.
(E) shows a serial transfer pattern of test data for the combinational circuit 109. During the test result output period, serial data of the test result of the preceding stage is output. FIG. 3H shows a serial transfer pattern of test data for a subsequent test. During the test result output period, serial data of the test result of the combinational circuit 108 is output. When the output of the necessary test signal is completed, the test result data for the test signal is output to the output terminals of the combinational circuits 108 and 109.

Next, the scan test enable signal ST
E is set to the "L" level, and one rising edge of the scan test clock is input in the "L" level state. Thereby, the D which constitutes each pipeline register
The type flip-flops 121 to 12n perform a parallel operation, and the D-type flip-flops 121 to 12n take in and latch test result data (parallel signals) from the combination circuits 108 and 109.

Thereafter, scan test enable signal STC is returned to "H" level again. When the scan test clock signal STC is input to the CLK terminal in FIG. 8, the latched test result data is serially transferred by the D-type flip-flops 121 to 12n. The serialized test result data is transferred from the output terminal SO to the input terminal SI of the scan test corresponding register of the next stage, and is output as the scan data output from the output terminal SO of the last final stage scan test corresponding register 107. Is done. By comparing this value with the expected value of a correct operation, it is possible to test whether the device is operating correctly.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0047]

As described above, according to the present invention, the conventional self-synchronous logic circuit does not require a clock and processes data with a transfer request signal and a transfer permission signal.
While it was difficult to exchange signals with a clock-synchronized test circuit, the connection between the self-synchronous control circuits was switched to the test clock during the test, eliminating the need to wire the clock for the test. Thus, it is possible to realize a logic circuit having a self-synchronous pipeline capable of easily performing a scan test.

Further, even if the logic circuit having the self-synchronous pipeline structure is large-scale, the test can be easily performed, so that a good product can be supplied to the market at low cost and in a stable manner. In addition, the self-synchronous logic circuit can have an advantage compared to the clock synchronous logic circuit having a tighter design of clock signal distribution due to the possibility of increasing the scale. Further, the increase in the number of circuits for realizing the present invention is insignificant, and does not increase the cost of the circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a self-synchronous logic circuit having a test circuit according to an embodiment of the present invention.

FIG. 2 is a specific circuit diagram of the scan test-compatible self-synchronous signal control circuit shown in FIG.

FIG. 3 is a time chart for explaining the operation of FIGS. 1 and 2;

FIG. 4 is a block diagram illustrating an example of a self-synchronous data transmission path.

FIG. 5 is a specific block diagram of the self-synchronous signal control circuit shown in FIG.

FIG. 6 is a time chart showing an example of a logic circuit according to a conventional scan test technique.

FIG. 7 is a block diagram illustrating a specific example of a scan test corresponding register illustrated in FIG. 6;

8 is a specific circuit diagram of the scan test corresponding register shown in FIG.

[Explanation of symbols]

101, 102, 103 Self-synchronous signal control circuit for scan test, 104, 111 to 11n, 209, 21
0 selector, 105, 106, 107 scan test corresponding register, 108, 109 combinational circuit, 20
6,208 flip-flops, 207 NAND gates, 121 to 12n D-type flip-flops.

Claims (3)

[Claims] 1. A register that holds a plurality of bits of parallel data to form a pipeline and is provided corresponding to each register, and a transfer control signal gives a transfer permission to the preceding stage in response to a transfer request from the preceding stage. Output the data from the register in the previous stage, hold the data in the corresponding register, and request the transfer to the next stage, and when the transfer permission is given from the next stage, the data held in the register is transferred to the register in the next stage. A self-synchronous logic circuit including a self-synchronous signal control circuit that performs data flow processing by transferring data to the register. The self-synchronous signal control circuit switches the data transfer signal to the transmission of a test clock signal during the test. Wherein the self-synchronous type logic circuit having a test circuit. 2. A data transfer request signal from the next stage is output during data transfer, and the test clock signal is supplied to a first register in the test in place of a transfer enable signal from the next stage of the self-synchronous signal control circuit. A self-synchronization signal control circuit for invalidating a transfer request signal from the next stage during the test, and supplying the test clock signal to the register as a control signal during the test. 2. The self-synchronous logic circuit according to claim 1, further comprising signal output means. 3. The register includes: a flip-flop provided corresponding to each of the plurality of bits of parallel data; and a plurality of bits of parallel data output from the corresponding flip-flop during the data transfer. 3. The self-synchronous logic circuit according to claim 2, further comprising a selector that connects the flip-flops serially and outputs data serially.