JPH03191883A - Electronic circuit with test function - Google Patents

Abstract

PURPOSE:To reduce a test time by letting a scan latch selectively output the input or output of a previous stage circuit portion to be tested to a subsequent stage circuit portion to be tested without being synchronized with a clock in a test mode. CONSTITUTION:A test mode is a condition wherein only part of control signals CC1, CC2...CCm fix the control signals of the terminals c1 and c2 of a scan latch circuit to levels 'L' and 'H', respectively, and the other control signals fix the control signals of the terminals c1 and c2 of the scan latch circuit to the level 'H'. At this time, the scan latch circuits 11-1n taken in data inputted to input terminals (b) and the data are inputted to output terminals (d). Similarly, the data are inputted to the terminals (b) of scan latch circuits 21-2n. Since scan latch circuits m1-mn similarly take in the data inputted to terminals (b) to output the data to terminals (d), the data outputted to the terminals (d) of the circuits m1-mn are outputted as they are from data output terminals O1-On after all.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic circuit with a test function, which has a data processing circuit and a test circuit for testing each circuit part constituting the data processing circuit. It is.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional electronic circuit with a test function, in which a parallel scan register type test circuit is built into the output side of each circuit section in order to test each circuit section constituting the data processing circuit. It is.

In the figure, each circuit portion 1a, 2a, ...ma
are composed of, for example, a combinational logic circuit, and each has n input terminals 11, 21 . ...ml and n output terminals 12, 22. ...~2.

The test circuits each include n scan latch circuits 1.
~1. ,2. ~2. ．． ．． m parallel registers (unit test circuit) consisting of ..., ml to m, , 2...1
It is composed of m. Each scan latch circuit 11”
"111+21"'211+..., It~m11
is the first input terminal a, the second input terminal b, and the control terminal C.
and an output terminal d, and one of the signals input to the first input terminal a and the second input terminal is selectively controlled by the control signal C (C1''Cm) input to the control terminal C. It is designed to be outputted to output terminal d.

This scan latch circuit 11~1,,2,~2°.

...2ml~m, 1 is the first one in synchronization with a clock signal (not shown) when the control signal C is at the "L" level.
It takes in the signal input to input terminal a and outputs it as is. On the other hand, when the control signal C is at rHJ level, it takes in the signal input to the second input terminal A in synchronization with the clock signal. Output as is.

FIG. 4 shows the configuration of the scan latch circuit. The scan latch circuit includes an inverter 101 and a multiplexer 104 consisting of two TGs (transfer gates) 102 and 103.
and a latch circuit 109,1 consisting of an n-channel TG105, a p-channel TG106, and an inverter 1071O8.
10 and an inverter 111. In this multiplexer 104, when the control signal C input to the control terminal C is at the rLJ level, TG102 is turned on and TG103 is turned off, and the data input to the first input terminal a is transferred to the launch circuit lO9, When control signal C is at rHJ level, TG102 is off, TG1
03 is turned on, and the data input to the second input terminal is transferred to the latch circuit 109.

In the launch circuits 109 and 110, the clock power φ is rHJ.
When the clock power φ is at the rLJ level, the TG105 is turned on and data is taken in, and when the clock power φ is at the rLJ level, the TG105 is turned on.
is turned off, TG 106 is turned on, and data is held in TG 106 and inverters 107 and 108.

A first parallel register 1 is arranged on the output side of the first circuit part 1a, a second parallel register 2 is arranged in the second circuit part 2a
is placed on the output side of
A parallel register m is arranged on the output side of the m-th circuit part ma. In this way, parallel registers 1 to m are arranged on the output sides of circuit parts 1a to 1a, respectively, and 1
A set of circuit elements is configured by cascading two circuit parts and one parallel register, and the circuit part la-
The entire data processing circuit is constructed by cascading ma.

The n input terminals 11 of the first circuit portion 1a are connected to data input terminals 11 to 7, respectively.

Each scan latch circuit 1 configuring the first parallel register 1. -1. The first input terminal a of the first circuit portion 1a
The second input terminals are connected to the data input terminals 1 to I, respectively. And each scan latch circuit 11
~1. ．． The output terminal d of is connected to each input terminal 21 of the second circuit portion 2a.

Similarly, the first input terminal a of each scan latch circuit 21 to 2 constituting the second parallel register 2 is connected to the second input terminal a.
The second input terminals are connected to the output terminals 22 of the circuit portion 2a, respectively, and the second input terminals are connected to the output terminals d of the scan latch circuits 1 to 17 forming the first parallel register l. There is. Then, each scan latch circuit 21-2. .

The output terminal d of is connected to each input terminal 31 of the third circuit portion 3a.
are connected to each. Each terminal of each scan latch circuit is connected as described above, and furthermore, the first input terminal a of each scan latch circuit m1 to m constituting the m-th parallel register m is connected to the first input terminal a of the m-th circuit portion ma. Each output terminal m
2, and the second input terminals are connected to each scan latch circuit (m-1), ~( m-1)
.

are connected to the output terminals d of the respective terminals. The output terminals d of the scan latch circuits m1 to m are connected to the data output terminals 01 to On, respectively.

Each scan latch circuit 11-1. ,2. 〜27゜・・１
The control terminals C of m1 to m7 are connected to each parallel register 1, 2 .・
. . . They are commonly connected every 2 m, and control signals C1, C2° . . . , Cm are applied to each of them independently.

Next, the operation of the electronic circuit with test function shown in FIG. 3 will be explained.

The operation of this test circuit is divided into an operation mode and a test mode.

The operation mode is control (no.c1.c2゜...
, Cm are all fixed at the rLJ level.

At this time, each scan latch circuit 1° to I Fil
21-2, Ig...') ml-fn6 take in the data input to the first input terminal a and output it as is to the output terminal d, so the data input to the data input terminals 11-■o The data is sequentially processed by circuit portions 1a to 1ma in accordance with a clock signal (not shown), and then output to data output terminals 0° to 0. ．． are output simultaneously and in parallel.

Test mode is control (no.c1.c2...
, Cm remains fixed at the rLJ level.

For example, when testing the second circuit portion 2a,
Control signals C1, C3, . . . Cm are set to rHJ level, and control signal C2 is set to rLJ level. At this time, the scan latch circuits l, ~17 are
Since the data input to each second input terminal is taken in and output to the output terminal d, the data input terminal ■
, ~■A, the n-bit test data is input as is to the second circuit portion 2a. In addition, the scan latch circuit 2. ~2. ．． are the respective first input terminals a
Since the data input to the scan latch circuits 21 to 27 are taken in and outputted to the output terminal d, the data processed by the second circuit portion 2a is taken in to the scan latch circuits 21 to 27 and outputted to the output terminal d.

Furthermore, scan latch circuit 3. ~3. ．． takes in the data input to the second input terminal d, outputs it to the output terminal d, and thereafter uses the scan latch circuits 41 to 47 .・・・
・2m, ~mn take in the data input to the second input terminal d and output it to the output terminal d, so in the end, the scan latch circuit 2. The data being output to the output terminal d of ~2, , is output as is from the data output terminal 0l-Oll.

In this way, the n-bit test data input to the data input terminals 11 to I is taken into the second circuit portion 2a via the first parallel register l, and After being processed by the second parallel register 2 to the m-th parallel register m, the data is output to the data output terminal 0. ~0. is output to. Therefore, in this test mode, equivalently, one stage of parallel registers is installed in the front stage of the second circuit portion 2a, and (ml) of parallel registers are installed in the rear stage of the second circuit portion 2a.
The configuration is such that the stages are installed in series. Since both the circuit portion 2a and the parallel register lm perform data processing in synchronization with the clock signal, the data input terminals 1. ~
(2) The n-pin data input to 7 is processed in the circuit portion 2a and then output simultaneously and in parallel from data output terminals O1 to O0.

In this manner, in this electronic circuit with a test function, test data is input in parallel only to a desired circuit portion, and data processed only in that circuit portion is output in parallel. Then, by connecting a predetermined measuring circuit to the output terminals O1-07, the output of a desired circuit portion is measured, and that circuit portion is tested.

[Problem to be solved by the invention]

Conventional electronic circuits with test functions are configured as described above, and when there are m circuits to be tested, in test mode, it takes m clock cycles to provide an input and obtain an output. However, as the number of circuit parts increases, the time required to test each circuit part increases.

The present invention has been made in view of these points, and an object thereof is to provide an electronic circuit with a test function that can shorten test time.

[Means to solve the problem]

In order to achieve such an object, in the electronic circuit with a test function according to the present invention, the scan latch circuit selectively inputs or outputs the input or output of the circuit under test in the previous stage without synchronizing with the clock in the test mode. It is now possible to output to the circuit under test.

[Effect]

In the test mode, the electronic circuit with a test function according to the present invention supplies input data to the circuit under test and outputs output data from the circuit under test without synchronizing with a clock.

〔Example〕

FIG. 1 is a configuration diagram showing an embodiment of an electronic circuit with a test function according to the present invention. In the same figure, each circuit portion 1a
12al..., ma are composed of combinational logic circuits, for example, and have n input terminals 11, 21 .
. . , ml and n output terminals 12, 22 .・・・
, m2.

Each test circuit consists of n scan latch circuits lI
m parallel registers 1, 2 . . . ~l, , 21~21%+HHl, ml~m, ...consisting of 1m. Each scan latch circuit 11-1, . 2. ~2
7. . . 1m, to m7 have a first input terminal a, a second input terminal s, 2-bit control terminals cl and c2, and an output terminal d.

FIG. 2 is a circuit diagram showing the scan latch circuit in this embodiment. This scan latch circuit is connected to inverter 1
a multiplexer 104 consisting of n-channel TGs 102, 103, and n-channel TGs 105. Launch circuit 109.110 consisting of p-channel TG 106 and inverters 107, 108, and OR circuit 112.1
13 and an inverter 114. This multiplexer 104 has a terminal cl control signal rLJ.
level, TG102 is on, TGIO3 is off, the data input to the first input terminal a is transferred to the latch circuit 109, and the control signal of the terminal C1 is r
At HJ level, TGIO2 is off, TG103
is turned on, and the data input to the second input terminal is transferred to the latch circuit 109.

In the latch circuit 109, when the clock signal φ' is at the "H" level, the TG 105 is turned on and data is taken in.
When φ' is "L" level, TGI05 is off, TG
106 is turned on, TG106. Inverter 10
Data is held at 7,108. The tick circuit 110 also operates in a similar manner.

The OR circuits 112 and 113 are such that the control signal at the terminal C2 is rL.
When at J level, clock signal φ and inverter 11
The inverted signal φ outputted to the latch circuit 109
, 110 as signals φ' and r, respectively, and when the control signal at terminal C2 is at the rHJ level, the signals φ'φ' on the clock input terminals of the latch circuits 109 and 110 are fixed at the rHJ level. .

Therefore, the scan latch circuit has a configuration that can realize the following first state, second state, and third state. In the first state, the control signal of terminal cl is r
When the control signal of the terminal C2 is at the LJ level and the control signal at the terminal C2 is at the rLJ level, the data at the input terminal a is taken in, and the data is taken into the latch circuits 109 and 110 in synchronization with the clock φ and held there. In the second state, the control signal at terminal CI is “
When the control signal at the terminal C2 is at the rHJ level and the control signal at the terminal C2 is at the rHJ level, the launch circuits 109 and 110 take in data from the input terminal d and output the data to the output terminal d regardless of the clock. In the third state, the control signal at the terminal C1 is at the "L" level, the control signal at the terminal C2 is at the rHJ level,
This is a state in which the launch circuit 109110 takes in data at the input terminal a and outputs the data to the output terminal d regardless of the clock.

A first parallel register 1 is arranged on the output side of the first circuit part 1a, a second parallel register 2 is arranged in the second circuit part 2a
is placed on the output side of
A parallel register m is arranged on the output side of the m-th circuit part ma. In this way, parallel registers 1 to m are arranged on the output side of circuit portion 1axma, and 1
A set of circuit elements is configured by series connection of two circuit parts and one parallel register, and the circuit part lax
The entire data processing circuit is constituted by series connection of ma.

The n input terminals 11 of the first circuit portion 1a are connected to data input terminals 1 to 7, respectively.

Each scan latch circuit 11 to 1 configuring the first parallel register 1. The first input terminal a of the first circuit portion 1a
are connected to the respective output terminals 12, and the second input terminals are connected to the data input terminals I, -1, respectively. Then, each scan latch circuit 11 to 1
The output terminal d of 7 is connected to each input terminal 2 of the second circuit part 2a.
1, respectively.

Similarly, each scan latch circuit 21 to 2 . The first input terminal a of
The second input terminals are respectively connected to the output terminals d of the scan latch circuits 11 to 17 constituting the first parallel register 1. . Then, each scan latch circuit 21-2. % output terminals d are respectively connected to each input terminal 31 of the third circuit portion 3a. Each terminal of each scan latch circuit is connected as above, and furthermore,
The first input terminal a of each scan latch circuit m1 to m7 constituting the m-th parallel register m is connected to the m-th circuit portion ma.
The second input terminal is connected to each output terminal m2 of ``J (m - 1)'' parallel register (m -
1) Each scan latch circuit (m
-1), ~(m-1).

are connected to the output terminals d of the respective terminals. The output terminals d of each scan latch circuit m1-m7 are connected to data output terminals O1-07, respectively.

Each scan latch circuit 11-1. ．． 2. ~2. ．． .

The control terminals cl, c2 of 1m, ~m7 are connected to each parallel register 1, 2, . ... Commonly connected every 1 m, each independently receives 2-bit control signals CCI and CC.
2,...+, CCm are given.

Next, the operation of the electronic circuit with test function shown in FIG. 1 will be explained.

The operation of this test circuit is divided into an operation mode and a test mode.

The operation mode is control (K number cct, cc2, ・
. . . CCm is all fixed at the rLJ level. At this time, each scan latch time Hzl+~la+
Each of L~2m+...+m+~ma is in the first state and takes in the data input to the first input terminal a and outputs it as is to the output terminal d, so the data input terminals II~■ The data input to 7 is sequentially input to the circuit portion 1axm according to a clock signal (not shown).
After being processed by data output terminal 0.a. ~07 are output simultaneously and in parallel.

In the test mode, the control signal cc1. CC2,・
..., the third state in which only a part of CCm fixes the control signal of the terminal cl of the scan latch circuit to the rLJ level and the control signal of the terminal C2 to the rHJ level, and the other control signals are fixed to the scan latch circuit. terminal cl,
This is the second state in which both the control signals of c2 are fixed at the rHJ level. For example, when testing the second circuit portion 2a, the control signals CCI, CC3, .
. . . CCm is set to the second state, and the control signal CC2 is set to the third state. At this time, the scan latch circuits 11 to IR each take in the data input to the second input terminal 1 and output it to the output terminal d, so that the scan latch circuits 11 to IR respectively take in the data input to the second input terminal 1 and output it to the output terminal d. ~ ■ The n-bit test data input to 7 is directly input to the second circuit portion 2a.
is input.

Moreover, since the scan latch circuits 21 to 27 take in the data input to the respective first input terminals a and output it to the output terminal d, the data processed by the second circuit portion 2a is transferred to the scan latch circuits. 2. ~27 and output to the output terminal d. Furthermore, the scan latch circuits 31 to 31 take in the data input to the second input terminals and output it to the output terminals d, and thereafter scan latch circuits 4 to 31 take in the data input to the second input terminals and output it to the output terminals d. ~4. ．． ...2m, ~m, 1 takes in the data input to the second input terminal and outputs it to the output terminal d, so it is ultimately output to the output terminal d of the scan latch circuits 21 to 27. Data is output as is from data output terminals 01 to on.

In this way, the n-bit test data input to the data input terminals ■1 to ■ are taken into the second circuit section 2a via the first parallel register 1, and After being processed by the data output terminal 0.2a, the data is outputted to the data output terminals 0. ~0. output to l. Therefore, in this test mode, equivalently, the input terminal 21 of the second circuit portion 2a is connected to TG, the data input terminal 1, to 17 is connected via the inverter, and the output terminal 22 of the second circuit portion 2a is connected to T.
G is connected to data output terminals 01 to 07 via an inverter. And data input terminal ■,
~! The data applied to 7 is directly applied to the circuit portion 2a as parallel data regardless of the clock, and after being processed by the circuit portion 2a, it is directly output as parallel data from the data output terminals O1 to 07 regardless of the clock. .

Note that in the above embodiment, the circuit portion 1axma is configured with a combinational logic circuit, but it is not limited to this, and may include a circuit in which circuits are sequentially inserted, a circuit in a pipeline configuration that operates in synchronization with a clock signal, etc. , any kind of circuit is acceptable.

Further, in the above embodiment, the second
Although the circuit shown in the figure is shown, any type of circuit can be used as long as it selectively takes in the data of the first input terminal and the second input terminal without synchronizing with the clock in test mode and outputs it as it is to the output terminal. good.

Further, in the above embodiment, a configuration was shown in which the control signal to each scan latch circuit is given with 2 bits, but any number of bits may be used as long as the function of the scan latch circuit of this embodiment can be realized.

〔Effect of the invention〕

As explained above, the present invention has a structure in which the scan latch circuit operates without synchronization with the clock in the test mode, thereby supplying input data to the circuit under test and transmitting output data to the outside. Since output can be performed without synchronizing with the clock, it has the effect of shortening test time.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of an electronic circuit with a test function according to the present invention, Fig. 2 is a circuit diagram showing a scan latch circuit constituting the embodiment of Fig. 1, and Fig. 3 is a circuit diagram showing a conventional test function. FIG. 4 is a circuit diagram showing a scan latch circuit constituting the circuit of FIG. 3. l a, 2a, -・+, ma"e circuit part, 1~m
. . . Parallel registers, 11 to l-, L to 27. ...,
mi~m11...Scan latch circuit, ■1~I1
1...Data input terminal, 0. ~0. ...Data output terminal, 11~ml...Input terminal, 12~m2. d...
- Output terminal, a...first input terminal, b...second input terminal, cLC2...control terminal.

Claims (1)

[Scope of Claims] An electronic circuit with a test function, which has a plurality of circuit parts and a plurality of parallel registers installed between the plurality of circuit parts, and is capable of testing the circuit parts, The parallel register is composed of a plurality of scan latch circuits, and the scan latch circuit has a first input terminal, a second input terminal, an output terminal, a clock terminal, and a plurality of bit control terminals, and the first input terminal The signal input to the terminal or the second input terminal is selectively taken in by the signal input to the control terminal, and the signal input to the control terminal is latched or output as is in synchronization with a clock. A first input terminal of the scan latch circuit is connected to an output terminal of the preceding circuit section, and a second input terminal of the scan latch circuit is connected to an input terminal of the preceding circuit section. . An electronic circuit with a test function, wherein an output terminal of the scan latch circuit is connected to an input terminal of a subsequent circuit portion, and a control terminal of the scan latch circuit is commonly connected to each parallel register.