JPH0483184A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To economically perform a test by feeding signals from a built-in clock generating circuit to each register, and providing a self inverted logical value as an input value to the head register of a serial scan path, and repeating '0' and '1' at each clock. CONSTITUTION:A scan-mode control signal is provided to an IC 10 and a group of registers are converted to a state of shift registers and also a control signal 11 is set at a logical value '1' and then a clock generating circuit 6 starts generating clock signals and the registers 1 to 3 each operate as a shift register. Because the scan input of the register 1 is connected to a scan exit via a selector circuit 4 and a logic inversion circuit 7, the register 1 has its logical value inverted at each clock and '0' and '1' are alternately set for each clock and are transferred to each of the registers 2, 3 with a delay of one clock and '0' and '1' are repeated. Therefore the internal logical circuit of the IC 10 which is connected to the exit of each register also performs logical action and so a bias test can be easily carried out without feeding logical signals from the external using special IC test equipment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a serial scan path type function.

[Conventional technology]

It is known that the failure rate of semiconductor integrated circuits (hereinafter referred to as ICs) follows a statistical failure probability curve called the bathtub curve, and some ICs shipped as products may have initial failures. Contains an IC with a

Bias testing (hereinafter referred to as BT) is generally performed as a method of screening ICs that are likely to cause such initial failures in a short period of time to obtain only high-quality ICs.

Bias testing is generally a screening method in which power is supplied to the IC while the IC is exposed to a high-temperature atmosphere or a high-temperature/high-humidity atmosphere to accelerate and induce initial failures. As a more severe screening method, there is a dynamic BT which allows the IC to perform further logical operations under such conditions.

Conventionally, when performing such dynamic BT, an IC connector, a printed circuit board, a wiring cable, etc. are connected to the IC to be tested housed in a thermostatic chamber, and a logic signal is supplied from a logic signal generator to the IC. It was being put into operation.

[Problem to be solved by the invention]

As mentioned above, when performing conventional dynamic BT on an IC, in addition to a constant temperature chamber, power supply, etc., equipment such as an IC test device or a signal generator is required to supply logic signals to the IC under test. , which has the disadvantage of requiring extra capital investment.

In addition, in order to improve productivity, a large number of ICs to be tested are placed in a thermostatic chamber and BT is performed simultaneously, so printed circuit boards and wiring cables are used from the signal generator to the ICs to be tested.
There is a drawback that complicated and complicated signal distribution connections must be made.

[Means to solve the problem]

A semiconductor integrated circuit of the present invention has a function of testing a plurality of internal registers using serial scanning, and generates an inverted logical value of the logical value of the first register on the scan-in side of a scan path. a logic inversion circuit; a first selector circuit that selects either the output of the logic inversion circuit or a scan-in terminal and supplies it to the scan input of the first register on the scan-in side of the scan canvas; a clock generation circuit that generates an internal clock signal capable of operating a register; A state in which the output of the inversion circuit is selected, and the clock generation circuit is caused to generate the internal clock signal, and a state in which the first selector circuit is caused to select the scan-in terminal, and the clock generation circuit is caused to generate the internal clock signal. and an input terminal for a control signal for selecting a state in which the generation of the signal is stopped.

Further, the semiconductor integrated circuit of the present invention includes a clock output terminal that is externally connected to a clock input terminal that inputs a clock signal from the outside, and supplies the internal clock signal from the clock generation circuit to the clock input terminal. It may be composed of.

Furthermore, in the semiconductor integrated circuit of the present invention, when the control signal causes the clock generation circuit to generate the internal clock signal, the output of the clock generation circuit is selected, and the clock generation circuit does not generate the clock signal. The clock input terminal may be configured to include a second selector circuit that selects a clock input terminal 'to which a clock signal is inputted from the outside when in the state, and supplies the selected clock input terminal to the tarok inputs of the plurality of registers.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit 1 which is a first embodiment of the present invention.
FIG. 2 is a block diagram showing 0.

Registers 1, 2, and 3 are registers used in the internal circuit of the semiconductor integrated circuit 10, and normally perform the original logic function of the IC, but can be shifted by applying a scan mode control signal (not shown). They are connected in series like a register to perform a serial scan operation. FIG. 1 illustrates the connection state in scan mode. That is, registers 1, 2, and 3 constitute a shift register, and the scan output of register 3 is sent to the semiconductor integrated circuit 10.
It is output to the scan out terminal 14 of.

The output of the selector circuit 4 is connected to the scan input of the register 1.

The selector circuit 4 selects the scan-in terminal 13 when the logic value of the control signal (hereinafter referred to as control signal 11) applied to the control terminal 11 is "0", and selects the output of the logic inversion circuit 7 when the logic value is "1°". is selected and supplied to the scan input of the register 1.The scan output of the register 1 is branched and input to the logic inversion circuit 7, which inverts the output value of the register 1 and inputs it to the selector circuit 4.

The control signal 11 is input to the selector circuit 4 as well as to the clock generation circuit 6. The tarlock generating circuit 6 is an oscillator that does not generate a clock when the control signal 11 is "0", but generates a clock when it becomes "1°". The output of the clock generation circuit 6 is connected to a clock output terminal 15 of the semiconductor integrated circuit 10.

In the semiconductor integrated circuit 10 configured as above,
When performing BT, the tarlock output terminal 15 and the tarlock terminal 12 are connected outside the semiconductor integrated circuit 10, and a scan mode control signal is given to the semiconductor integrated circuit 10 to put the register group in a shift register state, and the control The signal 11 is set to a logic value of "1". The clock generation circuit 6 starts generating a tarok signal, which is supplied to the registers 1, 2.3 through external connections.

At this time, registers 1, 2, and 3 operate as shift registers, and the logical value in register 1 is propagated to register 2, and the logical value in register 2 is propagated to register 3 every clock. Here, the scan input of register 1 is sent to first selector circuit 4. Since it is connected to the scan output of the register 1 via the logic inversion circuit 7, the inverted logic value of the register 1 immediately before the clock input is set in the register 1 every clock. Therefore, register 1 contains 0
"" and "1" are set alternately every clock, and the operation of register 1 is transmitted to register 2 with a delay of one clock, and to register 3 with a delay of two clocks.

In this way, the logic values of registers 1, 2, and 3 repeatedly change between "0" and "1" every clock. Therefore, the internal logic circuit of the semiconductor integrated circuit 10 (Fig. (not shown) also performs a logical operation in conjunction with this, so the internal circuit can easily be operated logically without supplying clocks or logic signals to the semiconductor integrated circuit 10 from outside the BT constant temperature oven.

Therefore, the scan mode control signal input terminal (not shown)
A printed circuit board for BT is created in such a way that the logical setting value when implementing dynamic BT is added to the terminal position of the control terminal 11, and the clock output terminal 15 and the clock terminal 12 are connected. When the integrated circuit 10 is attached to this printed circuit board, placed in a constant temperature oven, and a power supply voltage is applied, the semiconductor integrated circuit 10 automatically starts logic operation, so special IC test equipment and equipment such as a signal generator are required. There is no need to prepare a
Dynamic BT can be easily performed without making complicated and complicated signal distribution connections.

In addition, when performing normal IC inspection, the control signal 11
By setting "0" to "0" and supplying a clock signal to the clock terminal 12, registers 1, 2, and 3 are
It is also possible to set an arbitrary logical value to , and to perform inspection using scan mode.

FIG. 2 shows a semiconductor integrated circuit 2 which is a second embodiment of the present invention.
FIG. 2 is a block diagram showing 0.

The connection relationships among the registers 1, 2, 3, selector circuit 4, logic inversion circuit 7, scan-in terminal 13, and scan-out terminal 14 of the semiconductor integrated circuit 20 are the same as those of the semiconductor integrated circuit 1.
0, however, the semiconductor integrated circuit 20 is provided with a selector circuit that the semiconductor integrated circuit 10 does not have.

The selector circuit 5 selects the clock terminal 12 of the semiconductor integrated circuit 20 when the control signal 11 is "O", and also selects the clock terminal 12 of the semiconductor integrated circuit 20 when the control signal 11 is "0".
1 and the output of the clock generation circuit 6 are selected and the tarok signal is supplied to the clock input terminals of the registers 1, 2.3. That is, when the control signal 11 is "0", the registers 1, 2, and 3 are operated by the clock signal applied from the outside to the clock terminal 12, and when the control signal 11 is "1°", the registers 1, 2, and 3 are operated by the internal clock signal generated by the tarock generating circuit 6. It operates based on the clock signal.

In the semiconductor integrated circuit 20 connected as described above, B
When performing T, a scan mode control signal is applied to the semiconductor integrated circuit 20 to put the register group into a shift register state, and the control signal 11 is set to a logic value "1". The clock signal generated by the clock generation circuit 6 is supplied to the registers 1, 2.3 through the selector circuit 5, and the inverted logic value of the register 1 itself is supplied to the scan input of the register 1. The same effect as the embodiment shown in the figure can be obtained.

The embodiment shown in FIG. 2 differs from the embodiment shown in FIG. 1 in that the selector circuit 5 intervenes in the internal clock distribution wiring section, so
Although the clock skew between ICs may increase,
This eliminates the need for external wiring to connect clock signals, making it easier to create a printed circuit board for BT, and saving IC terminals.

[Effects of the Invention] As explained above, according to the present invention, in an IC that serially scans and tests the logical values of registers in the IC, when performing BT, the clock generation circuit built in the IC outputs data to each register. By supplying a clock signal and applying its own inverted logic value as an input value to the register at the beginning of the serial scan path, a circuit configuration is adopted that repeats "0'" and "1" every clock. IC
Dynamic B can be performed without having to supply logic signals externally using dedicated IC test equipment or signal generators.
This method has the advantage that T can be easily performed, and the test can be performed economically without any extra equipment investment.

In addition, by providing a second selector circuit that selects the output of the clock generation circuit built into the IC or the clock input terminal, there is no need to connect the clock externally to the IC, so the design around the printed circuit board for BT can be improved. This has the effect that it is possible to further simplify the process and save the number of IC terminals.

5... Selector circuit, 6... Clock generation circuit, 7
...Logic inversion circuit, 10.20...Semiconductor integrated circuit, 11...Control terminal, 12...Tarlock terminal, 13
...Scan-in terminal, 14... Scan-out terminal, 15... Clock output terminal.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a function of testing a plurality of internal registers using serial scan, an inverted logical value of the logical value of the first register on the scan-in side of a scan path is generated. a logic inversion circuit; a first selector circuit that selects either an output of the logic inversion circuit or a scan-in terminal and supplies the selected one to the scan input of the register at the beginning of the scan-in side of the scan path;
a clock generation circuit that generates an internal clock signal capable of operating the plurality of registers; and the first selector circuit that is input to the selection control input of the first selector circuit and the generation control input of the clock generation circuit. selects the output of the logic inversion circuit, causes the clock generation circuit to generate the internal clock signal, causes the first selector circuit to select the scan-in terminal, and causes the clock generation circuit to generate the internal clock signal. 1. A semiconductor integrated circuit comprising: a control signal input terminal for selecting a state in which generation of an internal clock signal is stopped; 2. Claim 1, further comprising a clock output terminal that is externally connected to a clock input terminal that inputs a clock signal from the outside, and supplies the internal clock signal from the clock generation circuit to the clock input terminal.
The semiconductor integrated circuit described. 3. Select the output of the clock generation circuit when the clock generation circuit generates the internal clock signal according to the control signal, and select the output of the clock generation circuit from the outside when the clock generation circuit does not generate the clock signal. 2. The semiconductor integrated circuit according to claim 1, further comprising a second selector circuit that selects an input clock input terminal and supplies the selected clock input terminal to the clock inputs of the plurality of registers.