JP2000009807A - Semiconductor device tester and testing method in it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a signal to be inputted to a device to be tested to be more efficiently generated in a semiconductor device tester to test semiconductor devices such as ICs. SOLUTION: Test signal generating and determining parts 30, 40, and 50 generate timing signals for generating test signals to be inputted to a semiconductor device (DUT) 10, which is an object of test, output the generated timing signals to DUT interface parts 60, 70, and 80, and output the generated timing signals to a multiplexer 20. The multiplexer 20 outputs the timing signals generated by the test signal generating and judging parts 30, 40, and 50 to the DUT interface parts 60, 70, and 80 which are not connected to the test signal generating and judging parts 30, 40, and 50 at need. The DUT interface parts 60, 70, and 80 switch the output values of test signals to be outputted to the DUT 10 in synchronization with the inputted timing signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device test apparatus and a semiconductor device test apparatus, and more particularly, to a semiconductor test system and a semiconductor test apparatus for performing a test by inputting a predetermined signal to a semiconductor device to be tested. It is about.

[0002]

2. Description of the Related Art In recent years, in various fields, IC (Inte
The use of semiconductor devices such as a grated circuit (integrated circuit) has been remarkably advanced, and the production amount has been greatly increased. Generally, in a semiconductor device manufacturing process, a test is performed to determine whether or not the manufactured semiconductor device operates normally. This test has become indispensable as the importance of semiconductor devices has increased, and there has been a demand for a semiconductor device test apparatus capable of performing tests more efficiently.

FIG. 4 is a block diagram showing a schematic configuration of an IC test system 100 as an example of a conventional semiconductor device test apparatus. The IC test system 1 shown in FIG.
At 00, the test signal generation / determination units 121, 122,
The 123 generates a timing signal for performing a test under predetermined conditions, and outputs the generated timing signal to the DUT interface units 131, 132, and 133.

DUT interface units 131 and 13
2 and 133 generate a test signal based on the input timing signal, and generate a test target semiconductor device (hereinafter, referred to as a test target).
The test is executed by inputting the data to each input / output pin of the DUT 10. The DUT 10 performs a process based on the input test signal, and outputs a processing result to the DUT interface units 131, 132, and 133.

The DUT interface unit 13
1, 132, 133 are test signal generation / judgment units 121,
The processing results input from the DUT 10 are output to the test signal generation / determination units 121 and
2 and 123 determine the quality of the DUT 10 based on the output result.

In the IC test system 100, a test condition control device 124 for executing a test under predetermined conditions is provided. The test condition control device 124 includes test signal generation / judgment units 121 and 122. , 1
23. That is, when it is necessary to generate a complex test signal, the test signal generation / determination unit 1
If not all test signals can be generated by the test signals 21, 122 and 123, the test condition control device 124 generates test signals in an auxiliary manner so as to meet predetermined conditions, and Output.
Here, the multiplexer 110 is connected to the test signal control device 1.
The test signal input from the DUT 24 is transmitted to any appropriate DUT interface unit 131, 132, 133.
Output to UT interface.

[0007]

However, the IC test system 100 configured as described above has a problem that the circuit configuration tends to be complicated. That is, a test signal generation / judgment unit 121 for generating and inputting a test signal to each pin of the DUT 10 is provided.
When it is assumed that 122 and 123 have a function of easily processing a test signal to be input to each pin, the test signal generation / determination units 121, 122 and 123 need to be very sophisticated. Test signal generation / judgment units 121 and 12
There has been a problem that the size of 2,123 is increased and the cost is increased.

Therefore, in the above IC test system 100, the test condition control device 124 and the multiplexer 1
And test signal generation / judgment units 121 and 12
2 and 123, but the test condition control device 124
And multiplexer 110,
DUT 10 and DUT interface units 131, 1
There has been a problem that the configuration of the circuits around 32 and 133 is complicated, which increases the cost and impairs the degree of freedom in design.

[0009] In order to solve the above problems, an object of the present invention is to provide a semiconductor device test apparatus for testing a semiconductor device such as an IC so that a signal to be input to a device under test can be generated more efficiently. It is.

[0010]

In order to solve the above problems, the invention according to claim 1 includes a plurality of test means for generating and outputting a test signal for testing a device under test; Test control means for causing the device under test to execute processing based on the test signal output by the test means; and output from the device under test by causing the device under test to execute processing by the test control means. And a pass / fail determination unit for determining pass / fail of the device under test based on the processing result to be performed. In the semiconductor device test apparatus, the test unit generates a timing signal at a predetermined timing. When,
A test signal generation unit that generates and outputs the test signal based on the timing signal generated by the timing signal generation unit, and a timing signal generated by the timing signal generation unit is included in another test unit. And a timing signal control means for inputting to the test signal generation means.

According to the first aspect of the present invention, a test signal for testing a device under test is generated and output by the plurality of test means, and the test signal is output by the test means by the test control means. The device under test executes the processing based on the test signal obtained, and the test control unit executes the process based on the processing result output from the device under test. In a semiconductor device test apparatus for judging pass / fail of a test device, a test means generates a timing signal at a predetermined timing by a timing signal generation means, and outputs a timing signal generated by the timing signal generation means by the test signal generation means. A test signal is generated and output based on the timing, and the timing signal is generated by the timing signal control means. The timing signal generated by the means, is inputted to the test signal generating means having the other test means.

Therefore, in the semiconductor device test apparatus, the timing signal generated by the timing signal generation means can be input to another test means. Even when a complicated signal that cannot be generated can be handled by using the timing signal generating means included in another test means. For example, when two timing signal generation units are provided in the test unit, and when it is necessary to generate a timing signal three times in succession, the timing signal generation unit included in the other test units may generate one. This can be achieved by generating timing signals for the second time. As a result, even if the circuit configuration is downsized, a complicated test signal can be generated, thereby realizing the downsizing and simplification of the circuit configuration, and enabling a more flexible design.
The cost can be greatly reduced.

According to a second aspect of the present invention, in the semiconductor device test apparatus according to the first aspect, the testing means includes a plurality of the timing signal generating means and a plurality of the test signal generating means, respectively, and the testing means has The timing signal control means inputs the timing signal generated by the timing signal generation means not used in the test means to the test signal generation means of another test means. The configuration was adopted.

According to the second aspect of the present invention, the test means includes a plurality of timing signal generation means and a plurality of test signal generation means, and the timing signal control means of the test means is used in the test means. The timing signal generated by the timing signal generating means
The signal is input to the test signal generation means of another test means.

Therefore, when a timing signal is input to another test means, the timing signal generated by the unused timing signal generation means is input by the timing signal control means, so that the timing generation means is more efficiently used. Can be used, the efficiency of the circuit configuration can be further improved, and the miniaturization and simplification can be realized.

The third aspect of the present invention is the first or second aspect.
In the semiconductor device test apparatus described in the above, the test signal generation means of the test means outputs a binary signal as the test signal, and synchronizes the test signal with the timing signal generated by the timing signal generation means. And the output value is switched and output.

According to the third aspect of the present invention, the test signal generation means of the test means outputs a binary signal as a test signal, and synchronizes the test signal with the timing signal generated by the timing signal generation means. The signal output value is switched and output.

Therefore, the test signal can be more efficiently and simply controlled by the timing signal generated by the timing signal generator, so that the timing signal generator of another test unit can be easily used. This makes it possible to more effectively utilize the components provided in the semiconductor device test apparatus and to improve efficiency.

According to a fourth aspect of the present invention, there are provided a plurality of test means for generating and outputting a test signal for testing a device under test, and a test signal output from the test means. A test control unit for causing the device under test to execute a process, and a processing result output from the device under test by causing the device under test to execute the process by the test control unit, based on a processing result output from the device under test. A semiconductor device test apparatus, comprising: a timing determination unit configured to generate a timing signal at a predetermined timing, wherein the timing signal is generated based on the generated timing signal. A test signal is generated and output, and the generated timing signal is output to another test means, and the timing signal is output. Thereby generate the test signal based on, it is characterized in.

Therefore, in the semiconductor device test apparatus, the timing signal generated by the test means can be input to another test means. Therefore, even when a complicated signal is generated by the test means, the other test means can be used. Can be dealt with by using the timing signal generated in. For example, a test means capable of generating a timing signal twice in succession cannot generate a timing signal three times in a row, but if another test means generates a timing signal once more, , Can respond. As a result, a complicated test signal can be generated even if the circuit configuration is downsized, so that the circuit configuration can be downsized and simplified, so that more free design is possible and the cost can be greatly reduced. It is.

According to a fifth aspect of the present invention, there is provided the test method in the semiconductor device test apparatus according to the fourth aspect, wherein the test means switches an output value as the test signal in synchronization with the timing signal. It outputs a value signal.

Therefore, the test signal can be more efficiently and simply controlled by the timing signal.
The timing signal can be controlled by easily using other test means, and each unit included in the semiconductor device test apparatus can be more effectively used to improve efficiency.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An IC test system 1 according to an embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a schematic configuration of the IC test system 1. As shown in FIG. 1, the IC test system 1 includes a multiplexer 20, test signal generation / determination units 30, 40, 50, a DUT. Interface unit 60,
The DUT 10 is configured by these components.

Test signal generation / judgment units 30, 40, 50
Are the DUT interface units 60, 70, and 8, respectively.
0, and is connected to the multiplexer 20 to generate a signal for testing the DUT 10 and output it to the DUT interface units 60, 70, 80, and output the signal to the multiplexer 20. Also, D
The processing is executed by the UT 10, and the processing result indicating the result of the processing is transmitted to the DUT interface units 60, 70, and 8.
0, the test signal generation / determination unit 30,
40 and 50 determine whether the DUT 10 is a non-defective product or a defective product that performs an abnormal operation based on the processing result.

The multiplexer 20 converts a signal input from the test signal generation / judgment unit 30, 40, 50 into a DUT interface unit 60 according to the operation state of the test signal generation / judgment unit 30, 40, 50 at that time. , 70, 80. For example, the signal to be generated by the test signal generation / judgment unit 30 is a complicated signal, and the test signal generation / judgment unit 30 cannot completely generate the signal to be output to the connected DUT interface unit 60. In this case, the signal generated by another test signal generation / determination unit 40 or test signal generation / determination unit 50 is
The data is input to the DUT interface unit 60 via the multiplexer 20. Thereby, even when the function of the test signal generation / judgment units 30, 40, 50 cannot cope with the generation of complicated signals, the DUT interface units 60, 7
A predetermined signal is reliably input to 0 and 80.

DUT interface units 60, 70, 8
0 is a DUT based on the signals input from the test signal generation / determination units 30, 40, 50 and the multiplexer 20.
10 to generate a test signal for performing the test,
Output for 0. The DUT interface units 60, 70, and 80 execute processing based on the test signal by the DUT 10, and when the processing result is input from the DUT 10, the processing result is transmitted to the test signal generation / determination units 30 and 4.
Output for 0,50.

FIG. 2 is a diagram showing the configuration of each part of the IC test system 1 shown in FIG. 1 in more detail. Also, FIG.
4 is a timing chart showing an example of test signals 62a and 72a input to the DUT 10 in the IC test system 1. Hereinafter, the configuration and operation of each unit of the IC test system 1 will be described in detail with reference to FIGS. 2, the illustration and description of the test signal generation / judgment unit 50 and the DUT interface unit 80 among the units of the IC test system 1 shown in FIG. 1 are omitted for convenience of description.

As shown in FIG. 2, the test signal generation / judgment unit 30 includes two timing signal generators 31 and 32 therein. The timing signal generators 31, 32
DUT is connected to the UT interface unit 60 and to the multiplexer 20 respectively.
The timing signals 31a and 32a are respectively generated at preset timings for testing the UT 10, and the DUTs are generated.
These are output to the interface unit 60 and the multiplexer 20. Similarly, the test signal generation / judgment unit 40 includes timing signal generators 41 and 42 connected to the DUT interface unit 70 and the multiplexer 20, and the timing signal generators 41 and 42.
Generates timing signals 41 a and 42 a at a predetermined timing, and outputs them to the DUT interface unit 70 and the multiplexer 20. The timing signal generators 31, 32, 41, and 42 execute operations independently of each other, and generate timing signals 31a, 32a, and 41, respectively.
a, 42a can be output.

The test signal generation / judgment units 30 and 40
Is provided with a pass / fail judgment circuit (not shown) for judging pass / fail of the DUT 10 based on a process result output from the DUT 10 by a process described later. The results of testing the DUT 10 are determined.

The pass / fail judgment circuit (not shown) includes:
It is not always necessary to provide the test signal generation / judgment units 30 and 40 inside the test signal generation / judgment units 30 and 40.
0, a pass / fail judgment circuit is connected to the outside, and the processing result output from the DUT 10 is output to the DUT interface units 60 and 70.
The processing result may be output from the test signal generation / judgment units 30 and 40 to the pass / fail judgment circuit when input to the test signal generation / judgment units 30 and 40 via A control device provided with the pass / fail judgment circuit is connected to the test signal generation / judgment units 30 and 40, and the control device controls the timing signals 31a, 32a, 41a and 42a in the test signal generation / judgment units 30 and 40. The timing of generation and other control may be performed together with the quality judgment of the DUT 10.

The multiplexer 20 includes a distribution control circuit 21
And AND gates 22, 23, 24 and 25 therein. The distribution control circuit 21 connects its output terminal to:
Connected to AND gates 22, 23, 24, and 25, and directed to AND gates 22, 23, 24, and 25 according to an instruction from an input device or a control device (not shown).
It outputs distribution signals 21a, 21b, 21c, 21d.
The distribution signals 21a, 21b, 21c, 21d are signals for operating a specific one of the AND gates 22, 23, 24, 25 to be used. , 24, and 25 are output from distribution control circuit 21 to distribution signals 21a, 21b, 21c,
The operation is performed only when 21d is input.

The AND gate 22 has two input terminals and 1
A logic circuit element having two output terminals and outputting from the output terminals only when equal inputs are made from two input terminals. The input terminal on one side of the AND gate 22 includes:
Timing signal generator 3 in test signal generation / judgment unit 30
When the timing signal 31 a is output from the timing signal generator 31, the timing signal 31 a is input to the AND gate 22. The other input terminal of the AND gate 22 is
It is connected to the output side terminal of the distribution control circuit 21. The output terminal of the AND gate 22 is connected to the DUT interface unit 70. And AND gate 2
When the timing signal 31a output from the timing signal generator 31 and the distribution signal 21a output from the distribution control circuit 21 are simultaneously input to the AND gate 22, the AND gate 22 outputs the auxiliary timing signal 22a to the DUT interface. Output to the unit 70.

Similarly, the input terminal of the AND gate 23 is
The distribution control circuit 21 is connected to the timing signal generator 32 in the test signal generation / judgment unit 30, and
The output terminal of the gate 23 is the DUT interface unit 70
And the timing signal 32a and the distribution signal 2
1b, the auxiliary timing signal 23a is output to the DUT interface unit 70.

The AND gates 24 and 25 have the same configuration as the AND gates 22 and 23, and
4 are connected to the timing signal generator 41 in the test signal generation / judgment unit 40 and the distribution control circuit 21, respectively. The output terminal of the AND gate 24 is connected to the DUT
The timing signal 41a output from the timing signal generator 41 is connected to the interface unit 60.
The auxiliary timing signal 24a is output to the DUT interface unit 60 only when the distribution control circuit 21 and the distribution signal 21c output from the distribution control circuit 21 are simultaneously input.
The input terminal of the AND gate 25 is connected to the output terminal of the timing signal generator 42 in the test signal generation / determination unit 40 and the distribution control circuit 21, and the output terminal is connected to the DUT interface unit 60. Signal 4
The auxiliary timing signal 25a is output only when 2a and the distribution signal 21d are input simultaneously.

The DUT interface unit 60 has a formatter 61 and a driver 62 inside, and the DUT interface unit 70 also has a formatter 7 inside.
1 and a driver 72.

The formatter 61 has one terminal connected to the timing signal generator 3 in the test signal generator / determiner 30.
1, 32 and AND gate 2 in multiplexer 20
The terminals on the other side of the formatter 61 are connected to a driver 62. For the formatter 61, the timing signal generators 31, 3
When any of the timing signals 31a and 32a output from the second and the auxiliary timing signals 24a and 25a output from the AND gates 24 and 25 are input, the formatter 61 outputs the test signal to the driver 62. The output of is inverted.

Similarly, the formatter 71 has one terminal connected to the timing signal generators 41 and 42 in the test signal generation / judgment unit 40 and the AND gates 22 and 23 in the multiplexer 20, and the other terminal connected to the other terminal. Driver 72
When one of the timing signals 41a and 42a or the auxiliary timing signals 24a and 25a is input, the test signal output to the driver 72 is inverted.

The formatters 61 and 71 can output a test signal having two output levels of “Lo” level or “Hi” level to the drivers 62 and 72 when the operation of the IC test system 1 starts. It is. Therefore, while the signal of the preset level is being output, the timing signals 31a, 32a, 41a input from the timing signal generators 31, 32, 41, 42 in the test signal generation / determination units 30, 40 are provided. , 42a, or AND gates 22, 23, 24,
Auxiliary timing signals 22a and 23 input from
a, 24a, 25a, the output level of the test signal is changed from the “Hi” level to the “Lo” level.
Level, or switching from 'Lo' level to 'Hi' level for output. As a result, the DUT 10 has two test signals of “Hi” level and “Lo” level.
A test signal that takes a value can be generated and output, and a test of the DUT 10 that operates according to the input of a digital signal can be performed.

The driver 62 has one terminal connected to the formatter 61 and the other terminal connected to the input / output pin 11 of the DUT 10. When a test signal is input from the formatter 61, the driver 62 outputs the test signal. The test signal 62a is generated by amplifying the intensity, and the input / output pin 11 of the DUT 10 is
Output a test signal 62a. Similarly, the driver 72 has one terminal connected to the formatter 71 and the other terminal connected to the input / output pin 12 of the DUT 10. The driver 72 amplifies a test signal input from the formatter 71 and converts the test signal 72 a into a signal. It is generated and output to the input / output pin 12 of the DUT 10.

The DUT 10 is a semiconductor device to be tested.
When the test signals 62a and 72a are input to the test signals 1 and 12, processing is executed based on the test signals 62a and 72a, and the processing results of the processing are output from the input / output pins 11 and 12. D
Processing results output from the input / output pins 11 and 12 of the UT 10 are output to the formatters 61 and
The test signal generation / judgment units 30 and 4
Input to 0. Then, the pass / fail judgment circuit (not shown) judges pass / fail of the DUT 10. In addition,
When the DUT 10 further includes input / output pins in addition to the input / output pins 11 and 12, the processing result may be output from input / output pins other than the input / output pins 11 and 12.

In the IC test system 1 configured as described above, when the operation is started, first, the timing signal generator 3 inside the test signal generation / judgment units 30 and 40 is started.
At 1, 32, 41 and 42, timing signals 31a, 32a, 41a and 42a are generated at a predetermined timing.

The timing signals 31a, 31a,
When the signals 32a, 41a and 42a are input to the formatters 61 and 71, the output of the test signal output from the formatters 61 and 71 is inverted, and the inverted test signals are input to the drivers 62 and 72. The drivers 62 and 72 amplify the intensity of the test signals input from the formatters 61 and 71 to amplify the test signals 62 a and 7.
2a is generated, and the test signals 62a and 72a are
0 is input to the input / output pins 11 and 12.

Then, in the DUT 10, the test signal 6
2a, 72a, processing results are output from the input / output pins 11, 12, and the drivers 62, 72
Is input to The processing results input to the drivers 62 and 72 are output to the formatters 61 and 71, and the formatters 61 and 71 further output the test signal generation / determination units 30, 4
Output for 0. Then, the pass / fail judgment circuit (not shown) included in the test signal generation / judgment sections 30 and 40 judges pass / fail of the DUT 10.

FIG. 3 is a timing chart showing an example of a test signal input to the DUT 10. As shown in FIG. 3A, the test signal input to the DUT 10 is 'Lo'
This signal takes binary output of the level and the 'Hi' level.

The signal shown in FIG. 3A is initially output at the “Lo” level to the DUT 10, and thereafter, at time t3
Rises to 'Hi' level. The inversion of the output at time t3 is based on the timing signals 31a, 32a, 41a,
42a or auxiliary timing signals 22a, 23a, 24
a and 25a. That is, the formatters 61 and 71 output the timing signals 31a, 32a and 4
1a, 42a and auxiliary timing signals 22a, 23
a, 24a, 25a, the level of the test signal output to the drivers 62, 72 is inverted, and the 'Lo' level is switched to the 'Hi' level, or Switch 'Hi' level to 'Lo' level.

The test signal shown in FIG. 3B is output at the "Lo" level until time t1, and at the time t1, the signal is "Hi".
Level, and then at time t2, 'L
Fall to o 'level. Further, at time t4, the signal rises to the “Hi” level again and is output. Here, the case where the test signal shown in FIG. 3B is input from the driver 62 to the input / output pin 11 of the DUT 10 will be described as an example. In the formatter 61, the time t1 and the time t2
At time t4, the output level is inverted. Therefore, the timing signal input to the formatter 61 needs to be input three times at times t1, t2, and t4.

As described above, the two timing signal generators for outputting the timing signal to the formatter 61 are the timing signal generators 31 and 32. Of these, the timing signal generator 31 generates and outputs the timing signal 31a at time t1. At time t2, the timing signal generator 32 generates and outputs the timing signal 32a. At time t4, Again, the timing signal needs to be generated by any of the timing signal generators. However, usually, the timing signal generator 3
It is difficult to perform the operations a plurality of times during the series of test signals input to the DUT 10 in the timing signal generators 31, 32, 41, and 42.
Cannot be operated twice.

Here, considering the case where the timing signal generator 42 in the test signal generation / judgment unit 40 is not operating, at time t4, the timing signal generator 42 generates and outputs the timing signal 42a. When the output timing signal 42a is input to the AND gate 25 and the distribution control circuit 21 outputs the distribution signal 21d to the AND gate 25, the auxiliary timing signal 25a is output from the AND gate 25 and the formatter 61 is input. Thus, at time t4, the formatters 61 and 71 execute the third switching in synchronization with the auxiliary timing signal 25a, generate the test signal 62a having the waveform shown in FIG.
10 can be entered.

Subsequently, the test signal 62a having the waveform shown in FIG. 3A is input to the input / output pin 11 of the DUT 10, and at the same time, the test signal 72a having the waveform shown in FIG.
An example of inputting to the input / output pin 12 of T10 is an IC
The operation of the test system 1 will be described.

First, at time t1, the test signal generation /
The timing signal 41a is generated by the timing signal generator 41 in the judging unit 40, is input to the formatter 71, and the input level of the test signal input from the formatter 71 to the driver 72 is changed from 'Lo' level to 'Hi' level. At the rise, the output level of the test signal 72a is inverted. Subsequently, at time t2, the timing signal 42a is generated by the timing signal generator 42 and input to the formatter 71, and the input level of the test signal input to the driver 72 falls from the "Hi" level to the "Lo" level. , The output level of the test signal 72a is inverted.

At time t3, the timing signal 31a is generated and output by the timing signal generator 31 in the test signal generation / judgment unit 30, and is input to the formatter 61.
2 rises from the “Lo” level to the “Hi” level, and the output level of the test signal 62 a output from the driver 62 is inverted.

At time t4, the timing signal 32a is generated and output by the timing signal generator 32 in the test signal generation / determination section 30, and the timing signal 32a is input to the AND gate 23. At the same time, the distribution control circuit 21 controls the distribution signal 21b.
Is output to the AND gate 23, and the AND gate 2
3 outputs an auxiliary timing signal 23a. The auxiliary timing signal 23a is input to the formatter 71, the input level of the test signal input from the formatter 71 to the driver 72 rises from the “Lo” level to the “Hi” level, and the output level of the test signal 72a output from the driver 72 Is inverted.

By the above series of operations, test signals requiring three or more output level inversions are generated by the test signal generation / judgment units 30 and 40 having two timing signal generators and input to the DUT 10. Test.

As described above, according to the IC test system 1 according to the embodiment of the present invention, the timing signal generators 31 and 32 in the test signal generation / judgment units 30 and 40 are used.
At 41 and 42, timing signals 31a, 32a, 41a and 42a are generated and output at predetermined timings,
Each time the timing signals 31a, 32a, 41a, 42a are input, the DUT interface units 60, 70, 80
In the formatters 61 and 71, the driver 62,
The driver 62 and 72 invert the output level of the signal to be output to the
The test signals 62a and 72a are generated by amplifying the intensity of the signals output from the DUT 10 and the input / output pin 1 of the DUT 10.
1 and 12, and based on the test signals 62a and 72a, the quality of the DUT 10 is determined based on the processing result obtained by causing the DUT 10 to execute the processing.

The timing signal generators 31, 3
Timing signal 31 generated in 2, 41, 42
a, 32a, 41a, and 42a are input to the AND gates 22, 23, 24, and 25 in the multiplexer 20, and output from the distribution control circuit 21.
1a, 21b, 21c, and 21d receive the auxiliary timing signal 2 from the AND gates 22, 23, 24, and 25.
2a, 23a, 24a and 25a are output and input to the formatters 61 and 71. Thus, in the formatter 61, the connected timing signal generator 3
1, 32 generated by the timing signals 31a, 32
In addition to a, the output is performed based on the auxiliary timing signals 24a and 25a output from the AND gates 24 and 25 in the multiplexer 20 based on the timing signals 41a and 42a generated by the timing signal generators 41 and 42. The output level of the signal can be inverted.

Therefore, it is necessary to input a more complicated signal to the DUT 10, and even if this signal cannot be generated only by the connected timing signal generators 31, 32, it is used. No other timing signal generators 41 and 42 in the test signal generation / judgment unit 40
Can be handled by using any one of the above. For this reason, in the IC test system 1, it is not necessary to install a large number of large-sized and high-cost devices in order to cope with a complicated signal, and the IC test system 1 can be realized with an inexpensive and relatively simple circuit configuration.

In the above embodiment, D
The pass / fail judgment circuit (not shown) of the test signal generation / judgment unit 30, 40, 50 judges the pass / fail of the DUT 10 based on the processing result obtained by performing processing based on the input test signal by the UT 10. However, the present invention is not limited to this, and a pass / fail determination device for determining pass / fail of the DUT 10 based on a processing result output from the DUT 10 is provided by each unit of the IC test system 1 described above. It is good also as a structure provided as another body.

The configuration of the pins of the DUT 10 and the like are also arbitrary, and it goes without saying that the specific detailed structure and the like can be appropriately changed.

[0060]

According to the first aspect of the present invention, in the semiconductor device test apparatus, the timing signal generated by the timing signal generating means can be input to another test means. When a complicated signal that cannot be handled by the timing signal generating means provided in the means is generated, it can be handled by using the timing signal generating means of the other testing means. For example, when two timing signal generation units are provided in the test unit, and when it is necessary to generate a timing signal three times in succession, the timing signal generation unit included in the other test units may generate one. This can be achieved by generating timing signals for the second time. As a result, a complicated test signal can be generated even if the circuit configuration is downsized, so that the circuit configuration can be downsized and simplified, so that more free design is possible and the cost can be greatly reduced. It is.

According to the second aspect of the invention, when a timing signal is input to another test means, the timing signal generated by the unused timing signal generation means is input by the timing signal control means. Therefore, the timing generation means can be used more efficiently, the efficiency of the circuit configuration can be further improved, and downsizing and simplification can be realized.

According to the third aspect of the present invention, the test signal can be more efficiently and simply controlled by the timing signal generated by the timing signal generator. The means can be easily used, and each unit included in the semiconductor device test apparatus can be used more effectively, and efficiency can be improved.

According to the fourth aspect of the present invention, in the semiconductor device test apparatus, since the timing signal generated by the test means can be input to another test means, a complicated signal is generated by the test means. In this case, it is possible to cope with the situation by using a timing signal generated by another test means. For example, a test means capable of generating a timing signal twice in succession cannot generate a timing signal three times in a row, but if another test means generates a timing signal once more, , Can respond. As a result, a complicated test signal can be generated even if the circuit configuration is downsized, so that the circuit configuration can be downsized and simplified, so that more free design is possible and the cost can be greatly reduced. It is.

According to the fifth aspect of the present invention, the test signal can be more efficiently and simply controlled by the timing signal, so that the timing signal can be controlled easily by using other test means. This makes it possible to more efficiently use the components provided in the semiconductor device test apparatus and to improve the efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an IC test system as an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of the IC test system shown in FIG. 1 in detail.

FIG. 3 is a timing chart showing an example of a test signal generated in the IC test system shown in FIGS. 1 and 2;

FIG. 4 is a block diagram showing a schematic configuration of an IC test system as an example of a conventional semiconductor device test apparatus.

[Description of Signs] 1 IC test system 10 DUT (device under test) 11, 12 I / O pins 20 Multiplexer 21 Distribution control circuit 22, 23, 24, 25 AND gate 30, 40, 50 Test signal generation / judgment unit 31, 32, 41, 42 Timing signal generator 60, 70, 80 DUT interface unit 61, 71 Formatter 62, 72 Driver

Claims (5)

[Claims] A plurality of test means for generating and outputting a test signal for performing a test of a device under test to be tested; and Test control means for executing a process; and pass / fail determining the pass / fail of the device under test based on a processing result output from the device under test by causing the device under test to execute the process by the test control means. A semiconductor device test apparatus, comprising: a timing signal generating unit configured to generate a timing signal at a predetermined timing; and a test unit configured to perform the test based on the timing signal generated by the timing signal generating unit. Test signal generating means for generating and outputting a signal; and a timing signal generated by the timing signal generating means. And a timing signal control means for inputting the test signal to the test signal generation means of the other test means. 2. The test means comprises a plurality of the timing signal generating means and a plurality of the test signal generating means, respectively.
2. The semiconductor device according to claim 1, wherein the timing signal generated by the timing signal generation unit not used in the test unit is input to the test signal generation unit of another test unit. 3. Testing equipment. 3. The test signal generation means of the test means outputs a binary signal as the test signal, and outputs a test signal output value in synchronization with the timing signal generated by the timing signal generation means. The semiconductor device test apparatus according to claim 1, wherein the output is switched. 4. A plurality of test means for generating and outputting a test signal for performing a test of a device under test as a test object, and a plurality of test means for generating a test signal based on the test signal output by the test means. Test control means for executing a process; and pass / fail determining the pass / fail of the device under test based on a processing result output from the device under test by causing the device under test to execute the process by the test control means. A test method for a semiconductor device test apparatus, comprising: a determination means; and a timing signal generated at a predetermined timing, wherein the test signal is generated based on the generated timing signal. And outputting the generated timing signal to the other test means, based on the timing signal. A test method in a semiconductor device test apparatus. 5. The semiconductor device test apparatus according to claim 4, wherein the test means outputs a binary signal whose output value is switched in synchronization with the timing signal, as the test signal. Test method.