JP2838459B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device and, more particularly, to an integrated circuit device capable of performing a connection test inside and between integrated circuit devices.

[0002]

2. Description of the Related Art Recent advances in surface mounting technology have made it difficult to perform printed circuit boards (mainly in-circuit tests). The in-circuit test is to test the board by mounting the chips on the board, crimping the back surface of the board with spring-loaded probes arranged at intervals of several mm, and testing all the chips individually. It is. However, recent advances in surface mounting technology have made it impossible to set up probes on chip terminals,
There is a problem that the cost is too high when the jig is created.

In order to solve such a problem, a board-level test design has been standardized by IEEE.
This is an extension of the scan design conventionally used for facilitating the test inside the chip to the board level, and is described in IEEE std. 1149.1-1990.

FIG. 5 is a block diagram of a test circuit configured by the boundary scan design disclosed in the above-mentioned document.

[0005] The test circuit shown in FIG. This test circuit includes a plurality of chips 2, a shift path 6, a system signal line 7, a system data input / output terminal 8,
It includes a scan input terminal 9, a scan output terminal 10, a terminal TMS for specifying a test mode, and a terminal TCK for inputting a test clock signal.

System signal line 7 normally transmits system data. That is, the system data is supplied to the chip 2 and the output data of the chip 2 is supplied to another chip or the data input / output terminal 8. The data input / output terminal 8 is provided at the edge of the board 1 to input data from the outside and output data from the chip 2 to the outside.

The scan input terminal 9 inputs test data from the outside to the shift path 6. Scan output terminal 1
0 outputs the test result propagated through the shift path 6 to the outside.

Each chip 2 has an internal logic circuit 3, a data input / output terminal 4 for inputting / outputting data between chips, and a plurality of chips 2 connected between the data input / output terminal 4 and the internal logic circuit 3. , And a control circuit 16 for controlling the boundary scan register 15.

The control circuit 16 includes a test mode signal TMS,
And controls the boundary scan register 15 in response to the clock signal TCK. The test control signal includes a mode signal M, a shift / load signal SL, a clock signal CKA, and a clock signal CKB described later.
By combining these signals, a signal for connecting the scan input terminal 9 and the scan output terminal 10 by completing the shift path 6 and for connecting the data input / output terminal 4 and the internal logic circuit 3 are provided. Create a control signal and so on.

The internal logic circuit 3 processes the data supplied through the boundary scan register 15 and outputs the processed data to the data input / output terminal 4 via the boundary scan register 15.

Each boundary scan register 15 is controlled by a control circuit 16 to complete the shift path 6, connect the data input / output terminal 4 to the internal logic circuit 3, and the like. Upon completion of the shift path 6, test data is propagated to each shift register 15. By connecting the data input / output terminal 4 and the internal logic circuit 3, test data is supplied to the internal logic circuit 3, and data processed by the internal logic circuit 3 is supplied to the shift path 6. Shift path 6
Transmits the given data to the scan output terminal 10.

Thus, the test of the internal logic circuit 3 can be executed.

In the test of the system signal line 7, test data is propagated from the boundary scan register 15 connected to the output terminal of one chip to the boundary scan register 15 connected to the input terminal of the other chip. It can be done by doing.

As described above, a specific chip on the board 1 can be directly accessed from the scan input terminal 9 provided at the edge of the board 1. Therefore, the chip on the board can be tested without using an expensive tester (in-circuit tester).

FIG. 6 is a circuit diagram of the boundary scan register 15 shown in FIG. In FIG. 6, the boundary scan register 15 has control terminals M, SL, CKA, and CK.
B, a data input terminal DI, a data output terminal DO,
A scan input terminal SI, a scan output terminal SO,
The circuit includes selector circuits 11 and 12 having one input and one output, and flip-flop circuits 13 and 14.

The symbols of the control terminals correspond to the names of input / output signals. That is, the control signal M inputs the mode signal M. The control terminal SL receives the shift / load signal SL. The control terminal CKA is connected to the clock signal C
Enter KA. The control terminal CKB is a clock signal CKB.
Enter

The data input terminal DI is connected to the data input terminal 4
Alternatively, it is connected to the output of the internal logic circuit 3, and the data output terminal DO is connected to the data input terminal 4 or the input of the internal logic circuit 3. Scan input terminal SI receives test data from adjacent boundary scan register 15. The scan output terminal SO outputs test data to an adjacent boundary scan register.

The selector circuit 11 outputs a shift / load signal S
Select the data input terminal DI or the scan input terminal SI in response to the input terminal I of the flip-flop circuit 13.
Give to D. The flip-flop circuit 13 updates the held data to the data from the selector circuit 11 in response to the clock signal CKA, and supplies the updated data to the scan output terminal SO and the terminal ID of the flip-flop circuit 14. The flip-flop circuit 14 updates the held data in response to the clock signal CKB and supplies the updated data to the selector circuit 12. The selector circuit 12 has one input terminal connected to the data input terminal DI, the other input terminal connected to the output of the flip-flop circuit 14, and the output terminal connected to the data output terminal DO. Selector circuit 12
Selects data from the flip-flop circuit 14 in response to the mode signal M "1", and selects data from the data input terminal DI in response to the mode signal M "0".

In operation, the boundary scan register 15 shifts test data, supplies test data,
Import test results.

First, the shift operation is performed by a shift / load signal SL.
Is set to “1”, and the clock signal CKA is supplied to the flip-flop circuit 13. The selector 12 selects the scan input terminal SI in response to the shift / load signal SL and supplies the same to the flip-flop circuit 13. The flip-flop circuit 13 outputs the clock signal CKA
To the scan output terminal SO. In this way, the test data is propagated to the boundary scan register 15 connected in series.

Next, test data is supplied by setting the mode signal M to "1" and supplying the clock signal CKB to the flip-flop circuit 14. Then, the flip-flop circuit 14 updates the held data to the test data from the flip-flop circuit 13, and the selector circuit 12 outputs the test data updated from the flip-flop circuit 14 to the data output terminal DO. Thereby, data can be given to the internal logic circuit 3.

The test result is taken in by setting the shift / load signal SL to "0" and supplying the clock signal CKA. That is, the shift of “0” /
In response to the load signal SL, the selector circuit 11 selects the data input terminal DI and supplies the data input to this terminal to the flip-flop circuit 13. Flip-flop circuit 13 takes in output data of selector circuit 11 in response to clock signal CKA. This captured data is
Scan output terminal 10 of board 1 through shift path 6
Is propagated to

In the normal operation, the mode signal M is set to "0".
And the selector circuit 12 selects the data input terminal DI. By doing so, the boundary scan register 15 operates as a mere driver.

FIG. 7 is a circuit diagram showing details of a portion shown by a broken line in FIG. 7, a thick solid line 61 is a propagation path of test data in a shift operation, a double line 62 is a propagation path of test data in a test data supply operation, and a dashed line 63 is test data in a test data capture operation. This is the propagation path. Also, 4I
Is a data input terminal of the chip 2, and 40 is a chip 2
Is a data output terminal.

An operation test of the internal logic circuit 3 will be described with reference to FIG. First, the shift / load signal SL is set to “1”.
And the clock signal CKA is applied to the boundary scan register 15. Thus, a shift path between the scan input terminal 9 and the scan output terminal 10 is completed.

The test data input to the scan input terminal 9 of the board 1 is held in the flip-flop circuit 13a of the desired boundary scan register 15a.

Next, the mode signal M is set to "1" and the clock signal CKB is set to the boundary scan register 15a.
To supply. Thus, a path 62 for supplying test data to the internal logic circuit 3 is formed. The internal logic circuit 3 processes the data supplied through the path 62 and supplies the processed data to the boundary scan register 15b connected to the data output terminal 4.

Next, the shift / load signal SL is set to "0", and the clock signal CKA is applied to the boundary scan register 15b. As a result, a path 63 for taking in the test result is formed, and the test result is held in the flip-flop circuit 13b.

The test results captured as described above are supplied to the scan output terminal 10 of the board 1 via the test path 6. Based on this result, the internal logic circuit 3
Can be determined.

FIG. 8 is a circuit diagram showing details of a portion surrounded by a chain line in FIG.

Referring to FIG. 7, the connection test operation of system signal line 7 will be described.

The shift / load signal SL is set to "1", and the clock signal CKA is applied to the boundary scan register 15. Thereby, a shift path is formed between the scan input terminal 9 of the board 1 and the boundary scan register 15c, and the test data is held in the flip-flop circuit 13c.

Next, the mode signal M is set to "1" and the clock signal CKB is supplied. As a result, a path 62 for supplying test data is formed, and the test data is provided to the boundary scan register 15d via the data output terminal 40-system signal line 7-data input terminal 4I.

Next, the shift / load signal SL is set to "0" and the clock signal CKA is applied to the boundary scan register 15d. Thereby, a test result taking path 63 is formed, and the test result is taken into the flip-flop circuit 13d. The acquired test result is transferred to the scan output terminal 1 of the board 1 by the shift operation.
Propagated to 0. Based on the transmitted test results, the quality of the system signal line can be determined.

[0035]

The boundary scan register 15 shown in FIG.
And 14 constitute a register, so that only the data input terminal DI, the selector circuit 12 and the data output terminal DO are allowed as a normal data propagation path.

In the normal operation of the system shown in FIG. 5, the expected operation may not be obtained because the input / output data timing of each chip 2 does not match. In this case, it is necessary to provide a delay element (not shown) between the data input terminal 4I or the data output terminal 40 of the predetermined chip 2 and the system signal line 7 in order to match the timing.

This requires labor for newly providing a delay element on the board, and increases the number of parts of the system device.

It is ideal that the timing can be matched not only between the chips but also between a predetermined data input terminal 4I or data output terminal 40 of each chip and the system signal line 7.

Therefore, an object of the present invention is to match the input / output timing of system data in an integrated circuit device having a test function without increasing the number of components of the system device.

[0040]

According to a first aspect of the present invention, there is provided an integrated circuit device having a plurality of scan register means connected in series between a test input terminal and a test output terminal. An integrated circuit device, wherein each of the scan register means has a first input terminal for inputting system data, a first output terminal for outputting system data, and a test output terminal for inputting test data. A second input terminal, a second output terminal for outputting test data, and a first terminal connected to the first and second input terminals for selecting one of the first and second input terminals. Selecting means and an output of the first selecting means,
A shift-out means for shifting out to the second output terminal, and latch means for latching the output of said shift-out means, connected to the output of said first input terminal and said latch means, said input terminal and said latch means A second input means for outputting one of the outputs to the first data output terminal, and a first input terminal by controlling the first and second selection means, shift-out means and latch means. A first path connecting between the first input terminal and the first output terminal between the first input terminal and the first output terminal, and a shift-out means between the first input terminal and the first output terminal. , A second path connected by the latch means and the second selection means,
A third path connecting between the second input terminal and the second output terminal by the first selector and the shift-out means, and a first path connecting the second input terminal and the first output terminal. Control means for forming a fourth path connected by the selection means, shift-out means, latch means and second selection means, and delay means interposed in the second path for delaying the system data. ,including.

According to a second aspect of the present invention, there is provided an integrated circuit device according to the first aspect of the present invention, wherein a plurality of scan register means and control means are provided between an output of the shift-out means and an input of the latch means. And a delay unit for delaying system data, wherein the control unit individually controls each of the scan register units to generate the first path and the second path.

[0042]

In the integrated circuit device according to the first aspect of the present invention, each of the scan register means is controlled by the control means to form first to fourth paths. The first path and the second path can propagate system data. The third path can shift out test data. Further, a fourth path can provide test data to the system logic. Since the second path is provided with a delay unit, the input first data can be delayed.

Therefore, this integrated circuit device can have two paths, that is, the first and second paths, which can propagate system data at different timings. As a result, by selectively using the first path and the second path as system data propagation paths, it becomes easy to match the input / output timing of system data. Further, since the delay means is provided in the integrated circuit device, the number of components of the system device does not increase.

Further, in the integrated circuit device according to the second aspect of the present invention, each scan register means can be individually controlled, and the first path and the second path can be individually generated. The system data input / output timing of the means can be matched.

[0045]

FIG. 1 shows an integrated circuit device 20 according to the present invention.
It is a block diagram of.

The integrated circuit device 20 shown in FIG. 1 shows only four boundary scan registers to simplify the description. Referring to FIG. 1, integrated circuit device 20 includes mode signal M, shift / load signal SL, clock signal CKA1,
A control circuit 50 for generating the clock signal CKA2 and the clock signal CKB; a path 61 for shifting test data and a path 62 for supplying shift data in response to a control signal from the control circuit 50; A path 63, a boundary scan register 5 forming paths P1 and P2 for transmitting system data, and a delay element 2
5 is included. The other circuits are the same as those of the integrated circuit device 2 shown in FIG. 5 , and the same reference numerals are given and the description will be appropriately omitted.

The control circuit 50 sets (1) the shift / load signal SL to "1" to form the path 61 for shifting the test data, and sets the clock signals CKA1 and CK.
A2 is given to each boundary scan register 5, and (2)
The mode signal M is set to "1" in order to form the path 62 for supplying test data, and the clock signals CKA1, CKA
KA2 is supplied to the boundary scan register 5,
(3) To form a path 63 for taking in test data, the shift / load signal SL is set to "0", the clock signal CKB is supplied to the boundary scan register 15, and (4) the system data propagation path P1 is (5) To form the system data propagation path P2, the mode signal M is set to "1", the shift / load signal SL is set to "1", and the clock signal is set to (5). CKA1, CKA2 and CKB are brought high.

Each boundary scan register 5 forms a path 61 in response to the control signal of the above (1), propagates the data supplied to the scan input terminal SI to the shift path 6, and transmits the data to the control signal of the above (2). In response, the path 62 is formed, the data supplied to the scan input terminal SI is output to the data output terminal DO, and in response to the control signal of (3),
The path 63 is formed, the data supplied to the data input terminal DI is taken in, the data is output to the shift path 6, the path P1 is formed in response to the control signal of (4), and the system data supplied to the input terminal DI is Output to the data output terminal DO. However, when the system data is delayed or when the path P1 fails, the path P2 is formed by receiving the control signal of the above (5), and the system data is transmitted via the delay element 25 instead of the path P1. Output to the output terminal DO.

By doing so, the input / output timing of the system data can be matched, and even if a failure occurs in the path P1, a propagation path for the system data can be secured.

The delay element 25 is an element for delaying data (system data) during normal operation for a predetermined time. This delay time is set, for example, by connecting a plurality of inverters in series.

FIG. 2 is a circuit diagram of the boundary scan register 5 shown in FIG. 5 is different from the boundary scan register 5 shown in FIG. 5 in that a register circuit 23, a latch circuit 24, and a delay circuit for performing a shift operation using non-overlapping two-phase clock signals CKA1 and CKA2 instead of the flip-flop circuits 13 and 14. That is, the element 25 is provided.

FIG. 3 is a circuit diagram showing a specific example of the register circuit 23 shown in FIG.

The register circuit 23 is a ratio type latch circuit 3
1a and 31b. Register circuit 2
Reference numeral 3 inputs a non-overlapping two-phase clock signal to terminals T1 and T2, thereby causing a shift operation between ID and Q. Further, by supplying a high-level clock signal to both the terminal TI and the terminal T2,
The portion between the input terminal ID and the output terminal Q can function as a data non-inversion driver.

The boundary scan register 5 shown in FIG. 2 has a mode signal M of "1", a shift / load signal SL of "0", and a clock signal in addition to the operation of the boundary scan register 5 shown in FIG. By setting CKA1, CKA2 and CKB to a high level, it is possible to secure a normal data propagation path in addition to the normal operation.
That is, by inserting the boundary scan register shown in FIG. 2 between the system logic circuits, a new normal data propagation path can be formed when the conventional normal data propagation path fails. Thereby, the system data can be delayed for a predetermined time, and the input / output timing can be matched.

FIG. 4 is a circuit diagram showing one embodiment of the integrated circuit device of the present invention.

In the integrated circuit device shown in FIG. 4, the boundary scan register 5 is inserted between the system logics, and
The boundary scan register is controlled by two mode signals M1 and M2. In the integrated circuit device of FIG. 4, each of the boundary scan registers is controlled by mode signals M1 and M2. Since the normal data propagation path of each boundary scan register can be controlled by the mode signals M1 and M2, the delay amount of the normal data propagation path can be set for each boundary scan register.

[0057]

According to the integrated circuit device of the present invention, the first path having no delay and the second path delayed by a predetermined time can be used as paths for transmitting system data. Therefore, when the timings of the system data are matched, the expected system operation can be performed by controlling the shift register means by the control means and selecting one of the first path and the second path. . Further, since the delay means is not provided in the integrated circuit device, the number of components of the system device does not increase.

Further, the control means independently controls the scan register means connected to the first input terminal and the scan register means connected to the first output terminal. Output timing can be controlled.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an integrated circuit device of the present invention.

FIG. 2 is a circuit diagram of a boundary scan register shown in FIG.

FIG. 3 is a circuit diagram showing a specific example of the register circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram of a test circuit configured by a boundary scan design.

6 is a circuit diagram showing a conventional example of the boundary scan register shown in FIG.

FIG. 7 is a circuit diagram showing details of a portion surrounded by a broken line in FIG. 5;

8 is a circuit diagram showing details of a portion surrounded by a chain line in FIG. 5;

[Explanation of symbols]

 2 chip 3 internal logic circuit 4 data input / output terminal 5 boundary scan register 6 shift path 7 system signal line 11, 12 selector circuit 13, 14 flip-flop circuit 23 register circuit 24 latch circuit 25 delay element

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28-31/3193 G06F 11/22-11/26 310 H01L 27/04

Claims (2)

(57) [Claims] 1. An integrated circuit device having a plurality of scan register means connected in series between a test input terminal and a test output terminal, wherein each of the scan register means includes a first input terminal for inputting system data. A first output terminal for outputting system data; a second input terminal for inputting test data; a second output terminal for outputting test data; Selecting means for selecting one of the first and second input terminals connected to the first and second input terminals; and shifting out the output of the first selecting means to the second output terminal. Shift-out means; latch means for latching the output of the shift-out means; connected to the first input terminal and the output of the latch means; A second selector for outputting one of the outputs to the first data output terminal; a first input terminal for controlling the first and second selectors, the shift-out unit, and the latch unit; A first path connecting between the first output terminal and the first output terminal, and a first path connecting between the first input terminal and the first output terminal via the second selection means; A second path connected by the latch means and the second selection means, a third path connected between the second input terminal and the second output terminal by the first selection means and the shift-out means, Control means for forming a fourth path connecting between the second input terminal and the first output terminal by a first selection means, a shift-out means, a latch means and a second selection means; 2 which is inserted in the path 2 and delays the system data. Integrated circuit device comprising: the means. 2. A semiconductor integrated circuit device in which a plurality of scan register means are connected in series between a test input terminal and a test output terminal, each of said scan register means having a first scan register for inputting system data. A first input terminal, a first output terminal for outputting system data, a second input terminal for inputting test data, a second output terminal for outputting test data, A first selector connected to the first and second input terminals and selecting one of the first and second input terminals; and an output of the first selector is shifted out to the second output terminal. Shift-out means, latch means for latching the output of the shift-out means, the input terminal and the latch connected to the first input terminal and the output of the latch means. A second selector for outputting one of the outputs of the stage to the first data output terminal; a first input for controlling the first and second selector, the shift-out unit, and the latch unit; A first path connecting the terminal and the first output terminal via the second selection means, and a first selection means connecting the first input terminal and the first output terminal to the shift-out terminal. Means, a latch means and a second path connected by the second selection means, and a third path connecting between the second input terminal and the second output terminal by the first selection means and the shift-out means. Control means for forming a fourth path connecting between the second input terminal and the first output terminal by the first selection means, the shift-out means, the latch means and the second selection means; Between the output of the shift-out means and the input of the latch means And a delay unit for delaying system data, wherein the control unit individually controls each of the scan register units to generate the first path and the second path. Integrated circuit device.