JPH02128179A - Integrated circuit - Google Patents

Abstract

PURPOSE:To simplify the formation of a test pattern and the development of a test substrate and to perform the test operation of an internal circuit so as to easily correspond even to an increase of a scale by inputting a fundamental clock from the outside of an integrated circuit. CONSTITUTION:When a test mode change-over signal for changing over and setting a test signal generation circuit 3 and a selector circuit 4 to a burn-in mode state is inputted to a test mode change-over input terminal 5, the signal generation circuit 3 becomes a usable state and the selector circuit 4 brings the signal generation circuit 3 and an internal circuit 1 to a connection state. The signal generation circuit 3 generates two or more kinds of signals as test signals on the basis of the fundamental clock inputted from a part of an external terminal 2. The test signals are combined so that the parts as many as possible of the internal circuit 1 are operated to be given to the internal circuit 1 through the selector circuit 4 and, by this method, the burn-in test operation of the internal circuit 1 is performed. Since the test signals are generated internally, correspondence can be easily taken even to an increase in the scale of an integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to integrated circuits, and particularly to facilitating the testing thereof.

[Conventional technology]

The manufacturing process for semi-custom integrated circuits, such as gate arrays, begins with the desired circuit design by the integrated circuit user, logic verification and timing verification with the integrated circuit manufacturer, and then the integrated circuit design. The conventional and common procedure is to move on to manufacturing the circuit. therefore,
The integrated circuit obtained by such a manufacturing process is
As schematically shown in the block diagram in FIG. 3, an internal circuit 1 installed by the user and used for actual use;
It is constituted by this internal circuit 1 and an external terminal 2 for transmitting and receiving signals between the outside of the integrated circuit.

By the way, integrated circuit manufacturers usually conduct a test called burn-in in order to reduce the initial failure rate of integrated circuits. This burn-in test is performed in order to discover early failures in integrated circuits by leaving the internal circuit 1 operating for several hours to several tens of hours under high voltage and high temperature environments that are more severe than actual usage conditions. This test is especially essential for integrated circuits that require a low failure rate, such as integrated circuits installed in automobiles.

[Problem to be solved by the invention]

However, when performing a burn-in test on a conventional integrated circuit with the above-mentioned internal configuration, the manufacturer must create a test pattern for test operation of the internal circuit 1 for each integrated circuit manufactured. As the scale of integrated circuits increases year by year,
There is a problem that the test pattern creation work becomes complicated and difficult.

In addition, the burn-in equipment traditionally used for burn-in tests has a limited number of pins that output test signals including the test patterns and clocks mentioned above, so as the scale of integrated circuits increases, their internal circuits A situation is occurring in which only a small part of 1 can be operated. Furthermore, a test board for supplying a plurality of types of D1- signals to the integrated circuit must be developed for each integrated circuit, which poses problems such as requiring a great deal of labor.

This sale was made in order to solve the problems mentioned above, and it does not require a lot of effort to create test patterns or develop test boards, and it can easily accommodate increases in scale. The object of the present invention is to obtain an integrated circuit capable of performing test operations on internal circuits.

[Means to solve the problem]

The integrated circuit according to the present invention includes an internal circuit for actual use, a basic clock input terminal for inputting a basic clock, and a test signal such as a test pattern for testing the internal circuit based on the basic clock. A test signal generating circuit is provided, and a test mode switching input terminal is provided for inputting a test mode switching signal that enables the use of the D1- signal generating circuit.

[Effect]

In this invention, when a test mode switching signal is input to the test mode switching input terminal from outside the integrated circuit, the test signal generation circuit becomes usable. A test signal such as a test pattern is generated based on the tarokk. In response to this test signal, the internal circuit performs a test operation.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of an integrated circuit according to the present invention. In the figure, an internal circuit 1 is an original circuit section used in actual use, and signals can be exchanged between this internal circuit 1 and the outside of the integrated circuit via an external terminal 2.

Separately, there is also a test signal generation circuit 3 that generates a test signal such as a test pattern for performing a burn-in test operation on the internal circuit 1, and a test signal generation circuit 3 that is connected to the internal circuit 1 or connected to the internal circuit 1. A selector circuit 4 for disconnecting the test signal generating circuit 3 and a test mode switching input terminal 5 for receiving a test mode switching signal for enabling the test signal generating circuit 3 from outside the integrated circuit are provided. The test mode switching input terminal 5 is connected not only to the test signal generation circuit 3 but also to the selector circuit 4. A part of the external terminal 2 is commonly used as a basic clock input terminal for receiving a basic clock CK, which is the basis for the signal generation circuit 3 to generate a test signal for the test 1, from outside the integrated circuit.

Next, the operation during a burn-in test of the above-described integrated circuit will be explained. When a test mode switching signal for switching and setting the test signal generation circuit 3 and selector circuit 4 to the burn-in mode state is input to the test mode switching input terminal 5, the test signal generation circuit 3 becomes available for use.
The selector circuit 4 connects the test signal generation circuit 3 and the internal circuit 1. When the test signal generation circuit 3 is ready for use, it generates multiple types of signals as test signals, as shown in the waveform diagram in FIG. 2, based on the basic clock CK input from a part of the external terminal 2. . That is, FIG. 2 (1) shows the waveform of the basic clock CK input from the external terminal 2 as it is, FIG. 2 (2) shows the waveform of the basic clock CK divided by two, CK2, and FIG. Clock GK frequency divided by 4 signal CK4. FIG. 2 (4) shows the waveform of the 8-frequency divided signal CK8 of the basic clock CK,
FIG. 2 (5) to (12) show the respective waveforms of eight-phase clocks φ to φ8 obtained by the combination of these signals.

The test signal generated by the test signal generation circuit 3 is as follows:
As many parts of the internal circuit 1 as possible are combined so as to be operational and applied to the internal circuit 1 through the selector circuit 4, thereby performing a burn-in test operation of the internal circuit 1. Since the test signal is generated internally, it can easily accommodate an increase in the scale of the integrated circuit.

In the above embodiment, the test signals generated by the test signal generation circuit 3 are given as examples of the signals having the respective waveforms shown in (1) to (12) in FIG. A signal may also be generated. In the case of a semi-custom integrated circuit, the generation of this test signal pattern can be left to the user (designer) side from the integrated circuit manufacturer side, making it extremely easy to generate it.

In addition, in the case of integrated circuits of different types but in the same package, the external clock input terminal is used as a basic clock input terminal for receiving the basic clock CK supplied to the test signal generation circuit 3 from outside the integrated circuit. By specifying pins in the same position among terminals 2, one burn-in test board can be shared for many types of integrated circuits, eliminating the need to design a test board for each integrated circuit. can do.

〔Effect of the invention〕

As explained above, according to the present invention, the integrated circuit itself is configured to generate the test signals necessary for testing the internal circuit by simply inputting the basic clock from outside the integrated circuit. Therefore, it does not require a lot of effort to create test patterns or develop test boards, and it can easily accommodate increases in the scale of integrated circuits.
This has the effect of making it easier to test internal circuits in burn-in tests and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an integrated circuit according to the present invention, FIG. 2 is a waveform diagram showing a test signal generated by a test signal generation circuit in the integrated circuit, and FIG. It is a block diagram showing the configuration. In the figure, 1 is an internal circuit, 2 is an external terminal, 3 is a test signal generation circuit, and 5 is a test mode switching input terminal. Note that the same reference numerals in each figure indicate the same or equivalent parts. to beat.

Claims (1)

[Claims] (1) An internal circuit for actual use, a basic clock input terminal for inputting a basic clock, and a test signal that generates a test signal such as a test pattern for testing the internal circuit based on the basic clock. An integrated circuit comprising: a generating circuit; and a test mode switching input terminal for inputting a test mode switching signal that enables the test signal generating circuit.