JPH0252461A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make a testing operation at a low cost and to simply operate it when a dynamic BT is executed by a constitution wherein, during a test, individual test pattern signals are supplied to individual signal input ends of an internal circuit by using a test control signal. CONSTITUTION:Terminals Tc, T1 to Tm of a test signal generation circuit are connected to individual signal input ends of an internal circuit 2. Gate transistors Q1 to Qm become in a conducting state during a test by means of a test control signal TC; individual test pattern signals from a test signal generation circuit 1 are supplied individually to the terminals T1 to Tm correspondingly. During a normal operation, gate transistors Q0, Q1 to Qm become in a nonconducting state; the test signal generation circuit 1 is separated from the internal circuit 2 and the terminals Tc, T1 to Tm. Accordingly, during a dynamic BT it is possible to test the internal circuit 2 only by supplying a clock signal CK and the test control signal TC from the outside (a testing apparatus).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device designed so that burn-in tests can be performed effectively.

[Conventional technology]

Traditionally, burn-in tests (hereinafter referred to as BT) for quality assurance of semiconductor devices have been conducted using static BT, which applies a certain voltage in a high-temperature furnace for a certain period of time, and tests that apply a certain voltage for a certain period of time while operating the internal circuits of the semiconductor device. There are two types of dynamic BTs that apply a constant voltage in a high-temperature furnace, and dynamic BTs are said to have a higher BT effect than static BTs because signal voltages can be applied to most of the elements inside a semiconductor device. There is.

FIG. 2 is a connection diagram with a test equipment when performing dynamic BT of a conventional semiconductor device.

In the conventional semiconductor device 10, when performing dynamic BT, a large number of test pattern signals are required to operate the internal circuit 2, as shown in FIG. Signal, BT
A dedicated testing device 20 equipped with a furnace and a test pattern signal generator includes terminals T, , To, Tl for connecting external circuits.
The configuration was such that it was supplied via T7.

[Problem to be solved by the invention]

The conventional semiconductor device 10 described above has a configuration that requires a dedicated test device 20 that generates a large number of test pattern signals in order to operate the internal circuit 2 when performing dynamic BT. Although it is large, it has the disadvantage that the manufacturing cost including the testing device 20 etc. is high.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can reduce manufacturing costs by reducing the cost of a test device and can provide sufficient quality assurance.

[Means to solve the problem]

The semiconductor device of the present invention includes a plurality of terminals for external circuit connection that are respectively connected to a plurality of signal input terminals of an internal circuit, and a test signal that inputs a clock signal and outputs a plurality of predetermined test pattern signals. It has a generation circuit and a plurality of gate circuits that transmit each of the test pattern signals to each of the terminals in response to a test control signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The test signal generation circuit 1 generates a goo transistor Q during a test using a test control signal TC. When it becomes conductive, it inputs the clock signal CK from the terminal Tc and outputs a plurality of predetermined test pattern signals.

The internal circuit 2 includes a plurality of combinational circuits 21A, 21θ, a plurality of flip-flops 22 (abbreviated as F/F in FIG. 1), and switch circuits SIO to S, -, S2o to S2m.
It has a predetermined function. This embodiment has a scan path circuit configuration.

Terminal T. .

Gate transistors RO 1 to Q YO become conductive during testing by test control signal TC, and test signal generation circuit 1
Each test pattern signal from
1 to T. That is, test pattern signals are supplied to each signal input terminal of the internal circuit 2, respectively.

During normal operation, the gate transistor Qo.

Q+ to Q□ are rendered non-conductive by the test control signal TC, and the test signal generation circuit 1 is connected to the internal circuit 2 and the terminals To,
T, ~T, separated from n.

Therefore, during dynamic BT, it is possible to test the internal circuit 2 by simply supplying the clock signal CK and test control signal TC from the outside (testing equipment), so the test pattern signal generation for the testing equipment for dynamic BT is possible. The apparatus can be greatly simplified, the test apparatus becomes inexpensive, the test operation becomes simple, and the manufacturing cost can be reduced. Moreover, the test signal generation circuit 1
The test pattern signal generated from the test pattern signal can sufficiently guarantee quality.

〔Effect of the invention〕

As explained above, the present invention provides a test signal generation circuit that inputs a clock signal and generates a plurality of test pattern signals, and during a test, each test pattern signal is transmitted to each signal input terminal of an internal circuit by a test control signal. When implementing dynamic BT, by configuring the supply to
Since the test equipment can be made inexpensive and easy to operate, manufacturing costs can be reduced and quality can be ensured sufficiently.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a connection diagram of a semiconductor device and a test device for explaining an example of a conventional semiconductor device. ■...Test signal generation circuit, 2...Internal circuit, 10
...Semiconductor device, 20...Testing device, 21A, 21
B...Combination circuit, 22...Flip-flop, Q
. Q t ~Q ---gate transistor, Slo ~ S1
．． ,,. 320~32m"・Switch circuit, 'r,,'ro, T
, ~T,,T,,,T□00. terminal. Pr, L, JT-Science and Engineering Uchihara Ei.

Claims (1)

[Claims] A plurality of terminals for external circuit connection that are respectively connected to the plurality of signal input terminals of the internal circuit, a test signal generation circuit that inputs a clock signal and outputs a plurality of predetermined test pattern signals, and a test control signal. and a plurality of gate circuits configured to transmit each of the test pattern signals to each of the terminals in a corresponding manner.