JPH01298733A - Integrated circuit with built-in self-traveling function - Google Patents

Abstract

PURPOSE:To positively operate an integrated circuit at the time of a test to generate an internal heat, and to improve the reliability of the test by receiving a selective control signal corresponding to the system operation mode and test mode of the integrated circuit, selecting the output of an FF circuit at the time of a system operation, selecting a clock synchronizing signal at the time of the test mode, and supplying it to a corresponding logic circuit. CONSTITUTION:When an output selective controller 13i receives a selective control signal from a selective control signal generator 14, it selectively controls a clock synchronizing signal from a clock synchronizing signal generator 15, and supplies it to a corresponding predetermined logic circuit. Thus, each logic circuit 12j (j=1-m) in an integrated circuit operates at random by the clock synchronizing signal input from the corresponding output selective controller, and generates an internal heat. Thus, the burn-in test of the integrated circuit can be conducted by adding the simple selective control signal generator and the output selective controller without using a scanning system. Thus, the integrated circuit can be effectively used for its original logic circuit operation.

Description

[Detailed Description of the Invention] [Summary] Regarding an integrated circuit with a built-in free-running function that randomly operates the internal logic circuit group of an integrated circuit such as an LSI to generate internal heat during a burn-in test, It can be used effectively for circuit operation, it simplifies the signals during testing, making the external circuit simpler and more reliable, and it ensures that the integrated circuit operates reliably during testing to generate internal heat, thereby increasing the reliability of the test. An integrated circuit with a built-in free-running function that uses the clock supplied to each FF circuit to operate the internal logic circuit group of the integrated circuit in a rung manner during a burn-in test to generate internal heat for the purpose of improving performance. means for generating a selection control signal corresponding to a system operation mode and a test mode of the integrated circuit; In the test mode, means is provided to select the clock synchronization signal and supply it to the corresponding logic circuit.

[Industrial application field]

The present invention provides a free-running function that randomly operates the internal logic circuit group of an integrated circuit such as an LSI using a clock supplied to its flip-flop circuit (hereinafter referred to as FF circuit) during a burn-in test to generate internal heat generation. Concerning built-in integrated circuits.

[Conventional technology]

When an integrated circuit such as an LSI is manufactured, a test is performed to stabilize its characteristics and eliminate initial defects prior to its actual use. In this case, in order to shorten the test time, a burn-in test is performed in which the test is performed in a high temperature environment and under energized conditions. this is,
This is an acceleration test that applies thermal stress to integrated circuits.

As thermal stress, it is effective to raise the temperature around the integrated circuit using a constant temperature device or the like, and also to raise the temperature inside the integrated circuit. In this case, for bipolar devices (for example, ECT, TTL circuits, etc.) in the logic circuit group in the integrated circuit, internal heat generation can be generated by the conduction current by static operation simply by applying the power supply voltage. . However, CMOS devices (CMO3 circuit, Bi
-CMO3 circuit, etc.) does not generate internal heat unless a switching operation is performed due to its circuit characteristic that there is almost no conduction current in a static state.

When performing a burn-in test on CMO3 type devices, it is necessary to add an external circuit to the integrated circuit and supply the integrated circuit with predetermined clock pulses, timing signals, test data signals, etc. to switch each device. A method has been adopted in which internal heat generation is generated through dynamic operation.

On the other hand, in integrated circuits, as the scale of integration increases, the amount of test data becomes enormous, and the number of human output pins is also limited, making it difficult to create test data and output it manually. (In order to solve this problem and to facilitate and automate the functional testing of highly integrated circuits, various scan systems have been adopted in testing of highly integrated circuits such as LSIs and VLSIs. .

In the scan system, test data is directly set from the outside to each FF circuit of the logic circuit group through the scan-in bus, the logic circuit group of the integrated circuit is operated by stepping with a lock as necessary, and the results are transferred to the scan-out bus. The test is carried out by taking out the data via the PC and checking the output results.

In the burn-in test method using this scan system, in order to further ensure the supply of test clocks and eliminate the need for an external circuit for clock supply, an internal oscillator is provided in the integrated circuit for each FF circuit. There is also a method in which internal heat generation is realized by supplying a clock to the device.

[Problem to be solved by the invention]

In the burn-in test, which applies thermal stress to an integrated circuit and performs an acceleration test, as a method of activating the logic circuit in order to generate internal heat in the integrated circuit, conventionally, as mentioned above, Add an external circuit,
There were two methods: one method was to generate internal heat by supplying test data and a clock to an integrated circuit to operate its internal logic circuit group, and the other was to generate internal heat by operating the integrated circuit using a scan system.

Method (2) has the advantage that there is no need to provide a special structure for testing inside the integrated circuit, but on the other hand, it requires an external circuit for testing, and it requires multiple types of inputs from external circuits. If there is a problem inside, correct test results cannot be obtained, and it is difficult to check the normality of the external circuit, so there is a problem in that it is not easy to increase the reliability of the test.

Method (2) has the advantage that the reliability of the external circuit is not a particular problem because it requires less human power, and in particular, the method with a built-in oscillator does not require an external circuit. configuration (for example, the gate ratio between scan FF and normal FF is about 1.3:l), the effective part used for the original logic circuit operation of the integrated circuit decreases, and this reduces the degree of integration. There was a problem in that it was unsuitable for integrated circuits with low densities.

The present invention makes it possible to effectively use an integrated circuit for its original logic circuit operation, simplify signals during testing, simplify the configuration and increase reliability of external circuits added during testing, and The purpose of the present invention is to provide an integrated circuit with a built-in free-running function that can be applied to small-scale integrated circuits by improving test reliability by operating the integrated circuit reliably and generating internal heat.

[Failure to solve the problem]

The means adopted by the present invention to solve the above-mentioned problems are as follows:
This will be explained with reference to FIG. FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, 10 is an integrated circuit, which has logic circuit groups such as flip-flop circuits (FF circuits, 111, 112, etc.) and combinational circuits (12, 12□, etc.). The configuration of the logic circuit group shown in FIG. 1 is an example thereof. The terminal 1 is a data input terminal to each FF circuit 11+.

1:L (!=l~n) is an output selection control circuit, and each F
The selection control signal from the selection control signal generation circuit 14 is provided for each F circuit 12+ (i=l-n), and receives a clock synchronization signal synchronized with the output from the corresponding FF circuit 121 and the clock (indicated by CK). Accordingly, in the system operation mode, the output of the corresponding FF circuit 111 is selectively controlled, and in the test mode, the clock synchronization signal is selectively controlled and supplied to the corresponding logic circuit.

The selection control signal generation circuit 14 receives a mode setting signal that sets the operation of the integrated circuit 10, generates a selection control signal corresponding to each mode setting signal state of the normal system operation mode and the test mode, and selects each output. Control circuit 13i
(i=l-n).

Reference numeral 15 denotes a clock synchronization signal generation circuit, which receives a clock from the outside and generates various clock synchronization signals synchronized with the clock, and outputs each FF circuit 11+ (]=1 to n) and output selection control circuit LL (i=1 -n).

[For production]

First, when the integrated circuit IO is to perform its original logic circuit operation, it is set to a mode setting signal in a system operation mode in which normal system operation is performed, and tarock and data are manually input to the integrated circuit IO.

At this time, the selection control signal generation circuit 14
A selection control signal is generated to select the output of each FF circuit 11. (l=l-n) is supplied to the output selection control circuit 13+. Further, the clock synchronization signal generation circuit 15 receives the clock CK, generates various clock synchronization signals synchronized with the clock CK-1, and supplies them to each FF circuit 11+ and the output selection control circuit 13m.

Upon receiving this selection control signal, the output selection control circuit 13+ selects the output of the corresponding FF circuit 11+ and supplies it to a predetermined logic circuit.

As a result, each FF circuit 111 (l
The logic circuit groups such as J = 1 to n) and each logic circuit 12j (J = 1 to m) perform their original logic circuit operations in response to an external clock CK and data input.

Next, when performing a burn-in test on the integrated circuit 10, the mode setting signal is set to a state corresponding to the test mode.

At this time, the selection control signal generation circuit 14 generates a selection control signal for selecting the clock input to each FF circuit 111.
-1 to n) output selection control circuits 13. Further, the clock synchronization signal generation circuit 15 receives the clock CK, generates various clock synchronization signals synchronized with the clock CK, and generates various clock synchronization signals for each FF circuit 11+ and the output selection control circuit 13.
+ Supply. On the other hand, data is not input manually to the D terminal of the integrated circuit.

The output selection control circuit 13 is a selection control circuit (No. 8 generation circuit 1
4, the clock synchronization signal generation circuit 15 selectively controls the clock synchronization signal from the clock synchronization signal generation circuit 15 and supplies it to a corresponding predetermined logic circuit.

As a result, each logic circuit 12J (j=1
~m) perform random operations based on the clock synchronization signal input from the corresponding output selection control circuit, and generate internal heat generation.

As described above, by adding a simple selection control signal generation circuit and an output selection control section without using a scan system, it is possible to perform burn-in tests on integrated circuits. It can be used effectively for

In addition, the external circuits added for burn-in testing only need to be generated circuits for clock signals and mode setting signals, and unlike conventional external circuits for testing, various timing signals other than clocks and data input for testing are required. This allows the integrated circuit to operate reliably and generate internal heat, making it simple and highly reliable.
Test reliability can be improved.

Furthermore, by simply adding a simple selection control signal generation circuit 14 and an output selection control section 13+, it is possible to effectively use the integrated circuit IO for its original logic operation, so it is possible to use a small-scale device with a relatively small degree of integration. It can also be used in integrated circuits.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is an explanatory diagram of the configuration of one embodiment of the present invention, and FIG. 3 shows the FF circuit, output selection control circuit, and
FIG. 2 is an explanatory diagram of each configuration of a selection control signal generation circuit and a clock synchronization signal generation circuit.

(A) Structure of the embodiment In FIGS. 2 and 3, the integrated circuit 10. FF circuit 1
1+ (+=1 to n), logic circuit 12. (j=1~m
), output selection control circuit 13i (i=1 to n), selection control signal generation circuit 14, and clock synchronization signal generation circuit 1
5. The clock CK, data terminal, etc. are as explained in FIG. 1.

FF circuit 11 in Figure 3 (Since this is a configuration common to all FF circuits, the addition of the suffix "l" is omitted and is added only when it is particularly necessary to differentiate. The same applies to other configurations. ) is a well-known mask slave type OFF. That is, the mask part is a series circuit consisting of an impark 111 that inverts input data, a mask transmission gate (indicated by mask TG) 112 that gates the inverted input data with tarlocks CK and *CK, and a mask latch 113 that holds the inverted input data. configured. The mask TG112 is configured by connecting in parallel -Jl a P channel MO3 whose gate is controlled by a clock CK and an N channel MO3 whose gate is controlled by an inverted clock *CK.

The slave part also includes a slave transmission gate (indicated by slave TG) 114 similar to the mask part;
It is composed of a series circuit of a slave latch 115 and an inverter 116. However, the slave TG114 has its P channel M O
S is gate-controlled by the inverted clock *CK, and N-channel MO5 is gate-controlled by the clock CK.

Next, in the output selection control circuit 13, 131 is a first transmission gate (indicated by a first TG) that gate-controls the output of the FF circuit 11;
A P-channel MO3 whose gate is controlled by an inverted burn-in control signal *TBi supplied from 4, and a burn-in control signal TB also supplied from the selection control signal generation circuit 14,
It is constructed by connecting N-channel MO8 gate-controlled in parallel.

132 is a second transmission gate (indicated by a second TG) that gate-controls the clock synchronization signal CK from the clock synchronization signal generation circuit 15, and similarly to the first TG 131, a P-channel MO3 and an N-channel MOS are connected in parallel. It consists of However, the second TG 132 is
Contrary to G131, its P-channel MO3 is gate-controlled by a burn-in control signal TBI, and its N-channel MO8 is gate-controlled by an inverted burn-in control (No. 8*TBi).

Therefore, when TBmu = "1" and *TB+ = "0", the first TG 131 is turned on (open) and the second TG 132 is turned off (closed), the signal from the FF circuit 11 is output, and TBI = " 0” and *TBi=1, the first TG
131 is turned off (closed), the second TG 132 is turned on (open), and the clock synchronization signal CK is output.

The selection control signal generation circuit 14 includes two inverters 141
and 142 series circuits. Inverter 141
In the system operation mode, the burn-in on signal (indicated by the TBOON signal) is input as the mode setting signal, and in the test mode, the TBi is input as the mode setting signal.
Bin-in/off signal (TBiOF) which is an inversion of the ON signal
(indicated by F signal) is manually operated. From the output end of the inverter 141, there is a manually inputted TB, an ON signal, or a TB.

An inverted burn-in signal (*TBl) which is an inversion of the OFF signal.
) is output as a selection control signal, and from the output terminal of the inverter 142, the manually input TBI ON signal or TBI
A burn-in signal (TBI) having the same polarity as the OFF signal is output as a selection control signal.

These selection control signals, that is, the inverted burn-in signal *TB and the burn-in signal TB, are connected to the F F" circuit 11.
+ and output selection control circuit 13. supplied to

The clock synchronization signal generation circuit 15 includes two inverters 1
It is composed of 51 and 152 series circuits.

The output terminal of the inverter 151 outputs an inverted clock synchronization signal *0K, which is obtained by inverting the manually input clock CK, and the output terminal of the inverter 152 outputs the input clock CK.
A clock synchronization signal (indicated by the same CK) synchronized with is output.

(B) Operation of the Embodiment The operation of the embodiment will be explained separately for operations when the integrated circuit 10 is caused to perform its original logical operation and when a burn-in test is performed.

(1) Original logic operation When making the integrated circuit 10 perform the original logic operation, the mode setting is set to system operation mode, and the integrated circuit 10
The TB+ON signal is manually input to the selection control signal generation circuit 14 of the . Further, a clock CK is inputted to the synchronization signal generation circuit 13, and data is inputted to the data terminal of the integrated circuit 10.

The clock synchronization signal generation circuit 15 generates a clock synchronization signal C.
K and an inverted clock synchronization signal *CK to each FF.
Circuit 11+ (i=1 to n) and output selection control section 13
Supply to t.

On the other hand, when the selection control signal generation circuit 14 receives the TB+ON signal, it generates a burn-in signal TB and an inverted burn-in signal *TB+, and outputs a burn-in signal *TB+.

N-channel MO3 of the first TG131 and the second TG13
2, P channel MO3, and *TB+ is supplied to the first TG
131 and the N-channel MO3 of the second TG 132.

During system operation, the burn-in signal TBi is on and the inverted burn-in signal *T B l is off. Therefore, in each output selection control section 131, the first
Since the TG 131 is turned on (open) and the second TG 132 is turned off (closed), each output selection control circuit 13+ is
The output of the corresponding FF circuit lit is selected and supplied to the corresponding predetermined logic circuit.

As a result, each FF circuit 111 (l
The logic circuit groups such as the logic circuits 12J (j=1 to n) and the logic circuits 12J (j=1 to m) perform their original logic circuit operations in response to an external clock CK and data input.

(2) Burn-in test operation When performing a burn-in test on the integrated circuit 10, the mode setting is set to test mode, and the TB and OFF signals are manually input to the selection control signal generation circuit 14.

On the other hand, although the clock CK is input to the clock synchronization signal generation circuit 15, no data is input to the data terminal of the integrated circuit 10.

The clock synchronization signal generation circuit 15 generates the clock synchronization signal CK and the inverted clock synchronization signal *CK as in the system operation mode, and each FF circuit 11+ (i=
1 to n) and the output selection control circuit 13i.

On the other hand, when the selection control signal generation circuit 14 receives the TBi OFF signal, it generates the corresponding burn-in signal TB.
, and an inverted burn-in signal *TB.

As in the system operation mode, TB is supplied to the N channel MO3 of the first TG 131 and the P channel MO3 of the second TG 132, and *TB is supplied to the first TG 131.
and the N-channel MO3 of the second TG 132.

During the burn-in test, the burn-in signal T B t is off, and the inverted burn-in signal *TBl is on.

Therefore, in each output selection control circuit 13°, the first
Since the TG 131 is turned off (closed) and the second TG 132 is turned on (opened), each output selection control circuit 13 I is
The clock synchronization signal CK from the clock synchronization signal generation circuit 15 is selected and supplied to a corresponding predetermined logic circuit.

As a result, each logic circuit 12> (j=1 to m) is
Random operations are performed in response to a clock synchronization signal CK manually input from a corresponding output selection control circuit, generating internal heat and performing burn-in.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(1) Burn-in testing of integrated circuits becomes possible by adding a simple selection control signal generation circuit and output selection control section, so integrated circuits can be effectively used for their original logic circuit operations. .

(2) The external circuits added for testing only need to be clock signal and mode setting signal generation circuits, making it simple and highly reliable, thereby ensuring that the integrated circuit operates reliably. This can generate internal heat generation and improve the reliability of the test.

(3) It is possible to effectively use the integrated circuit for its original logic circuit operation by simply adding a simple selection control signal generation circuit and an output selection control section, so it is possible to use a small-scale integrated circuit with a relatively low degree of integration. It can also be applied to

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the basic configuration of the present invention, FIG. 2 is an explanatory diagram of the configuration of an embodiment of the invention, and FIG. 3 is a diagram of the flip-flop circuit (FF circuit) used in the embodiment. FIG. 2 is an explanatory diagram of the configuration. In FIGS. 1 to 3, 10... integrated circuit, 11 (11, to 11..)...
Flip-flop (FF) circuit, 12 (12, ~ 121
)...Logic circuit, 13 (13, to 13o)...Output selection control circuit, 14...Selection control signal generation circuit, 15
...Clock synchronization signal generation circuit.

Claims (1)

[Claims] 1. An internal logic circuit group of an integrated circuit including logic circuits (12_j, J=1 to m) operated by the outputs of flip-flop circuits (11_i, i=1 to n) is connected to each flip-flop circuit. (A) Each flip-flop circuit (12_i) is an integrated circuit with a built-in free-running function that operates randomly during a burn-in test using a clock supplied to each flip-flop circuit (11_i) to generate internal heat. ) is provided for each flip-flop circuit (12_i) and receives a clock synchronization signal synchronized with the output and clock from the corresponding flip-flop circuit (12_i),
According to the selection control signal from the selection control signal generation circuit (14), in the system operation mode, the output of the corresponding flip-flop circuit (11_i) is selectively controlled, and in the test mode, the clock synchronization signal is selectively controlled to generate the corresponding logic. An output selection control circuit (13_i, i=1 to n) supplied to the circuit, and (B) receiving a mode setting signal for setting the operation mode of the integrated circuit (10), each mode of the normal system operation mode and test mode. Generates a selection control signal corresponding to the setting signal state and controls each output selection control circuit (13_i, i=1 to n
) A selection control signal generation circuit (14) for supplying a selection control signal to an integrated circuit with a built-in self-running function.