JP2001215463A - Circuit and method for setting common output of lcd driver and semiconductor device for lcd driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a common output setting circuit of an LCD driver to easily set a common output state in a short time according to a test, and a setting method therefor. SOLUTION: This is a circuit for generating a signal pattern for testing a common output of an LCD driver, and is provided with a shift register SR controlled by a clock signal CLK consisting of plural registers 11 to be connected with the common output of the LCD driver, respectively, a logic circuit 12 arranged for each data transmission route of the shift register, and signal control circuits 131, 132 for giving a logic signal to a prescribed input of the logic circuit 12, and an output of the logic circuit 12 is set to a prescribed test signal pattern by the logic signal from control signal busses B1, B2, and is transmitted to each corresponding register 11 by a single clock signal CLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for an LCD (Liquid Crystal Display) driver, and more particularly to a LCD driver common for generating a common output test signal pattern for driving the LCD driver on the Y axis. The present invention relates to an output setting circuit, a setting method, and a semiconductor device for an LCD driver.

[0002]

2. Description of the Related Art In an LCD driver semiconductor device (LCD driver IC), a liquid crystal drive circuit in the X-axis direction is called a segment output, and a liquid crystal drive circuit in the Y-axis direction is called a common output. The common output has a lot of on / off drive control with respect to the segment output. In the common output system, a circuit that generates a common output control signal has a shift register configuration.

FIG. 4 is a circuit diagram showing a shift register for generating a common output control signal of a common output system in a conventional LCD driver. A register 41 composed of a plurality of D-type flip-flops connects a Q output and a D input to each other to form a shift register. Data for driving a common output is input to the D input. Each time the clock is input, the data is shifted, and a common output control signal Sout is obtained at the Q output of each register 41.

According to the above configuration, at the time of the common output test, clocks of the number of commons are input to the shift register, and the common output state is set according to the test. Thereby, the electrical characteristic test of the IC, for example, the on-resistance of the output transistor is measured to determine whether the resistance between the liquid crystal display device and the driver IC is within an allowable range, and the leakage between adjacent common outputs is measured.

[0005]

However, in order to set one test pattern for a common output test, it is necessary to input clocks (several hundred times) as many as the number of commons to the shift register. Further, an operation of resetting to the initial state is required to set another test pattern, which also requires the number of clocks equal to the number of commons. Thus, it takes time to set the common output state according to the test. As a result, the test cost is increased in the LCD driver, which is not preferable.

The present invention has been made in view of the above circumstances, and provides a common output setting circuit and a setting method of an LCD driver which can easily set a common output state according to a test in a short time. Is to do.

[0007]

A common output setting circuit of an LCD driver according to the present invention is a circuit for generating a signal pattern for testing a common output of an LCD driver, and includes a plurality of latches respectively connected to the common output of the LCD driver. A shift register including a circuit and controlled by a clock signal, a logic circuit provided for each data transmission path of the shift register, and a signal control circuit for providing a logic signal to a predetermined input of the logic circuit; An output of the logic circuit is set to a predetermined test signal pattern by a logic signal, and transmitted to each of the corresponding latch circuits.

A method of setting a common output of an LCD driver according to the present invention is a method of generating a signal pattern for testing a common output of an LCD driver, the method including a plurality of latch circuits each connected to the common output of the LCD driver and using a clock signal. A shift register to be controlled, a logic circuit provided for each data transmission path of the shift register, and a signal control circuit for providing a logic signal to a predetermined input of the logic circuit, wherein the signal control circuit has at least The latch circuit includes two control signal paths, and controls output of the logic circuit transmitted to each of the latch circuits according to a control signal supplied to the control signal path. A first pattern in which all are at a first logic level output, and all of the latch circuits are in a second pattern
A second pattern in which all the latch circuits are adjacently and alternately a first logic level output, a third pattern in which a second logic level output is obtained, and all the latch circuits which are opposite to the third pattern Are characterized by generating a fourth pattern in which the second logic level output and the first logic level output are alternately adjacent to each other by one clock input to the latch circuit.

According to the common output setting circuit and the setting method of the LCD driver of the present invention, the output of the logic circuit is controlled by the signal control circuit. Thus, desired data is simultaneously set to each of the latch circuits constituting the shift register by one clock input.

[0010] The semiconductor device for an LCD driver of the present invention comprises:
The above-mentioned common output setting circuit is provided.

[0011]

FIG. 1 is a circuit diagram showing a main part of a common output setting circuit of an LCD driver according to one embodiment of the present invention. A shift register SR including a plurality of latch circuits connected to the common output of the LCD driver, for example, a register 11 including a plurality of D-type flip-flops
Is configured. Data Din for driving a common output is input to the D input. Normally, data is shifted every time a clock is input, and a common output control signal Sout (shown as Sout1, Sout2 for convenience) is applied to the Q output of each register 11.
Is obtained.

A logic circuit 12 is provided for each data transmission path of such a shift register SR. Logic circuit 1
Reference numeral 2 includes an AND gate circuit AND having one input and output inserted into the data transmission path, and an OR gate circuit OR. In the first input of the gate circuit AND, data for driving a common output is input in the first stage, and thereafter, the Q output of each register 11 is supplied. The one input of the gate circuit OR is
The output of the gate circuit AND is supplied. Gate circuit OR
Are supplied to the D inputs of the corresponding registers 11.

Further, a signal control circuit 13 for providing a logic signal to a predetermined input of the logic circuit 12 is provided. The signal control circuit 13 includes two control signal buses B1 and B2. The signal control circuit 13 differs in the form of signal supply to the logic circuit 12 between the adjacent registers 11 and is denoted by signal control circuits 131 and 132.

Logic circuit 12 in signal control circuit 131
The form of signal supply to is as follows. Control signal bus B1
Is supplied to the other input of the gate circuit OR. The signal on the control signal bus B2 is inverted via the inverter IV1 and supplied to the other input of the gate circuit AND.

Logic circuit 12 in signal control circuit 132
The form of signal supply to is as follows. Control signal bus B1
Is inverted via an inverter IV2 and supplied to the other input N1 of the gate circuit AND. The signal on the control signal bus B2 is inverted via the inverter IV3 and supplied to the other input N2 of the gate circuit AND. Further, control signal buses B1,
An AND gate circuit AND132 having B2 as two inputs is provided. The output of this gate circuit AND132 is
The data is supplied to the gate circuit OR.

The common output setting circuit of the LCD driver according to the present invention has a shift register SR of a common output system as a main body, and the logic circuit 12 is inserted for each register 11.
It is in the form of a shift register in which the signal control circuits 131 and 132 are alternately combined.

FIG. 2 is a diagram showing a method of setting a common output control signal for the operation of the common output setting circuit of the LCD driver shown in FIG. First, in the normal mode, the logic circuit 12 must be used only as a signal transmission path of the shift register. By setting both the control signal buses B1 and B2 to "L" (low level), all the logic circuits 12 simply serve as a signal transmission path of the shift register (TEST0).

A common output control signal Sout (for convenience, Sout
In order to set all of the control signal buses B1 and B2 to "H" (indicated as 1 and Sout2) to "H" (high level). In this state, one clock CLK is input. As a result, the latch data of each register 11 is all “H”.
(TEST1).

A common output control signal Sout (for convenience, Sout
In order to set all the control signal buses B1 and L2 to "L", the control signal bus B1 is set to "L" and the control signal bus B2 is set to "H". In this state, one clock CLK is input. As a result, all the latch data of each register 11 becomes "L" (TEST2).

A common output control signal Sout (for convenience, Sout
1, Sout2) are alternately set to “H”, “L”, “H”... (Ie, Sout1 is set to “H” and Sout2 is set to “L”) for adjacent outputs. The signal bus B1 is set to "H" and the control signal bus B2 is set to "L".
In this state, one clock CLK is input. As a result, the latch data of each register 11 is set alternately between adjacent “H”, “L”, “H”.
T3).

A common output control signal Sout (for convenience, Sout
1 and Sout2) are alternately changed to “L”, “H”, “L”... (Ie, Sout1 is set to “L” and Sout2 is set to “H”) for the adjacent output. Is
From the state of TEST3, the control signal buses B1 and B2 are set to "L" and the data Din is set to "L". In this state, one clock CLK is input. Thereby, each register 11
Latch data of adjacent "L", "H", "L" ...
Are alternately set (TEST4).

The above TEST1 and TEST2 are used for DC test of IC such as ON resistance of output transistor and static power supply current test. The above TESTs 3 and 4 are used for, for example, checking for a short between adjacent common outputs.

FIG. 3 shows an LC according to an embodiment of the present invention.
FIG. 2 is a schematic diagram illustrating an example of a D driver IC. The LCD driver IC 31 is mounted together with an LCD (liquid crystal display) 33 such that the main surface side on which pads (not shown) are arranged faces the flexible substrate 32. LCD Driver I
C31 has a segment output for driving the X-axis of the LCD and a common output for driving the Y-axis. The signal input to the control signal buses B1 and B2 in the common output setting circuit of the LCD driver shown in FIG. 1 may be input from a pad or input by a command of a built-in CPU.

According to the above embodiment, the logic circuit 12 is provided in the shift register SR, and the output of the logic circuit 12 is controlled by the signal control circuit 13 (131, 132). The signal control circuit 13 includes two control signal buses B1 and B2, and adjacent registers 11 differently supply signals to the logic circuit 12 (signal control circuits 131 and 132). Thus, desired data is simultaneously set to each of the shift registers by one clock input. Therefore, the setting of the state of the common output is simplified as compared with the related art, which contributes to shortening of the test time.

[0025]

As described above, according to the present invention, the logic circuit is provided in the shift register which is the main body of the common output, and the output of the logic circuit is controlled by the signal control circuit. Thereby, desired data can be simultaneously set to each of the latches constituting the shift register by one clock input. Therefore, an LCD that can easily set the common output state according to the test in a short time
A driver common output setting circuit and setting method can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of a common output setting circuit of an LCD driver according to an embodiment of the present invention.

FIG. 2 is a diagram showing a method of setting a common output control signal for the operation of the common output setting circuit of the LCD driver shown in FIG.

FIG. 3 is an LCD driver I to which an embodiment of the present invention is applied.
It is an outline figure showing the example of C.

FIG. 4 is a circuit diagram showing a shift register that generates a common output control signal of a common output system in a conventional LCD driver.

[Explanation of symbols]

 11, 41 ... register 12 ... logic circuit 13, 131, 132 ... signal control circuit 31 ... LCD driver IC 32 ... flexible board 33 ... LCD (liquid crystal display) SR ... shift register B1, B2 ... control signal bus AND, AND132 ... AND gate circuit OR ... OR gate circuit IV1 to IV3 ... Inverter

Claims (6)

[Claims] 1. A circuit for generating a test signal pattern for a common output of an LCD driver, comprising: a shift register including a plurality of latch circuits each connected to a common output of the LCD driver and controlled by a clock signal; A logic circuit provided for each data transmission path, and a signal control circuit for providing a logic signal to a predetermined input of the logic circuit, wherein the logic signal causes an output of the logic circuit to a predetermined test signal pattern. A common output setting circuit for an LCD driver, which is set and transmitted to each of the corresponding latch circuits. 2. The signal control circuit includes at least two control signal paths, and generates the logic signal to the logic circuit according to a control signal supplied to the control signal path. A common output setting circuit for an LCD driver according to claim 1. 3. The signal control circuit according to claim 2, wherein a normal mode other than the generation and test of the test signal pattern by the logic circuit is performed in accordance with the control signal. The common output setting circuit of the described LCD driver. 4. A method for generating a test signal pattern of a common output of an LCD driver, comprising: a shift register including a plurality of latch circuits each connected to a common output of the LCD driver and controlled by a clock signal; And a signal control circuit for providing a logic signal to a predetermined input of the logic circuit, wherein the signal control circuit includes at least two control signal paths. An output of the logic circuit transmitted to each of the latch circuits is controlled in accordance with a control signal supplied to a control signal path, and all of the latch circuits have a first logic level output as at least the test signal pattern. A first pattern, a second pattern in which all of the latch circuits have a second logic level output, and a second pattern in which all of the latch circuits are adjacent Alternately a first logic level output, a third pattern according to a second logic level output, and a second logic level output the latch circuit all become opposite to the third pattern to the adjacent alternately,
A common output setting method for an LCD driver, wherein a fourth pattern that becomes a first logical level output is generated by one clock input to the latch circuit. 5. The LCD driver according to claim 4, wherein a normal mode other than the generation and test of the test signal pattern by the logic circuit is controlled according to the control signal to the signal control circuit. Common output setting method. 6. A semiconductor device for an LCD driver comprising the common output setting circuit according to claim 1. Description: