JPH06244343A - Semiconductor chip mounting device - Google Patents

Abstract

PURPOSE:To provide a semiconductor chip mounting device capable of increasing the number of tabs to be taken by restricting a space occupied by test pads to a minimum. CONSTITUTION:On a carrier 11 having an input line 12 and an output line 13 where a semiconductor chip 14 is directly mounted, gate means is provided for selecting each output one by one for a plurality of outputs from the semiconductor chip 14, a test pad 15 for short-circuiting the output lines, to which each output is given, is provided and the state of each output line 13 can be tested by the outputs appearing sequentially at this test pad 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TAB (Tape Automa) for directly mounting a semiconductor bare chip on a circuit board.
The present invention relates to a semiconductor chip mounting device to which the te Bonding method is applied.

[0002]

2. Description of the Related Art Recently, a hybrid technique has been realized as a component mounting technique in response to the demand for higher performance and smaller size of electronic equipment. As a method of mounting a semiconductor chip on a circuit board, a TAB method is used. Is used.

Conventionally, however, as shown in FIG. 4, there is one in which a semiconductor chip 4 is directly mounted on a film carrier 3 on which an input line 1 and an output line 2 are printed by using a TAB method.

In this case, it is necessary to inspect whether the output terminals of the semiconductor chip 4 and the respective output signals are correctly connected. Therefore, conventionally, the test pads 5 are connected to the respective output lines 2. Then, the output of each output line 2 is taken out through these test pads 5, and the connection state of each output line 2 is tested.

[0005]

However, in the case where the test pads 5 are connected to the respective output lines 2 in this way, the output lines 2 are increased due to the increase of the output terminals of the semiconductor chip 4.
When the number of test pads 5 increases, the number of test pads 5 also increases, so that the area occupied by the test pads 5 on the film carrier 3 becomes large, and the number of TABs taken is limited.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor chip mounting apparatus capable of increasing the number of TABs to be taken while minimizing the occupation of test pads.

[0007]

The present invention is a semiconductor chip mounting apparatus in which a semiconductor chip is directly mounted on a carrier having an input line and a plurality of output lines, and the semiconductor chip mounting apparatus is provided for a plurality of outputs of the semiconductor chip. A gate means for selecting one output at a time and a test pad for short-circuiting a plurality of output lines to which each output is applied are provided, and the state of each output line is tested by the output sequentially appearing on the test pad. It is configured to be possible.

[0008]

As a result, according to the present invention, a plurality of outputs from the semiconductor chip directly mounted on the carrier are taken out one by one through the gate means, and each output line is short-circuited by one test pad. Therefore, it becomes possible to test the state of each output line by the output that appears in sequence on the test pad. Even if the number of output lines increases due to the increase in output from the semiconductor chip, the number of test pads also increases. In addition, the area occupied by the test pad on the film carrier can be minimized.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic structure of the embodiment. In the figure, 11 is a film carrier, and this film carrier 11 has a plurality of input lines 12 and output lines 13.
Is printed. Then, the semiconductor chip 14 is mounted on such a film carrier 11 by the TAB method. In this case, a common test pad 15 is provided at the tip of each output line 13 on the film carrier 11,
The tip of each output line 13 is short-circuited.

On the other hand, when the semiconductor chip 14 is a signal electrode drive circuit for driving the signal electrodes of the liquid crystal display panel as an example, the determination circuit 14 shown in FIG.
1, output control timing circuit 142, shift register 1
43, a gate circuit 144, a level shifter 145, and an output amplifier 146.

The judgment circuit 141 is supplied with a control signal or a test signal for setting the semiconductor chip 14 in a certain state, and outputs a corresponding judgment signal. The output control timing circuit 142 generates a timing signal from the output of the shift register 143 and applies it to the output amplifier 146 when the determination signal from the determination circuit 141 is determined to be a test signal. Shift register 143, gate circuit 1
Reference numeral 44 and the level shifter 145 are for generating a signal electrode drive signal as a signal electrode drive circuit, and are adapted to generate outputs X1 to Xn via an output amplifier 146.

The output amplifier 146 is composed of a plurality of output amplifier / tri-state gates 1461 as shown in FIG.
1 to Xn are generated, and a timing signal from the output control timing circuit 142 is applied to each enable terminal.

Now, the test signal is now the decision circuit 1
When it is given to the signal 41, a corresponding decision signal is outputted from the decision circuit 141 and given to the output control timing circuit 142.

Then, when the output control timing circuit 142 determines that the determination signal from the determination circuit 141 is the test signal, it generates a timing signal and applies it to the output amplifier 146. In this case, the output control timing circuit 1
The timing signal 42 corresponds to the output from the shift register 143, and is applied so as to select each enable terminal of the plurality of tristate gates 1461 shown in FIG. 3 one by one.

As a result, the outputs X1 to Xn are sequentially set to the H level via the output amplifier 146. That is, one of the outputs X1 to Xn is selected at the H level, and the rest remains at the L level.

As a result, even if the tip of the output line 13 on the film carrier 11 is short-circuited by the test pad 15, the output appearing on the test pad 15 comes from each output line 13, By checking the outputs that sequentially appear on the test pad 15, each output line 13
It will be possible to test the condition of.

Therefore, in this way, the semiconductor chip 14 mounted on the film carrier 11 by the TAB method is used.
Outputs X1 to Xn from the tristate gate 1461
Output line 1
Since all the tip portions of 3 can be short-circuited by one test pad 15, even if the number of output lines increases due to the increase in the output of the semiconductor chip, the number of test pads does not increase, and the film The area occupied by the test pads on the carrier can always be minimized, and the number of TABs taken can be increased.

The test pad 15 which short-circuits each output line 13 is used when the test pad 15 is actually used after the test is completed.
Since it is cut off from the line A part, there is no problem after that.

The present invention is not limited to the above-mentioned embodiments, and can be carried out by appropriately modifying it without changing the scope of the invention.
For example, in the above description, the case of the signal electrode drive circuit for driving the signal electrode of the liquid crystal display panel as the semiconductor chip has been described, but the present invention can be applied to those used in other circuits.

[0021]

According to the present invention, a plurality of outputs from the semiconductor chip directly mounted on the carrier are taken out one by one through the gate means, and each output line is set to one.
Since it becomes possible to test the state of each output line by the output that appears on the test pad short-circuited by two test pads, even if the output from the semiconductor chip increases, the number of output lines increases. The number of pads does not increase, the area occupied by the test pads on the film carrier can be minimized, and the number of TABs taken can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a semiconductor chip of an example.

FIG. 3 is a diagram showing a schematic configuration of an output amplifier according to an embodiment.

FIG. 4 is a diagram showing a schematic configuration of a conventional example.

[Explanation of symbols]

11 ... Film carrier, 12 ... Input line, 13 ... Output line, 14 ... Semiconductor chip, 141 ... Judgment circuit, 142 ...
Output control timing circuit, 143 ... Shift register, 1
44 ... Gate circuit, 145 ... Level shifter, 146 ... Output amplifier, 15 ... Test pad.

Claims (1)

[Claims] 1. A semiconductor chip mounting apparatus in which a semiconductor chip is directly mounted on a carrier having an input line and a plurality of output lines, and gate means provided for a plurality of outputs of the semiconductor chip to select each output one by one. And a test pad that short-circuits a plurality of output lines to which the respective outputs are given, and a semiconductor chip mounting apparatus capable of testing the states of the respective output lines by the outputs that sequentially appear on the test pads.