JPH0552910A - System for testing signal propagation characteristic of high-speed logic unit - Google Patents

Abstract

PURPOSE:To measure the signal propagation characteristic between LSI devices without bringing a probe into direct contact with the leads of LSIs. CONSTITUTION:A logic LSI device 1 is provided with a test output terminal selection circuit 3, test signal input circuit 5, test function selecting signal input circuit 11, output selection circuits 7 and 8, and test signal input terminal (D). An other logic LSI device 2 is provided with a test input terminal selection circuit 10, test signal output circuit 12, input selection circuit 13, and test signal output terminal (R). Then a test signal is propagated through the terminal (D), a test output terminal A, a test input terminal A', and test signal output terminal (R) by respectively inputting the test signal, signal for selecting a test output terminal (A-N), and test function selecting signal and a signal for selecting a test input terminal (A'-N') connected to the test output terminal (A-N) and the test function selecting signal to the devices 1 and 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal propagation characteristic test system in a high speed logic unit having a plurality of logic LSI devices mounted on a printed circuit board.

[0002]

2. Description of the Related Art A connection test on a board between logic LSI devices (hereinafter abbreviated as LSI devices) in a logic unit used in a conventional high-speed computer is performed by bringing a probe of the test device into contact with a lead or a terminating resistor of the LSI device. This was done by measuring the VI characteristic at the contact point.

FIG. 5 is a diagram showing a conventional inter-terminal connection test method for a logic LSI device. In the figure, 100, 101
Is an LSI device, 102 is a terminating resistor, 110 is an output gate of the LSI device 100, and 111 is an input gate of the LSI device 101.

A is an output terminal of the LSI device 100, A'is an input terminal of the LSI device 101, and C is a measurement point of the connection test. In the configuration shown in the figure, for example, the LSI device 100,
In the state where the power supply voltage terminal 101 is grounded, a probe of a test device (not shown) is brought into contact with the measurement point C to measure the voltage-current static characteristic. Then, the connection state at the terminal A and the terminal B was estimated from the obtained voltage-current static characteristics to confirm the connection.

[0005]

By the way, with the increase in the number of surface-mount type LSI devices, there are cases in which the probe cannot directly contact the leads of the LSI device of the logic unit, and the terminating resistor is used. Since the number of transmission methods that do not use is increasing, the conventional test methods described above cannot be applied.

In addition, in the test method as described above, the LSI device may be destroyed by applying a voltage for measurement, and furthermore, the direct-current connection state can be estimated, but the LSI
It was not possible to measure the signal propagation characteristics between devices.

It is an object of the present invention to provide a test method for measuring signal propagation characteristics between LSI devices without directly contacting the leads of the LSI devices with a probe.

[0008]

According to the present invention, a terminal for inputting a test signal to an LSI device connected to one test external input terminal of an LSI device, a selected test output terminal, and its test output terminal. The path between the test input terminal of the other LSI device connected to and the test signal output terminal for outputting the test signal can be made flow-through. Then, the test signal input to one test signal input terminal of the LSI device propagates between the LSI devices and the other L
Since it is output to the test signal output terminal of the SI device, L
The signal propagation characteristic between terminals of the SI device was measured.

FIG. 1 shows the basic configuration of the present invention. In the figure, 1 is an LSI device, which has test output terminals A to N,
It has a test signal input terminal D. An LSI device 2 has test input terminals A ′ to N ′ and a test signal output terminal R. 3 is a test output terminal selection circuit, based on an address signal input from the outside,
This is to select the test output terminal for the signal propagation characteristic test. Reference numeral 4 is a test function selection signal input circuit for inputting a signal for selecting a test function. Reference numeral 5 is a test signal input circuit for inputting a signal for performing a signal propagation characteristic test. 6 is a logic circuit,
It is a logic circuit of the LSI device 1. Reference numeral 7 denotes an output selection circuit for outputting a test signal to the terminal A, which is selected by the output signal of the test output terminal selection circuit 3 and the test function selection signal is input to output the test signal to the terminal A. To do. An output selection circuit 8 selects the terminal N.

Reference numeral 10 is a test input terminal selection circuit,
The input terminal to be tested is selected by an address signal input from the outside. Reference numeral 11 is a test function selection signal input circuit for inputting a signal for selecting a test function. 12 is a test signal output circuit,
The test signal is output to the test signal output terminal R.
Reference numeral 13 is for outputting the input test signal input from the terminal A ′ to the test signal output circuit. Reference numeral 14 is an input selection circuit connected to the input terminal N '. Reference numeral 15 is a logic circuit.

[0011]

The operation of the configuration shown in FIG. 1 will be described. The test output terminal selection circuit 3 of the LSI device 1 receives an address signal for selecting the test output terminals A to N from an external terminal. For example, if the number of output terminals is n, the output selection circuits 7 to 8 are selected by an n-bit address signal. A test function selection signal is input to the test function selection signal input circuit 4 from an external terminal, and a signal for performing a propagation characteristic test is externally input from the test signal input terminal D. Then, the test function selection signal and the address signal for selecting the test output terminal are input to the respective output selection circuits 7-8, and in the output selection circuits 7-8,
The output selection circuit designated by the address signal switches the output to the test output circuit from the logic signal of the logic circuit 6 to the test signal.

On the other hand, in the LSI device 2, the test input terminal selection circuit (10) is driven by an address signal input from the outside.
Then, the test input terminals A'-N 'are selected. For example,
If the number of input terminals is n, it is addressed by an n-bit address signal. Further, a test function selection signal is externally input to the test function selection signal input circuit 11, and a test function selection signal is input to the input selection circuit 13. Then, in each of the input selection circuits 13 and 14, based on the test function selection signal, the test input terminals (A ′ to N ′)
The test signal input from is output to the test signal output terminal R.

As described above, the test signal input from the test signal input terminal D of the LSI device 1 passes through the test output terminal A of the D-LSI device 1-test input terminal A'-R of the LSI device 2. Propagate.

In the above structure, the LSI devices 1 and 2 are provided with respective circuits. However, only one test function selection signal input circuit is required in common.

[0015]

FIG. 2 shows the configuration of an embodiment of the present invention. In the figure, 20 is a high-speed logic unit, and 21 to 24 are LSI devices. Reference numerals 25, 27, and 29 are DV selection circuits, which are circuits that select a test output terminal for performing a signal propagation test and propagate a test signal. Reference numerals 26, 28 and 30 denote RV selection circuits which select a test input terminal for inputting a test signal to input a test signal and output a test signal output terminal (RV-OU).
The test signal is output to T).

TEST is a test function selection signal, and RV selection address is an RV to be tested from LSI devices 22 to 24.
It is an address signal for selecting the selection circuit. The DV selection address is an address signal for selecting the DV selection circuit of the LSI devices 21-23. DV-IN1, DV-IN2, D
V-IN3 is a test signal input terminal of the LSI devices 21, 22, and 23, respectively. RV-OUT2, RV-OUT
3, RV-OUT4 are LSI devices 22, 23, respectively.
24 test signal output terminals.

In the configuration shown in the figure, the LSI devices 21, 2
2 and 23 are the respective DV selection circuits 25, 27 and 29.
In, there is a terminal for inputting an address signal for selecting the test output terminal, but it is omitted in the figure. Also, LS
The I devices 22, 23, 24 are respectively connected to the respective RV selection circuits 2
6, 28 and 30 have terminals for inputting address signals for selecting test input terminals, which are omitted in the figure.

The operation of the configuration shown in the figure will be described. LSI device 2
A case where a test signal is output from the DV-IN1 of 1 to the RV-OUT2 of the LSI device 22 via the connection line A will be described.

The DV selection address is an address signal for selecting the DV selection circuit 25. Then, an address signal for selecting A as a test output terminal is input to the DV selection circuit 25 of the LSI device 21.

On the other hand, the RV selection address is the LSI device 22.
The RV selection circuit 26 is used as an address signal for selecting. Then, the RV selection circuit 26 of the LSI device 22 inputs the address signal for selecting the test input terminal connected to the wiring (connection line A) of the test input terminal A of the LSI device 22.

Then, the test function selection signal (TEST) is input to the DV selection circuit 25, and the test signal is input from DV-IN1. At the same time, the test function selection signal (TEST) is also input to the RV selection circuit 26. As a result, DV-
The test signal input from IN1 is output to the test signal output terminal RV-OUT2 via the connection line A.

FIG. 3 shows an embodiment of the DV selection circuit of the present invention. In the figure, 30 'is a DV selection circuit, 31 is a test signal input circuit, 32 is an output selection circuit A, 33 is an output selection circuit N, and 34 is a test output terminal selection circuit, which is composed of a decoder. Reference numeral 35 is a test function selection signal input circuit, and 36 is a logic circuit of the LSI device.

Reference numeral 40 is a gate for inputting a test signal, and 41 is an AND circuit for inputting the negation of the test function selection signal and the output of the logic circuit 36. An AND circuit 42 inputs a test signal, a test output terminal selection signal (output of the test output terminal selection circuit 34), and a test function selection signal. Reference numeral 43 denotes an OR of the outputs of the OR circuits 41 and 42.

The operation of the configuration shown in the figure will be described. The case where the DV selection circuit 30 'shown in the figure is selected by the DV selection address and the output terminal A is selected as the test output terminal will be described.

An address signal for selecting the terminal A as a test output terminal is input to the test output terminal selection circuit 34,
A selection signal (high signal) is input to the AND circuit 42. At the same time, the test signal (DV-IN, high signal) is input to the AND circuit 42 via the test signal input circuit 31. The test function selection signal (TEST, high) is input to the AND circuit 42 via the test function selection signal input circuit 35. As a result, the test signal is output from the AND circuit 42 of the output selection circuit A (32).

On the other hand, since the negation (low) of the test function selection signal (TEST) is input to the AND circuit 41, the output of the logic circuit 36 input to the AND circuit 41 is canceled. As a result, a test signal is output to the test output terminal A via the OR circuit 43.

When the test function is not selected,
Since the test function selection signal (TEST) is low, the output low of the AND circuit 42 is input to the OR circuit 43. At that time, since the negative (high) of the test function selection signal (TEST) is input to the output selection circuit A (32), the output of the logic circuit 36 is output from the AND gate 41 and the OR circuit 43. It is output to the test output terminal A.

FIG. 4 shows an embodiment of the RV selection circuit of the present invention. In the figure, 50 is an RV selection circuit, 51 is a test function selection signal input circuit, and 52 is an input selection circuit for outputting a test signal to a test signal output circuit 53. 5
A test signal output circuit 3 outputs a test signal (test output signal RV-OUT). A test input terminal selection circuit 54 selects a test input terminal to which a test signal is input. Reference numeral 55 is a logic circuit of the LSI device.

Reference numeral 56 is a gate for inputting a test function selection signal (TEST), and 57 and 58 are AND circuits, which are output to the test input terminal A to N and the test input terminal selection circuit 54, respectively. A selection signal is input. Reference numeral 59 is an OR circuit, which takes the OR of the output from the input selection circuit 52. An AND circuit 60 receives the output of the OR circuit and the test function selection signal (TEST).

The operation of the configuration shown in the figure will be described. A case where the RV selection circuit 50 in the figure is selected by the RV selection address and the input terminal A is selected as the test input terminal will be described.

An address signal for selecting the input terminal A as a test input terminal is input to the test input terminal selection circuit 54, and the test output terminal A is selected. As a result, a high test signal input from the test input terminal A and a high signal output from the test input terminal selection circuit 54 are input to the AND circuit 57, and a high signal is input to the OR circuit 59. ..

On the other hand, the test function selection signal (TEST, high) and the output (high) of the OR circuit 59 are input to the AND circuit 60, and the test signal output circuit outputs the test signal (RV-
OUT) is obtained.

When the test function selection signal (TEST) is low, the output of the AND circuit 60 is low and the test signal output circuit 53 does not output the input signal from the test input terminal A.

[0034]

According to the present invention, a flow-through circuit for connecting a test signal input terminal, a terminal connecting the LSI device, and a test signal output terminal can be constructed by a signal input to the LSI device from the outside. By inputting a test signal to the LSI device without directly contacting the terminals with the probe, a connection test and a propagation characteristic test between the LSI devices can be easily performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 3 is a diagram showing an embodiment of a DV selection circuit of the present invention.

FIG. 4 is a diagram showing an embodiment of an RV selection circuit of the present invention.

FIG. 5 is a diagram showing a conventional inter-terminal connection test method for a logic LSI device.

[Explanation of symbols]

 1 and 2: LSI device 3: Test output terminal selection circuit 4: Test function selection signal input circuit 5: Test signal input circuit 6: Logic circuit 7, 8: Output selection circuit 10: Test input terminal selection circuit 11: Test function selection Signal input circuit 12: Test signal output circuit 13, 14: Input selection circuit 15: Logic circuit

Claims (1)

[Claims] 1. In a high-speed logic unit having a plurality of logic LSI devices (1) and (2) mounted, a logic LSI device (1) on the side of inputting a test signal is controlled by a selection signal given from the outside. Test output terminal selection circuit (3) that selects the test output terminals (A to N), test signal input circuit (5) that inputs the test signal, and test function selection signal input circuit (4 that inputs the test function selection signal ), An output selection circuit (7, 8) for outputting a test signal to the selected test output terminals (A to N), and a test signal input terminal (D), and a logic LSI on the side for outputting the test signal. The device (2) includes a test input terminal selection circuit (10) for selecting the test input terminals (A 'to N') by an externally applied signal and a test function selection signal input circuit (11) for inputting the test function selection signal. )When,
A test signal output circuit (12) that outputs a test signal, an input selection circuit (13) that inputs the test signal input from the test input terminals (A 'to N') to the test signal output circuit (12), and a test A logic L that has a signal output terminal (R) and inputs a test signal
The test signal and the signal for selecting the test output terminals (A to N) and the test function selection signal are input to the SI device (1), and the test output terminal ( A-N) connected to test input terminals (A'-
N ') selection signal and test function selection signal are input,
The test signal input terminal (D) and the test output terminal (A to
N), the test input terminals (A 'to N'), and the test signal output terminal (R) are propagated to carry out a test signal propagation characteristic test between terminals of the logic LSI device. Signal propagation characteristics test method in logic unit.