JP2002005999A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor testing device allowing high-speed testing of a measured device with low drive ability. SOLUTION: In this semiconductor testing device, a socket means is arranged in a performance board electrically connectable to a test head by means of a contact means, and a DUT for the measured device is mounted in the socket means for performing a test according to a program. In this semiconductor testing device, a switching means turning on/off an input/output signal from the DUT according to the program, an input buffer for the DUT, and an output buffer for the DUT are arranged in the performance board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor test apparatus for testing a DUT having a small drive capability at a high speed.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. First, the configuration and operation of a semiconductor test apparatus for testing a DUT of a device under test will be described.
As shown in FIG. 3, the configuration of a conventional semiconductor test apparatus includes a workstation 10, a main frame 20, a test head 30, and a performance board 40. Then, the semiconductor test apparatus tests the DUT 60 of the device under test mounted on the IC socket 50 provided on the performance board 40.

[0003] The workstation 10 is an input / output means that serves as an interface between the semiconductor test apparatus and a person.

The main frame 20 includes units such as a power supply unit of a semiconductor test apparatus, a computer, a test signal generation unit, a signal measurement unit, and a logical comparator.

The test head 30 includes an electronic circuit having a function corresponding to the number of test channels.

[0006] The performance board 40 is detachable from the test head 30 by contact means, and the signals of the electronic circuit of the test head 30 are electrically connected to the respective pins of the IC socket 50.

The IC socket 50 is connected to the device under test DU.
Socket means corresponding to the type of T60, package, and the like.

Next, an example of the internal configuration of the semiconductor test apparatus will be briefly described with reference to FIG. In the main frame 20, a signal generator 22 and a UD of a DC tester are used.
C23, a logical comparator 24, each unit such as a digitizer 25, and a CPU 25 of a processor are connected by a bus cable to perform program control.

The test head 30 includes pin electronics 36 and 37, a motherboard 34, and a contact board 32. And the main frame 20
Each of the units is connected to the pin electronics 36, 37 by a signal via a cable, and the pin electronics 36, 37 are connected.
Is connected to the motherboard 34 by a connector 35,
The motherboard 34 and the contact board 32 are signal-connected by a coaxial cable 33, and the contact board 32 and the performance board 40 are signal-connected by pogo pins 31.

The performance board 40 is detachable by pressing the pogo pins 31 of the contact means against the pads of the substrate so as to be detachable and replaceable. As shown in FIG. 5, in the circuit of the performance board 40, signals with the pin electronics 36 and 37 are connected to the IC socket 50 of the socket means by pattern wiring.

The pin electronics 36 and 37 are composed of electronic circuits having functions corresponding to the number of test channels, but have two channels for simplification of the drawing. For example, since the number of test channels of a semiconductor test device is 1000, there are a corresponding number of pin electronics and contact means. Further, as shown in FIG. 4, the pin electronics 36 includes a gain variable circuit 71.
, A buffer 73, and relays S1, S2, S3.
, A buffer 74, relays S4 and S5, and a comparator 75.

Next, referring to FIG.
An example of the operation of testing the DUT 60 mounted on the CAM will be described. For example, when performing a DC test, a predetermined voltage programmed from the UDC 23 of the DC tester is generated, the relay S1 is turned off, the relays S3 and S2 are turned on, and a voltage is applied to the test pins of the DUT 60. Measure with

When an AC test is performed, a programmed high-frequency signal is generated from a signal generator 22, amplified or attenuated to a desired level by a gain variable circuit 71, and output to a buffer 73. The high-frequency signal received by the buffer 73 is subjected to offset control, set in a programmed level range of a predetermined high voltage (+ V) and a predetermined low voltage (−V), and output. The output signal of the buffer 73 is such that the relays S1 and S2 are turned on, the relay S3 is turned off, and the DUT 6
0 input pin.

When the signal at the output pin of the DUT 60 is a logic signal, the relay S4 is turned on and the relay S5 is turned off, and the level of the digital signal output by the comparator 75 is compared with the expected value by the logical comparator 24. And pass /
Determine the failure.

If the signal at the output pin of the DUT 60 is an analog signal, the relay S4 is turned off and the relay S5 is turned on, and the signal received by the buffer 74 is offset-controlled and programmed to a predetermined high voltage (+ V). , And the low voltage (-V) level range and output. The output signal of the buffer 74 is amplified or attenuated to a desired level by the variable gain circuit 72 and output to the digitizer 25. The digitizer 25 converts an analog signal into a digital signal for arithmetic processing.

Next, the program control of the pin electronics 36 and 37 will be described. In the pin electronics 36 and 37, the gain control of the gain variable circuits 71 and 72 and the power supply voltages (+ V, −
V) and offset voltage, and program control such as ON (make) / OFF (break) of the relay. For example, as shown in FIG. 6, the control of the relays S1 to Sn of the switching means for switching the signals is performed by executing a program in the CPU 21 and sending the relays S1 to S1 from the relay control circuit 76.
The outputs of the Sn relay drivers 81 to 8n are respectively controlled to low / high levels to turn on the relays S1 to Sn, respectively.
/ OFF.

In a conventional semiconductor test apparatus, the performance board 40 is tested by attaching and detaching and replacing it in accordance with the type and package of the device to be measured. Also, DU
Input / output signal buffers 73 and 7 for testing T60
Since 4 is provided in the pin electronics 36 and 37, respectively, the circuit of the performance board 40 can be relatively simple as shown in FIG. 5, for example. However, semiconductors such as ICs used in recent high-density wired mobile phones have a small output drive capability and high speed because components are arranged close to each other.

For example, a conventional semiconductor has a drive capability of 50 mA or more, but a drive current of a recent semiconductor is about 1 mA. The slope dV / dt of the rising waveform is expressed by the following equation (1). dV / dt = i / C (1) where i: drive current C: load capacity

Therefore, when a semiconductor is tested at high speed, DU
It is desirable that the load capacitance between the T pin and the input / output buffer be small. However, the conventional semiconductor test apparatus has a coaxial cable from the DUT 60 to the input / output buffer and a wiring pattern wiring of about 1 m, and has a load capacity of 100 m.
There is about pF. Therefore, when the drive current is reduced, the output waveform becomes dull due to the load capacitance due to the coaxial cable and the wiring pattern, and the high-speed test cannot be easily performed.

[0020]

As described above, in the conventional semiconductor test apparatus, the coaxial cable from the DUT 60 to the input / output buffer and the wiring pattern wiring are about 1 m, and the load capacitance is about 100 pF. Therefore, there is a practical problem that the output waveform becomes dull due to the load capacitance of the coaxial cable and the wiring pattern wiring, and a high-speed test cannot be easily performed. The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor test apparatus capable of performing a high-speed test of a device to be measured having a small drive capability.

[0021]

That is, a first object of the present invention to achieve the above object is to provide a performance board which can be electrically connected to a test head by a contact means, and the socket means is provided with a device to be measured. In a semiconductor test apparatus in which a DUT of a device is mounted and a test is performed by a program, a switching unit capable of ON / OFF of a test signal by a program and a buffer of an output signal of the DUT are provided on the performance board. The gist is a semiconductor test device.

In order to achieve the above object, a second aspect of the present invention is to provide a performance board which can be electrically connected to a test head by a contact means, and to mount a DUT of a device under test on the socket means. In a semiconductor test apparatus for testing by a program using a program, a switching means for turning on / off a DUT input / output signal by a program, a buffer for an input signal of the DUT, and a buffer for an output signal of the DUT are provided on the performance board. The gist is a semiconductor test apparatus characterized by the above.

According to a third aspect of the present invention, a control signal for the switching means and a voltage control signal for the buffer are supplied from the test head side to the performance board via the contact means. The gist of the present invention is a semiconductor test apparatus according to the first or second aspect of the present invention, which is controlled by a program.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. The main configuration and operation of the semiconductor test apparatus for testing the DUT of the device under test are the same as those of the prior art shown in FIG. As shown in FIG. 2, the main frame 20 of the semiconductor test apparatus of the present embodiment has the same configuration example as the conventional one, and the test head 30 has pin electronics 38, 39.
, Motherboard 34 and contact board 32.

As in the conventional case, each unit of the main frame 20 is connected to the pin electronics 38 and 39 by a signal, a signal is connected to the pin electronics 38 and 39 and the motherboard 34 by a connector 35, and the motherboard 34 is contacted. Board 32 is coaxial cable 3
3, the contact board 32 and the performance board 41 are signal-connected by the pogo pins 31. In addition, the performance board 41 is configured such that the pogo pins 31 of the contact means are brought into contact with the pads of the substrate by pressing and contacting the pads, so that the pads can be detached and replaced.

In the semiconductor test apparatus of this embodiment, an electronic circuit having a function corresponding to the number of test channels is constituted by pin electronics 38 and 39 and a performance board 41. As shown in FIG. 2, the pin electronics 38 includes a variable gain circuit 71 and pattern wiring, and the pin electronics 39 includes a variable gain circuit 72 and pattern wiring.

On the other hand, as shown in FIG. 1, the performance board 41 includes a buffer 73 and relays S1, S2, and S2.
3, IC socket 50, buffer 74, and relay S
4, S5 and a comparator 75.

Next, control of the electronic circuits of the pin electronics 38 and 39 and the performance board 41 will be described. Among the components of the conventional pin electronics 36 and 37, the components driven or driven directly by the high-speed signals with the input / output pins of the DUT 60 are constituted by the performance board 41. Therefore, the power supply voltages (+ V,-) of the buffers 73, 74 of the performance board 41
V) and the offset voltage, and ON (make) / OFF (break) control of the relays S1, S2, S3, S4, and S5 of the switching means for switching the signals. However, since the control signals of the components of the performance board 41 do not require high speed, the control circuit itself is provided on the test head 30 side, and although not shown in FIG. 33, the contact board 32, and the pogo pin 31 to transmit the data to the performance board 41. On the other hand, the gain variable circuit 7
1, 72 are pin electronics 38 as before,
Although not shown in FIG. 2, the gain control signal is supplied to the pin electronics 38 and 39 as in the prior art.

Next, an example of an operation for testing the DUT 60 mounted on the IC socket 50 will be described with reference to FIGS. For example, when performing a DC test, a predetermined voltage programmed by the UDC 23 of the DC tester shown in FIG. 2 is generated, and the relay S1 shown in FIG.
The relays S3 and S2 are turned on, a voltage is applied to the test pins of the DUT 60, and the flowing current is measured by the UDC23.

When an AC test is performed, a signal from the signal generator 22 shown in FIG. 2 is amplified or attenuated to a desired level by a variable gain circuit 71 and output to a buffer 73 shown in FIG. The signal received by the buffer 73 is subjected to offset control, and a predetermined high voltage (+
V) and the low voltage (-V) level range. The output voltage of the buffer 73 is determined by the relays S1, S
2 is turned on and the relay S3 is turned off, and is given to the input pin of the DUT 60.

When the signal at the output pin of the DUT 60 is a logic signal, the relay S4 shown in FIG.
Is turned off, and the digital signal output from the comparator 75 after level comparison is logically compared with the expected value by the logical comparator 24 shown in FIG. 2 to determine pass / fail.

When the signal at the output pin of the DUT 60 is an analog signal, the relay S4 shown in FIG.
5 is turned on, the signal received by the buffer 74 is offset-controlled, and a predetermined high voltage (+
V) and the low voltage (-V) level range. The output signal of the buffer 74 is amplified or attenuated to a desired level by the variable gain circuit 72 shown in FIG. The digitizer 25 converts an analog signal into a digital signal for arithmetic processing.

In the semiconductor test apparatus of the present invention, the DUT
I / O signal buffers 73 and 74 for testing
And the signal switching relay is provided on the performance board 41, so that the input / output buffer 7
The length of the wiring pattern up to 3, 74 is 5 cm each
Can be shortened to about 10 cm.

By the way, as described in the prior art, the slope dV / dt of the rising waveform is expressed by the following equation (2). dV / dt = i / C (2) where i: drive current C: load capacity In the above equation (2), a recent semiconductor drive current i
Is several tenths of the conventional one, but in the semiconductor test apparatus of the present invention, the load capacitance C between the pin of the DUT 60 and the input / output buffer is set to be several tenths or less of the conventional one. Can be easily done. Therefore, the slope dV / dt of the rising waveform of the semiconductor test apparatus of the present invention has a relatively small i / C, so that the drive capability is small.
In addition, a high-speed semiconductor test can be realized.

When the input / output buffers and relay means of the DUT 60 provided on the performance board 41 are used in a plurality of channels, they can be miniaturized and high-density mounting by modularizing them, and are provided inside the IC socket. As a result, the distance between the pins of the DUT 60 and the buffer can be reduced to further increase the speed. In the performance board 41, a switching relay for diagnosing the timing and level of the system can be similarly mounted. Note that, in this embodiment, the D
The UT 60 has been described with one case.
If the number of channels is sufficient, it is also possible to provide a buffer for input / output of a plurality of DUTs and a switching relay on a performance board to simultaneously measure and test.

[0037]

The present invention is embodied in the form described above and has the following effects. That is,
Since the input / output signal buffer for testing the DUT and the signal switching relay are provided on the performance board, the length of the wiring pattern from the DUT to the input / output buffer can be shortened. However, there is an effect that a test of a semiconductor with reduced drive capability and a high speed can be easily realized.

[Brief description of the drawings]

FIG. 1 is a main part circuit diagram of a semiconductor test apparatus of the present invention.

FIG. 2 is a main part circuit diagram of the semiconductor test apparatus of the present invention.

FIG. 3 is a configuration diagram of a semiconductor test apparatus.

FIG. 4 is a main part circuit diagram of a conventional semiconductor test apparatus.

FIG. 5 is a main part circuit diagram of a conventional semiconductor test apparatus.

FIG. 6 is a control circuit diagram of the semiconductor test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Workstation 20 Main frame 30 Test head 31 Pogo pin 32 Contact board 33 Coaxial cable 34 Motherboard 35 Connector 36, 37, 38, 39 pin electronics 40, 41 Performance board 50 IC socket 60 DUT 71, 72 Gain variable circuit 73, 74 Buffer 75 Comparator 76 Relay control circuit 81-8n Relay driver

Claims (3)

[Claims] 1. A semiconductor test apparatus in which a socket is provided on a performance board which can be electrically connected to a test head by a contact, and a DUT of a device under test is mounted on the socket and a test is performed by a program. A semiconductor test apparatus comprising: a switching unit capable of performing the program by a program; and a buffer for a DUT output signal, provided on the performance board. 2. A semiconductor test apparatus in which a socket is provided on a performance board which can be electrically connected to a test head by a contact, and a DUT of a device under test is mounted on the socket and a test is performed by a program. A semiconductor test apparatus, comprising: a switching unit capable of performing the following by a program; a buffer for an input signal of the DUT; and a buffer for an output signal of the DUT, provided on the performance board. 3. A control signal of the switching means, a voltage control signal of the input buffer of the DUT, and a voltage control signal of the output buffer of the DUT are supplied from the test head side to the performance board through the contact means, and are programmed. 3. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is controlled.