WO2007018020A1

WO2007018020A1 - Semiconductor testing apparatus

Info

Publication number: WO2007018020A1
Application number: PCT/JP2006/314347
Authority: WO
Inventors: Nobusuke Seki
Original assignee: Advantest Corporation
Priority date: 2005-08-09
Filing date: 2006-07-20
Publication date: 2007-02-15
Also published as: KR101088203B1; JP5038137B2; KR20090061083A; JPWO2007018020A1; TWI317814B; KR20080014995A; TW200712521A

Abstract

A semiconductor testing apparatus in which measurement accuracy is prevented from being reduced and the number of to-be-tested devices that can be simultaneously measured is increased. The semiconductor testing apparatus has a driver DR for inputting a signal to a pin of DUTs (200), a signal line connected at one end to the output end of the driver DR and having connection points provided in the middle of the signal line, and a termination resistor (28) connected to the other end of the signal line. The connection points provided in the signal line are respectively connected to the DUTs (200).

Description

Specification

Semiconductor test equipment

Technical field

The present invention relates to a semiconductor test apparatus that performs a function test on a plurality of devices under test.

Background art

Conventionally, when performing a functional test on a plurality of devices under test using a semiconductor test apparatus, the output side of one driver is branched to connect the two devices under test, and these two devices under test are connected. A method is known in which a common test pattern is simultaneously input to a test device from one dryno (see, for example, Patent Document 1). It is possible to perform functional tests on the device under test.

Patent Document 1: Japanese Unexamined Patent Publication No. 2000-292491 (Page 2-6, Fig. 1-5)

Disclosure of the invention

Problems to be solved by the invention

[0003] By the way, in the method disclosed in Patent Document 1, for example, if the impedance of the signal line connected to the output end side of the driver is 50 Ω, each of the two signal lines as branch destinations is provided. The impedance must be 100 Ω. Theoretically, if the impedance of the signal line at the branch destination is set to 200 Ω and four signal lines are used, matching can be achieved with the 50 Ω signal line connected to the output side of the driver. In addition, functional tests can be performed on many devices under test with a small number of drivers. However, in reality, the upper limit of the wiring impedance of the socket board that electrically connects the device under test is about 100 Ω, and the device under test that can perform functional tests at the same time as the number of branches There was a problem that the number of people could not be increased. On the other hand, if the number of branches is set to 4 or more using such a low-impedance signal line, signal reflection occurs due to impedance mismatch and the signal waveform is disturbed, so that the measurement accuracy decreases. There's a problem. [0004] The present invention was created in view of the above points, and its purpose is to prevent a decrease in measurement accuracy and to increase the number of devices under test that can be simultaneously measured. To provide an apparatus.

Means for solving the problem

In order to solve the above-described problems, a semiconductor test apparatus according to the present invention includes a driver for inputting an applied signal to be used for testing to a pin of a device under test, and one end connected to an output terminal of the driver. A signal line having a plurality of connection points provided in the middle and a termination resistor connected to the other end of the signal line, and connecting each of a plurality of devices under test to each of the plurality of connection points. Yes. This makes it possible to connect multiple devices under test to the signal line without increasing the impedance of the signal line, so there is no restriction due to the impedance of the signal line, and the number of devices under test that can be measured simultaneously is reduced. Can be increased.

[0006] Further, the apparatus further includes a test signal waveform generating means for generating a signal waveform necessary for the functional test of the device under test described above, receives the signal waveform, generates an applied signal with a driver, and generates the generated applied signal as a signal. It is desirable to input to each of multiple devices under test connected to the track. As a result, it is possible to input a common applied signal to the devices under test whose number has been increased and simultaneously perform a function test.

[0007] Further, it is desirable to match the output impedance of the driver, the impedance of the termination resistor, and the impedance of the signal line. As a result, the disturbance of the signal waveform due to the reflection of the signal output from the driver can be prevented, and the degradation of measurement accuracy can be prevented. For example, if the output impedance of the driver is 50 Ω, the signal line impedance is also set to 50 Ω. Such a signal line is easy to realize, and the number of devices under test that are subject to simultaneous measurement. This makes it possible to increase the amount of calories and prevent the measurement accuracy from being lowered, and to facilitate manufacturing.

[0008] In addition, the above-described pin eletronics on which a driver channel having a driver and a terminating resistor is mounted, and a pin electronics, forming part of a signal line connected to each of the driver and the terminating resistor are formed. A mother board wired with a coaxial cable and a device connected to the mother board with multiple devices under test, It would be desirable to have a socket board with wiring that forms part of the track. This makes it possible to simultaneously test many devices under test without increasing the impedance of the wiring inside the socket board more than necessary.

[0009] In addition, a DC power source that generates at least one of the voltage and current necessary for the DC test of the device under test described above, a first switch that connects the DC power source to the signal line, a dryer, and a signal line It is desirable to further include a second switch that is inserted between the two and opens and closes the track. This makes it possible to selectively perform both functional tests and DC tests on multiple devices under test using the same signal line.

[0010] Further, the semiconductor test apparatus of the present invention includes a driver for a plurality of channels for inputting an applied signal to be used for testing to a pin of a device under test, and one end connected to an output terminal of the driver. A signal line having a connection path that is sequentially connected in series to the corresponding pins of the device under test, and the signal lines that are sequentially connected in series between the devices under test have the same propagation length in each of the plurality of channels. The amount of delay is set. By making the wiring length of the signal line of each channel the same and making the same propagation delay time, individual timing control becomes unnecessary.

[0011] Further, it is desirable to further include a termination resistor connected to the other end of the signal line connected to the driver described above. Thereby, reflection of a signal can be suppressed.

[0012] Further, the socket board of the present invention is provided in the above-described semiconductor test apparatus, has a plurality of devices under test, and has signal lines for sequentially connecting corresponding pins of the plurality of devices under test in series. I have. By using such a socket board, it becomes possible to connect a plurality of devices under test to the signal line without increasing the impedance of the signal line, and to increase the number of devices under test that can be measured simultaneously. it can.

[0013] In addition, the timing generated in the applied signal applied to each pin of the device under test corresponding to the amount of propagation delay associated with the wiring length of the signal line sequentially connecting the plurality of devices under test in series. Based on the delay, it is desirable to adjust the delay timing for the IO channel connected to each IO pin of multiple devices under test. This makes it possible to adjust the timing for capturing the output signal of each device under test in accordance with the difference in the input timing of the applied signal. o

[0014] In addition, the adjustment of the delay timing for the IO channel described above cancels the difference in propagation delay amount due to the difference in wiring length of the signal line for the second driver provided in the IO channel. In addition to setting the delay amount, it is desirable to set a delay amount that offsets the difference in propagation delay amount due to the difference in signal line length for the comparator provided in the IO channel. This makes it possible to adjust the timing of both the driver and comparator provided in each IO channel.

Brief Description of Drawings

FIG. 1 is a diagram showing an overall configuration of a semiconductor test apparatus according to an embodiment.

FIG. 2 is a diagram showing a connection state between a driver channel and IO channel in the pin electronics and the DUT.

FIG. 3 is a diagram showing a modified example of a driver channel that can support both a functional test and a DC test.

FIG. 4 is a diagram showing a configuration of a modified example having a branch.

FIG. 5 is a diagram showing a modified connection configuration without using a termination resistor.

Explanation of symbols

Semiconductor test equipment body

12 Tester control unit

14 Timing generator

16 pattern generator

18 Data selector

20 Format controller

22 pin electronics

24, 24A, 24B Driver channel (Dch)

26 IO channel (IOch)

28, 28B termination resistor

30 Motherboard

32 Coaxial cable

40 socket board 60 workstation

200 DUT (device under test)

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a semiconductor test apparatus according to an embodiment to which the present invention is applied will be described in detail. FIG. 1 is a diagram illustrating an overall configuration of a semiconductor test apparatus according to an embodiment. This semiconductor test equipment includes a semiconductor test equipment main body 10 and a workstation 60 in order to perform various tests such as functional tests and DC tests on a plurality of DUTs (devices under test) 200. ing. The workstation 60 controls the entire series of test operations such as functional tests and timing 'calibration operations, and realizes an interface with the user. As the DUT 200, various semiconductor devices such as semiconductor memories and logic ICs can be considered.

[0018] The semiconductor test apparatus body 10 performs various tests on the DUT 200 by executing a predetermined test program transferred from the workstation 60. For this purpose, the semiconductor test apparatus body 10 includes a tester control unit 12, a timing generator 14, a pattern generator 16, a data selector 18, a format control unit 20, and pin electronics 22. These tester control unit 12, timing generator 14, pattern generator 16, data selector 18 and format control unit 20 correspond to the test signal waveform generating means.

[0019] The tester control unit 12 is connected to each component such as the timing generator 14 via a bus, and by executing the test program transferred from the workstation 60, the tester controller 12 controls each component. Control necessary for various test operations.

[0020] The timing generator 14 sets a basic period of the test operation and generates various timing edges included in the set basic period. The pattern generator 16 generates various pattern data. The data selector 18 assigns the logical pin numbers, which are various pattern data output from the pattern generator 16, to the physical pin numbers of the DUT 200 and associates them. The format control unit 20 performs waveform control applied to the DUT 200 based on the pattern data generated by the no-turn generator 16 and selected by the data selector 18 and the timing edge generated by the timing generator 14. .

[0021] The pin electronics 22 is used to physically interface the DUT 200. Based on the waveform signal FD and strobe signal STB generated by the waveform control of the format control unit 20, a signal that is actually input / output from / to the DUT 200 is generated. For this purpose, the pin electronics 22 includes a plurality of driver channels (Dch) 24 and a plurality of IO channels (IOch) 26. In general, the pin electronics 22 is housed in a dedicated test head and has a structure that can be separated from the apparatus main body.

[0022] The driver channel 24 generates an actual test waveform that is input to the driver pins of the DUT 200. For this purpose, the driver channel 24 includes a driver DR and a variable delay element VD that adjusts the timing of the waveform signal FD input to the driver DR. Here, the “dry pin” is a pin that only applies a test waveform to the DUT 200, such as an address pin of a memory device and various control pins. The driver DR passes the waveform signal FD output from the format control unit 20 through the variable delay element VD and applies a test waveform delayed to an arbitrary timing to the DUT 200. The variable delay element VD may be provided in the format control unit 20.

[0023] The IO channel 26 generates an actual test waveform to be applied to the IO pin of the DUT200, and also receives the response signal that is actually output from the IO pin force and performs timing determination in synchronization with the strobe signal STB. . For this purpose, the IO channel 26 adjusts the timing of the driver DR and the variable delay element VD that adjusts the timing of the waveform signal FD input to the driver DR, and the timing of the comparator CP and the strobe signal STB input to the comparator CP. And a variable delay element VD to be adjusted. Here, the “IO pin” is an input Z output pin, which is a pin for applying a test waveform and determining the timing of a response signal like a data pin of a memory device. The comparator CP samples the response signal at a timing based on the strobe signal STB output from the format control unit 20 and input via the variable delay element VD, and determines whether the sampled signal is good or bad in the subsequent stage. Supply to a circuit (not shown).

In addition, a mother board 30 that mediates between the socket board 40 and the pin electronics 22 is mounted on the semiconductor test apparatus main body 10, and the coaxial cable 32 in the mother board 30 is connected to the mother board 30. The pin electronics 22 described above is connected to the socket board 40. The socket board 40 has multiple DUTs 200 mounted via IC sockets (not shown). Wiring for connecting these DUT200 driver pins and IO pins to the mother board 30 is provided.

FIG. 2 is a diagram illustrating a connection state between the driver channel 24 and the IO channel 26 in the pin electronics 22 and a plurality of n (for example, four) DUTs 200. In this embodiment, one driver channel 24 in the pinpoint mouth 22 is associated with four DUTs 200 (200-1, 200-2, 200-3, 200-4). That is, the common signal power output from the driver DR in the driver channel 24 is input to the same driver pin of each of the DUT 200-1 to 200-4, and four 0171200-1 to 200-4 are input. A functional test is performed at the same time.

Specifically, the output terminal of the driver DR in the driver channel 24 is the coaxial cable 32 (32—1) in the mother board 30 and the wiring Cl, C2, C3, C4, C5 in the socket board 40. It is connected to the terminal resistor 28 in the driver channel 24 via the coaxial cable 32 (32-2) in the mother board 30. The output impedance of driver DR in driver channel 24 is set to 50 Ω. Also, the coaxial cables 32-1 and 32 2 in the motherboard 30 and the wiring in the socket board 40 Cl, C2, C3, C4, C5, and the impedance of the terminal resistor 28 in the driver channel 24 are also 50 Ω. Is set to Therefore, the signal that is also output as the driver DR force in the driver channel 24 is transmitted to the terminating resistor 28 without causing reflection. The termination resistor 28 may be provided on the socket board 40 or the mother board 30.

[0027] In the socket board 40, the driver pins of the DUT 200-1 are connected to the connection points of the wirings Cl and C2. Similarly, the driver pin of DUT200-2 is connected to the connection point of wirings C2 and C3. The driver pin of DUT200-3 is connected to the connection point of wiring C3 and C4. The driver pins of DUT200-4 are connected to the connection points of wirings C4 and C5. As described above, in this embodiment, the wirings Cl, C2, C3, C4, and C5 in the socket board 40 are connected in cascade (series connection), and a plurality of DUTs 200-1 to 200-4 are connected to the connection points of the respective wirings. It is connected

[0028] It should be noted that the connection between the IO pins included in each of the DUTs 200-1 to 200-4 and the respective IO channels 26 in the pin electronics 22 is performed in the same manner as in the prior art. That is, DUT200- Each IO pin 1 and each IO channel 26 are connected in a one-to-one relationship, and the path Z fail judgment is performed separately for the signal output from each IO pin.

Here, as shown by delay times DL1 to DL4 in FIG. 2, the waveforms applied to the driver pins of each DUT are applied at different timings. On the other hand, the delay times DL21 to DL24 of the four IO channels 26a to 26d are the same. In this case, for each DUT, the delay correction that gives the offset delay DLx to the variable delay element VD of the driver DR provided on the IO channel 26 side and the variable delay element VD of the stove signal STB is necessary. That is, in the case of the IO channel 26b, an offset delay amount DLx = DL2-DL1 is assigned. In the case of IO channel 26c, the offset delay amount DLx = DL3—DL1 is assigned. For IO channel 26d, the offset delay DLx = DL4—DLl is assigned. It is desirable to wire a plurality of adjacent DUTs so that the offset delay DLx is minimized. Further, since there are a plurality of driver channels 24, it is necessary to design a wiring pattern in the socket board 40 so that the delay times DL1 to DL4 corresponding to the driver channels 24 are the same. It is also desirable to adjust the skew by performing timing calibration on multiple IO channels 26 and multiple driver channels 24 to minimize skew between channels.

[0030] In the semiconductor test apparatus of this embodiment, the driver DR in the driver channel 24 is connected to the coaxial cable 32-1, the wiring Cl, C2, C3, C4, C5, and the coaxial cable 32-2 as one signal line. Are connected to each other, and four DUT200-1 to 200-4 are connected to different locations along the signal line. By matching the impedance of the coaxial cable 32-1 and wiring C1, etc., and connecting a termination resistor 28 to the tip of this signal line, it is possible to eliminate signal reflection at the middle and at the tip of this signal line. Therefore, it is possible to prevent a decrease in measurement accuracy due to signal waveform disturbance due to reflection. In addition, it is not necessary to increase the impedance of the wiring C1 etc. in the socket board 40 in order to increase the number of DUTs 200 as before, so the number of DUTs 200 that can be measured simultaneously can be easily increased to 2 or more. be able to. As a result, in the case of driver channel 24 having hundreds to thousands of channels, the number of channels can be greatly reduced, so that a cheaper semiconductor test apparatus can be realized. Can appear.

[0031] As described above, since it becomes possible to connect a plurality of DUTs 200 to the signal line without increasing the impedance of the signal line, there is no restriction due to the impedance of the signal line, and the DUT 200 that can be measured simultaneously is eliminated. You can increase the number. In addition, it is possible to input a common applied signal to a plurality of DUTs 200 with an increased number and simultaneously perform a function test.

[0032] It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the gist of the present invention. For example, in the embodiment described above, the configuration in which the signal output from the driver DR is input to the four DUTs 200-1 to 200-4 when performing the function test has been described. The DC test for supplying current can be used with almost the same configuration with only minor changes.

[0033] FIG. 3 is a diagram showing a modified example of the driver channel that can handle both the function test and the DC test. The driver channel 24A shown in FIG. 3 has a configuration in which switches 50, 52, 56 and a DC power supply 54 are added to the driver channel 24 shown in FIGS. The switch 50 is arranged between the output terminal of the driver DR and one end of the coaxial cable 32-1 in the mother board 30, and the connection between them is interrupted. The switch 52 is arranged between the terminating resistor 28 and one end of the coaxial cable 32-2 in the mother board 30, and the connection between them is interrupted. The switch 56 is arranged between the DC power source 54 and one end of the coaxial cable 32-1 in the mother board 30, and the connection between them is interrupted. The DC power source 54 generates a constant voltage and a constant current necessary for the DC test. Switches 50 and 56 correspond to the first switch, and switch 52 corresponds to the second switch.

When a functional test is performed using the driver channel 24A described above, the switches 50 and 52 are turned on and the switch 56 is turned off. By performing such switch control, the same connection state as that of the driver channel 24 shown in FIG. 2 is realized, and then a functional test is performed. The switch control is performed by the tester control unit 12.

[0035] When a DC test is performed, the switches 50 and 52 are turned off and the switch 56 is turned on. By performing such switch control, only the DC power supply 54 is connected to one end of the signal line formed by the coaxial cable 32-1, wiring C1, etc., and the other end of this signal line is connected. A connection state with open ends is realized, after which a DC test is performed. In this way, it is possible to selectively perform both functional tests and DC tests on multiple DUTs 200 using the same signal line. The terminal resistor 28 and switch 52 may be provided on the socket board 40 or the mother board 30.

[0036] In the above-described embodiment, a conventional branch may be combined with the present invention. FIG. 4 is a diagram showing a configuration of a modified example having a branch. The driver channel 24B shown in FIG. 4 has a configuration in which a termination resistor 28B is added to the driver channel 24 shown in FIG. The mother board 30B has a configuration in which one coaxial cable 32 (32-3) for connecting the driver channel 24B and the socket board 40B is added. The socket board 40B has two signal lines composed of wirings C1 to C5 in the socket board 40 shown in FIG. 2, and each end of each of these two signal lines has a mother line. It has a branch structure commonly connected to the coaxial cable 32-1 in the board 30B. To prevent signal reflection at the connection point (branch point) between the coaxial cable 32-1 and the two signal lines, the two signals when the impedance of the coaxial cable 32-1 is 50 Ω. The impedance of each line is set to 100 Ω. Therefore, the impedance of the two termination resistors 28 and 28B in the driver channel 24B is also set to 100 Ω. Thus, by combining the methods of branching the wiring in the socket board 40B, the number of DUTs 200 that can be measured simultaneously without causing signal reflection can be increased.

FIG. 5 is a diagram showing a connection configuration of a modified example that does not use a termination resistor, and shows a connection configuration in which the termination resistor 28 is deleted from the configuration shown in FIG. Even in this case, although the output terminal force of the driver channel 24 is 50 Ω, the impedance of the transmission line to the far end is 50 Ω, but the capacitance component is added at the connection points of the wirings C1 to C4 to each DUT. This causes a drop in impedance. When a DUT that does not terminate with the termination resistor 28 and allows the waveform quality of the test waveform to be acceptable, a connection configuration in which the termination resistor 28 is removed as shown in FIG. 5 may be employed.

[0038] In the above-described embodiment, the socket board 40 is connected to the pin electronics 22 via the mother board 30, and the names of these boards are the semiconductor test equipment manufacturers. It depends on etc. For example, the mother board 30 connected to the pin electronics 22 may be referred to as a performance board, or the combination of the mother board 30 and the socket board 40 may be realized by a combination of three or more boards. As shown in FIG. 2, the present invention can be applied to any configuration in which a plurality of DUTs 200 are connected in the middle of one signal line.

Industrial applicability

According to the present invention, since it becomes possible to connect a plurality of devices under test to the signal line without increasing the impedance of the signal line, there is no restriction due to the impedance of the signal line, and the device under test that can be measured simultaneously You can increase the number.

Claims

The scope of the claims

[1] A driver for inputting an applied signal to be used for testing to a pin of a device under test;

A signal line having one end connected to the output terminal of the driver and having a plurality of connection points provided in the middle;

A terminating resistor connected to the other end of the signal line;

A semiconductor test apparatus for connecting each of the plurality of devices under test to each of the plurality of connection points.

[2] In claim 1,

A test signal waveform generating means for generating a signal waveform required for a function test of the device under test;

A semiconductor test apparatus that receives the signal waveform, generates an applied signal by the driver, and inputs the generated applied signal to each of the plurality of devices under test connected to the signal line.

[3] In claim 1,

A semiconductor test apparatus that matches the output impedance of the driver, the impedance of the termination resistor, and the impedance of the signal line.

[4] In claim 3,

A pin-elect port on which a driver channel having the driver and the termination resistor is mounted;

A mother board connected to the pin electronics and wired by a coaxial cable forming part of the signal line connected to each of the driver and the termination resistor;

A socket board connected to the mother board, mounted with a plurality of the devices under test, and wired to form part of the signal line;

A semiconductor testing apparatus comprising:

[5] In any one of claims 2 to 4,

A DC power source that generates at least one of a voltage and a current necessary for a DC test of the device under test; A first switch for connecting the DC power source to the signal line;

A semiconductor test apparatus further comprising: a second switch that is inserted between the driver and the signal line to open and close the line.

[6] A driver for multiple channels that inputs an applied signal to be used for testing to the pins of the device under test;

A signal line having one end connected to the output terminal of the driver and having a connection path sequentially connected in series to corresponding pins of a plurality of devices under test;

A wiring length of the signal line that sequentially connects the plurality of devices under test in series with each other. The semiconductor test apparatus is set to have the same propagation delay amount in each of the plurality of channels.

[7] In claim 6,

A semiconductor test apparatus further comprising a termination resistor connected to the other end of the signal line connected to the driver.

[8] A socket board for mounting a plurality of devices under test provided in the semiconductor test apparatus according to claim 1.

A socket board comprising the signal line for sequentially connecting corresponding pins of the plurality of devices under test in series.

[9] In claim 6,

Corresponding to the amount of propagation delay associated with the wiring length of the signal line that is sequentially connected in series between the plurality of devices under test, it is based on the timing delay that occurs in the applied signal applied to the pin of each device under test. A semiconductor test apparatus that adjusts delay timing for the IO channels connected to the IO pins of the plurality of devices under test.

[10] In claim 9,

The adjustment of the delay timing for the IO channel is performed by setting a delay amount that cancels a difference in propagation delay amount due to a difference in the wiring length of the signal line for the second driver provided in the IO channel, and A semiconductor test apparatus for setting a delay amount that cancels a difference in propagation delay amount due to a difference in wiring length of the signal line with respect to a comparator provided in an IO channel.