JP4214361B2 - IC test apparatus and output signal timing adjustment method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is an IC test apparatus for testing ICs (particularly, grouping according to the hardware configuration of the adjustment target pins in output signal output timing adjustment, and determining the timing of the determination strobe signal given to the logical comparator used for adjustment for each group) IC test apparatus that can be changed to
[0002]
[Prior art]
FIG. 7 is a block diagram showing a configuration of a conventional IC test apparatus, and FIG. 8 is a flowchart showing a timing adjustment method in this IC test apparatus. First, an output signal pin to be adjusted is extracted from a file set by the user by the computer CPU2. (Step S21)
[0003]
The IC test apparatus A2 inputs the driver signal SGst output from the driver waveform generation circuit TGFCst from the drive circuit Dst to the connection destination switching apparatus M2 as the reference driver signal Wsd. This reference driver signal Wsd is terminated to the termination voltage VTM via the resistor Rstd.
[0004]
The input reference driver signal Wsd is selected and output from the connection switching device M2 as the selection signal Wsc, and is input to the logic comparator Jst via the voltage comparison circuit Vst. The selection signal Wsc is terminated at the termination voltage VTM via the resistor Rstc at the input of the voltage comparison circuit Vst.
[0005]
The timing adjustment of the determination strobe signal STB to the logical comparator Jst is performed by changing the edge timing of the determination strobe signal STB by changing the value of the variable delay amount data Kst2 given from the computer CPU2 to the variable delay circuit DLst.,Variable delay amount data when the input signal is judged by the logical comparator Jst at the edge timing of this judgment strobe signal STB, and the resulting Pass / Fail judgment result Pst changes from Fail (H) to Pass (L) Execute by obtaining the value of Kst2. (Step S22)
[0006]
The connection destination switching device M2 selects the driver output signal W1 of the adjustment target pin as an input signal and outputs it as the selection signal Wsc. The signal is input to the logical comparator Jst via the voltage comparison circuit Vst. (Step S23)
[0007]
The adjustment is a variable that is given from the computer CPU2 to the variable delay circuit DL1 of the adjustment target pin in a state where the timing data is given to the timing generation circuit TGst so that the timing of the determination strobe signal STB becomes the timing value that the adjustment target pin wants to match. While changing the value of the delay amount data K1, the value of the variable delay amount data K1 when the signal of the Pass / Fail determination result Pst resulting from the edge search by the logical comparator Jst changes is obtained. (Step S8).
[0008]
After the adjustment value is obtained, the input signal is switched to the next adjustment target pin by the connection destination switching device M2. (Step S9) Thereafter, the processing from step S5 to step S9 is repeated in the same manner for all the adjustment target pins.
[0009]
[Problems to be solved by the invention]
Conventionally, in the IC test apparatus A2, the hardware configuration of the adjustment target pins is connected like driver waveform generation circuits TGFC1 to TGFCm-1, variable delay circuits DL1 to DLm-1, and drive circuits D1 to Dm-1. In the case of driver pins DRV1 to DRVm-1 whose outputs are open ends, driver waveform generation circuits TGFCm to TGFCx, variable delay circuits DLm, to DLx, drive circuits Dm to Dx, resistors R1 to Rx,TerminationThe voltage VTM and the voltage comparison circuits V1 to Vx are connected and the termination voltage VTM is mixed with the case of the I / O pins I / O1 to I / Ox terminated through resistors.
[0010]
In this way, in the IC test equipment A2 where the hardware configuration of the pin to be adjusted is mixed, at the time of adjustment by the adjustment pin CMP, it is terminated to the termination voltage VTM via the resistor Rstc on the path, and on the connection path A filter circuit is formed by the stray capacitance and the resistor Rstc.
[0011]
For this reason, when the hardware configuration of the adjustment target pin is the open-ended driver pins DRV1 to DRVm-1, the output timing of the output signal changes between this adjustment and the adjusted open-ended state. In the conventional IC test apparatus A2 having only one type of variable delay amount data Kst2 which is the timing adjustment data of the determination strobe signal STB input to the logical comparator Jst, even if the output timing of the adjustment target pin is adjusted There was a problem that a deviation of about 100 ps occurred between pins with different hardware configurations.
[0012]
Problems of the present invention
(Objective) was made in order to solve the above problem, and is to provide an IC test apparatus capable of performing an accurate output timing adjustment regardless of the hardware configuration of the adjustment target pin. .
[0013]
[Means for Solving the Problems]
In order to solve the above problem,Adjustment types with different hardware configurationsAn IC test device in which a plurality of pins are mixed,HardwareGroup by configuration and record one pin for each group as the representative pin of the groupRepresentative pin recordMeans and for each groupAboveRepresentative pinOutput signalMeasure and record the delay time with respect to the reference timingMeasurement and recording of representative pin delay timeMeans and saidEach measured and recordedDelay timeBased on the representative pin output timing adjustment means for adjusting the timing of each output signal of the representative pin, and for each of the groups, based on the adjusted output signal of the representative pin, the corresponding groupFor each pin to be adjustedOutput signalAdjust timingAdjustment target pin output timing adjustmentIC testing device comprising meansI will provide a. (Claim 1)
[0014]
Also, the aboveHardware configurationThe grouping for each configuration is a configuration in which at least an output is a driver pin having an open end, and an output is an I / O pin terminated with a termination at a termination voltage. (Claim 2)
[0015]
Also,driverGenerate signalDoDriver waveform generation circuit and the driver waveform generation circuitOccurrenceThe input driver signal as inputDriverA variable delay circuit capable of adjusting a delay time for outputting a signal, and a delay time adjusted by the variable delay circuitdriverSignalAs output signaloutputDoA drive circuit, a CPU that executes processing of variable delay amount data for changing the delay time of the variable delay circuit, and the drive circuit from the drive circuit via a contact washerAboveOutputs a voltage comparison circuit that receives an output signal, a logical comparator that receives a signal from the voltage comparison circuit and determines Pass / Fail by edge search of a determination strobe signal, and a reference driver signal that is a timing reference signal An IC test apparatus including a timing generation circuit. (Claim 3)
[0016]
Also,Adjustment types with different hardware configurationsA method for adjusting the timing of an output signal in an IC test apparatus having a plurality of pins,AbovePin to be adjustedThe aboveGroup by hardware configurationDivide,eachSelect and record one representative pin for each group numberRepresentative pin selection / recordingMeasure the reference timing using the delay time measurement function of the oscilloscope with the step and reference driver signal as input.Reference timing measurementSteps,With the delay time measurement function of the oscilloscopeSaidrepresentativeOf pinFor each output signalMeasure and record the delay time with respect to the reference timingDelay time measurement and recordingSteps,Based on the measured and recorded delay times, the representative pin output timing adjustment step for adjusting the timing of each output signal of the representative pin, and for each group number, based on the adjusted output signal of the representative pin , The corresponding group numberOf the pin to be adjustedThe timing of the output signaladjustAdjustment target pin output timing adjustment step andso,Of the pin to be adjustedAdjust the timing of the output signal. (Claim 4)
[0017]
Also,The adjustment target pin output timing adjustment step includes at least the adjusted representative for each group number.pinofOutput signalAnd a determination strobe signal, the delay time of the determination strobe signal is changed, and the timing adjustment of the determination strobe signal is performed based on the determination result in the logical comparator. In the state where the determination strobe signal adjustment step and the output signal of the adjustment target pin of the group number corresponding to the adjusted determination strobe signal for each group number are provided to the logical comparator, The delay time of the output signal is changed and the logic comparator And an adjustment target pin output delay time amount calculating step for calculating a delay time amount of the output signal of the adjustment target pin based on the determination result.. (Claim 5)Adjustment targetOf pinhardwareThe grouping for each configuration is configured such that at least the driver pins whose outputs are open ends and the outputs are grouped into termination voltages and I / O pins terminated via resistors. (Claim 6)
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram according to an embodiment of the present invention, and FIG. 2 is a flowchart illustrating a timing adjustment method according to an embodiment of the present invention. FIG. 3 is an example of classification information data used in timing adjustment according to an embodiment of the present invention. 4, 5, and 6 are timing charts showing the operation of the IC test apparatus A1 in the present embodiment.
[0019]
In FIG. 1, the pin that outputs the reference driver signal Wsd at the reference timing Tso of the IC test apparatus A1 outputs the driver signal SGst from the driver waveform generation circuit TGFCst, and inputs the driver signal SGst as a reference from the drive circuit Dst. The driver signal Wsd is output. Further, this pin is terminated from the contact washer Bst to the termination voltage VTM via the resistor Rstd.
[0020]
The driver pins DV1 to DVm-1 receive the driver signals SG1 to SGm-1 output from the driver waveform generation circuits TGFC1 to TGFCm-1, and receive input signals based on the variable delay amount data K1 to Km-1 from the computer CPU1. Variable delay circuits DL1 to DLm-1 that can change the delay time of the output timing, and drive circuits D1 to Dm-1 that use the output signals from the variable delay circuits DL1 to DLm-1 as input signals. It is connected to seats B1 to Bm-1.
[0021]
Also, the I / O pins I / O1 to I / Ox receive the driver signals SGm to SGx output from the driver waveform generation circuits TGFCm to TGFCx as input, and input signals by the variable delay amount data Km to Kx from the computer CPU1. Variable delay circuits DLm to DLx that can change the delay time of the output timing, and drive circuits Dm to Dx that use the output signals from the variable delay circuits DLm to DLx as input signals, and are connected to contact washer Bm to Bx Has been. Further, the contact washer Bm to Bx is terminated to the termination voltage VTM via the resistors Rm to Rx, and input to the voltage comparison circuits V1 to Vx.
[0022]
The adjustment pin CMP outputs the determination strobe pulse SP output from the timing generation circuit TGst as a determination strobe signal STB from the variable delay circuit DLst with a delay time corresponding to the variable delay amount data Kst1 given by the computer CPU1. Input to comparator Jst. The selection signal Wsc is input to the logical comparator Jst via the voltage comparison circuit Vst, and the edge is determined by the edge timing of the determination strobe signal STB, and the Pass / Fail determination result Pst is output.
[0023]
The driver output signals W1 to Wx output from the driver pins DR1 to DRm-1 and the I / O pins I / O1 to I / Ox are the contact pins B1 to Bx at the input terminals of the connection destination switching device M1. Switching can be selected by touching sequentially. The selected driver output signals W1 to Wx are output as the selection signal Wsc and connected to the adjustment pin CMP.
[0024]
The driver output signals W1 to Wx selected in the same manner as described above can be switched and input to the oscilloscope as the selection signal Wso. When the selection signal Wso for the oscilloscope is used as the selection signal, the contact with the output signals W1 to Wx is performed with the input terminal of the connection destination switching device M1 in a high impedance state.
[0025]
The computer CPU1 changes the delay time of the signal passing through the variable delay circuits DL1 to DLx and DLst based on the data grouped by the hardware configuration of the adjustment target pins and selecting the representative pins of the group Variable delay amount data K1 to Kx, Kst1 and variable delay amount data K1 to Kst1 output to the variable delay circuits DL1 to DLx and DLst according to the Pass / Fai determination result Pst output from the logical comparator Jst A process of storing and storing the values of Kx and Kst1 as the adjustment result of each adjustment target pin is executed.
[0026]
Next, the operation of the present invention will be described using the flowchart of FIG. 2 showing the procedure of the timing adjustment method according to the present invention and the example of the classification information data grouped by the hardware configuration of the adjustment target pins of FIG. explain. First, the pin to be adjusted is grasped and the group representative pin is selected from the classification information data stored in the computer CPU1. (Step S1)
[0027]
The selection of the group representative pin is performed by the computer CPU1 using the pin number when the new group number value is detected while searching for the group number of the classification information data as the group representative pin. In the example of FIG. 3, first, the group number 1 is detected and the driver pin DRV1 is selected as the representative pin. Next, 2 is detected as a new group number, and the I / O pin I / O1 is selectively recorded by the computer CPU1. By increasing the number of types of group numbers, not only the classification of driver pins and I / O pins, but also the classification based on the types of output voltage amplitude of driver output signals can be easily performed.
[0028]
Next, the reference driver signal Wsd is measured by an oscilloscope, and the delay time is measured by the delay time measurement function of the oscilloscope. (Step S2) The delay time is measured by the delay time measurement function of the oscilloscope for the representative pin extracted by the process of step S1, and the value of the variable delay amount data that is the timing adjustment value for each representative pin is measured. Calculated by computer CPU1. (Step S3)
[0029]
The operation of step S3 will be described in detail using FIG. 4 as an example. FIG. 4 is a timing chart showing the operation of the IC test apparatus A1 in the present embodiment. Reference numeral 100 denotes a waveform measured with an oscilloscope by bringing the input terminal of the connection switching device M1 into contact with the contact washer Bst and using the reference driver signal Wsd as the selection signal Wso. The delay time Ts0 measured by the oscilloscope at this time becomes the reference timing of the IC test apparatus A1.
[0030]
When the driver pins DRV1 and I / O pins I / O1 are selected as group representative pins, the driver output signals W1 and Wm of the driver pins DRV1 and I / O pins I / O1 at the start of adjustment This is a waveform observed with an oscilloscope as a selection signal Wso by bringing the contact terminals B1 and Bm into contact with the input terminal of the connection switching device M1 in order.
[0031]
At this time, the differences Tβ and Tγ between the delay times Tio0 and Tdr0 measured by the oscilloscope and the adjustment timing Texp derived from the reference timing Ts0 and the user setting timing Tα are the adjustment widths of the respective pins. Based on these values Tβ and Tγ, the values of the variable delay amount data K1 and Km are calculated by the computer CPU1 and given to the variable delay circuits DL1 and DLm. For example, when the variable delay circuits DL1 and DLm are delayed by 1 ps per unit, the value of the variable delay amount data K1 is Tβ and the value of the variable delay amount data Km is Tγ.
[0032]
Reference numerals 300 and 301 denote driver output signals W1 and I / O pins I / O1 in a state where Tβ and Tγ are given to the variable delay circuits DL1 and DLm as values of the variable delay amount data K1 and Km, and Wm is a waveform observed with an oscilloscope as a selection signal Wso when the input terminal of the connection switching device M1 is brought into contact with the contact washer B1 and Bm.
[0033]
Next, for each representative pin adjusted in step S3, the timing adjustment of the determination strobe signal STB used in the adjustment pin CMP is performed, and the value of the variable delay amount data Kst1 as the adjustment result for each representative pin, Record and save in computer CPU1. (Step S4)
[0034]
The timing adjustment of the determination strobe signal STB in step S4 will be described in detail with reference to FIG. 400 is selected by the connection destination switching device M1 for the driver output signal W1 of the driver pin DRV1 in a state where Tβ is supplied to the variable delay circuit DL1 as the value of the variable delay amount data K1 adjusted by the oscilloscope. This is the waveform at the input point of the logical comparator Jst when it is input to the adjustment pin CMP as Wsc.
[0035]
Reference numerals 500, 501 and 502 represent changes in edge timing when the value of the variable delay amount data Kst1 supplied from the computer CPU1 is 0, 5, 10 when the determination strobe signal STB input to the logical comparator Jst is 0,5,10. ing. The output result obtained by determining the signal 400 input to the logical comparator Jst at the timing of the rising edge of this signal (500, 501 and 502) is the Pass / Fail determination result Pst of 600, 601 and 602. The Pass / Fail judgment result Pst is Fail (H) when the voltage level of the input signal 400 is lower than the judgment voltage value Vsh at the timing of the rising edge of the judgment strobe signal STB, and Pass (L) when it is high. Output.
[0036]
When the Pass / Fail judgment result Pst changes from Fail (H) to Pass (L), the value of the variable delay amount data Kst1 is the timing adjustment of the judgment strobe signal STB by the representative pins of the driver pins DRV1 to DRVm-1. This is the result, and the value in this case is 10. The computer CPU1 stores 10 as the value of the variable delay amount data Kst1 as a value used when adjusting the driver pins DRV1 to DRVm-1.
[0037]
401 selects the driver output signal Wm of the I / O pin I / O1 in a state where Tγ is given to the variable delay circuit DLm as the value of the variable delay amount data Km adjusted by the oscilloscope, and is selected by the connection destination switching device M1. This is a waveform at the input point of the logical comparator Jst when it is input to the adjustment pin CMP as the selection signal Wsc.
[0038]
Reference numeral 503 denotes a signal when the determination strobe signal STB input to the logical comparator Jst has the value of the variable delay amount data Kst1 given from the computer CPU1 as 12. The output result of determining the signal 401 input to the logical comparator Jst at the timing of the rising edge of the determination strobe signal (500, 501, 502 and 503) is the Pass / Fail determination result of 700, 701, 702 and 703. Pst.
[0039]
When the Pass / Fail judgment result Pst changes from Fail (H) to Pass (L), the value of the variable delay data Kst1 is the judgment strobe signal from the representative pins of the I / O pins I / O1 to I / Ox This is the STB timing adjustment result, and the value in this case is 12. The computer CPU1 saves and stores 12 which is the value of the variable delay amount data Kst1 as a value used when adjusting the I / O pins I / O1 to I / Ox.
[0040]
The computer CPU1 determines whether or not there is a pin for performing timing adjustment. (Step S5) If there is no adjustment target pin (NO) in step S5, the process ends. If it is determined in step S5 that there is a pin for which timing adjustment is to be performed (YES), contact metal pins B1 to Bx of the adjustment target pin are brought into contact with the input terminal of the connection destination switching device (M1) and selected. Output as signal Wsc. (Step S6)
[0041]
The group number of the pin to be adjusted is searched by the computer CPU1 from the classification information data used in step S1, and the timing adjustment data of the determination strobe signal STB by the representative pin of the same group number stored and recorded in the computer CPU1 in step S4 The value of the variable delay amount data Kst1 is transferred from the computer CPU1 to the variable delay circuit DLst. (Step S7)
[0042]
In the example of FIG. 6, when adjusting the pin of the same group number 1 as the driver pin DRV1, 10 is transferred to the value of the variable delay amount data Kst1, and the same group number 2 as the I / O pin I / O1. 12 is transferred to the value of the variable delay amount data Kst1.
[0043]
While changing the value of the variable delay amount data K1 to Kx given from the computer CPU1 to the variable delay circuits DL1 to DLx of the pin to be adjusted, the logical comparator Jst performs edge search of the judgment strobe signal STB, and the Pass / Fail judgment result The values of the variable delay amount data K1 to Kx when Pst changes from Pass (L) to Fail (H) are searched to obtain the adjustment value. (Step S8)
[0044]
Using FIG. 6 as an example, the operation in step S8 will be described in detail. 800 indicates the waveform of the input point of the logical comparator Jst when the driver output signal W2 of the driver pin DRV2 at the start of adjustment is selected by the connection destination switching device M1 and is input to the adjustment pin CMP as the selection signal Wsc. It is.
[0045]
Reference numeral 801 denotes a waveform at the input point of the logical comparator Jst when the value of the variable delay amount data K2 applied from the computer CPU1 to the variable delay circuit DL2 is changed. The output result of determining the signal 800 input to the logical comparator Jst at the timing of the rising edge of the determination strobe signal 502 is the 900 Pass / Fail determination result Pst, and the output of determining the input signal 801 The result is a Pass / Fail determination result Pst of 901.
[0046]
The value of the variable delay amount data K2 when the Pass / Fail determination result Pst changes from Pass (L) to Fail (H) is the timing adjustment result of the driver pin DRV2. In this example, when the variable delay amount data K2 is 20, the Pass / Fail determination result Pst changes, and 20 is stored and recorded in the computer CPU1 as the adjustment result.
[0047]
802 is the output of the logical comparator Jst when the driver output signal Wn of the I / O pin I / O2 at the start of adjustment is selected by the connection destination switching device M1 and is input to the adjustment pin CMP as the selection signal Wsc. It is the waveform of the input point. Reference numeral 803 denotes a waveform at the input point of the logical comparator Jst when the value of the variable delay amount data Kn given from the computer CPU1 to the variable delay circuit DLn is changed.
[0048]
The output result of determining the signal 802 input to the logical comparator Jst at the timing of the rising edge of the determination strobe signal 503 is the Pass / Fail determination result Pst of 902, and the output determining the input signal 803 The result is the Pass / Fail determination result Pst of 903.
[0049]
The value of the variable delay amount data Kn when the Pass / Fail determination result Pst changes from Pass (L) to Fail (H) is the timing adjustment result of the I / O pin I / O2. In this example, the variable delay amount data Kn changes to 25, the Pass / Fail determination result Pst changes, and 25 is stored and recorded in the computer CPU1 as the adjustment result. The process is changed to the next adjustment target pin, and the processing from step S5 to step S8 is repeated for other adjustment target pins. (Step S9)
[0050]
【The invention's effect】
In the invention according to claim 1,Adjustment types with different hardware configurationsAn IC test device in which a plurality of pins are mixed,HardwareGroup by configuration and record one pin for each group as the representative pin of the groupRepresentative pin recordMeans and for each groupAboveRepresentative pinOutput signalMeasure and record the delay time with respect to the reference timingMeasurement and recording of representative pin delay timeMeans and saidEach measured and recordedDelay timeBased on the representative pin output timing adjustment means for adjusting the timing of each output signal of the representative pin, and for each of the groups, based on the adjusted output signal of the representative pin, the corresponding groupFor each pin to be adjustedOutput signalAdjust timingAdjustment target pin output timing adjustmentMeans for providing an IC test apparatus.Of pinWhen performing output signal timing adjustment,hardwareEven when pins having different configurations and output voltage amplitudes are mixed, there is an effect that timing adjustment can be performed with high accuracy.
[0051]
Moreover, in invention of Claim 2, the saidHardware of the pin to be adjustedThe grouping for each configuration consists of at least driver pins whose outputs are open ends and I / O pins whose outputs are terminated to the termination voltage VTM via resistors. In this case, it is possible to solve the problem that the output timing of the output signal changes between this adjustment and the open end state after the adjustment.
[0052]
In the invention according to claim 3,driverGenerate signalDoDriver waveform generation circuit and the driver waveform generation circuitOccurrenceThe input driver signal as inputDriverA variable delay circuit capable of adjusting a delay time for outputting a signal, and a delay time adjusted by the variable delay circuitdriverSignalAs output signaloutputDoA drive circuit, a CPU that executes processing of variable delay amount data for changing the delay time of the variable delay circuit, and the drive circuit from the drive circuit via a contact washerAboveOutputs a voltage comparison circuit that receives an output signal, a logical comparator that receives a signal from the voltage comparison circuit and determines Pass / Fail by edge search of a determination strobe signal, and a reference driver signal that is a timing reference signal The present invention can be easily applied to a conventional IC test apparatus that includes an IC test apparatus including a timing generation circuit.
[0053]
In the invention according to claim 4,Adjustment types with different hardware configurationsA method for adjusting the timing of an output signal in an IC test apparatus having a plurality of pins,AbovePin to be adjustedThe aboveGroup by hardware configurationDivide,eachSelect and record one representative pin for each group numberRepresentative pin selection / recordingMeasure the reference timing using the delay time measurement function of the oscilloscope with the step and reference driver signal as input.Reference timing measurementSteps,With the delay time measurement function of the oscilloscopeSaidrepresentativeOf pinFor each output signalMeasure and record the delay time with respect to the reference timingDelay time measurement and recordingSteps,Based on the measured and recorded delay times, the representative pin output timing adjustment step for adjusting the timing of each output signal of the representative pin, and for each group number, based on the adjusted output signal of the representative pin , The corresponding group numberOf the pin to be adjustedThe timing of the output signaladjustAdjustment target pin output timing adjustment step andso,Of the pin to be adjustedThe timing of the output signalhardwareEven when pins with different configurations and output voltage amplitudes are mixed, there is an effect that timing adjustment can be performed with high accuracy.
[0054]
In the invention according to claim 5,The adjustment target pin output timing adjustment step includes at least the adjusted representative for each group number.pinofOutput signalAnd the delay time of the determination strobe signal are changed while the determination strobe signal is applied to the logical comparator. And a determination strobe signal adjustment step for each group number for performing timing adjustment of the determination strobe signal based on a determination result in the logical comparator, and corresponding to the adjusted determination strobe signal for each group number In a state where the output signal of the adjustment target pin of the group number is supplied to the logical comparator, the delay time of the output signal of the adjustment target pin is changed, and based on the determination result in the logical comparator, the adjustment target And an adjustment target pin output delay time amount calculating step for calculating a delay time amount of the output signal of the pin.SohardwareEven when pins with different configurations and output voltage amplitudes are mixed, timing adjustment can be performed with high accuracy. In the invention according to claim 6, theHardware of the pin to be adjustedThe grouping for each configuration is divided into at least driver pins whose outputs are open ends, and outputs are terminated at termination voltage VTM and I / O pins terminated via resistors. In this case, it is possible to solve the problem that the output timing of the output signal changes during the adjustment and in the open end state after the adjustment.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an IC test apparatus according to an embodiment of the present invention.
FIG. 2 is a flowchart of a timing adjustment method in the IC test apparatus according to the embodiment of the present invention.
FIG. 3 is an example of classification information data used in the timing adjustment method in the IC test apparatus according to the embodiment of the present invention.
FIG. 4 is a measurement waveform at timing adjustment in an oscilloscope according to an embodiment of the present invention.
FIG. 5 is an example of a measurement waveform input to the logical comparator during timing adjustment of the determination strobe signal input to the logical comparator in one embodiment of the present invention.
FIG. 6 is an example of a measurement waveform input to a logical comparator at the time of timing adjustment of an adjustment target pin in one embodiment of the present invention.
FIG. 7 is a diagram showing a configuration of a conventional IC test apparatus.
FIG. 8 is a flowchart of a timing adjustment method by a conventional IC test apparatus.
[Explanation of symbols]
A1, A2 IC test equipment
B1, B2, Bm, Bn, Bx, Bst Contact washer
CMP adjustment pin
CPU1, CPU2 computer
D1, D2, Dm, Dn, Dx, Dst drive circuit
DL1, DL2, DLm, DLn, DLx, DLst Variable delay circuit
DRV1, DRV2 driver pins
I / 01, I / 02, I / ox I / O pins
Jst logical comparator
K1, K2, Km, Kn, Kx, Kst1, Kst2 Variable delay data
M1, M2 connection destination switching device
Pst Pass / Fail judgment result
R1, R2, Rstc, Rstd resistance
SG!, SG2, SGm, SGn, SGx, SGst Driver signal
SP judgment strobe pulse
STB judgment strobe signal
TGst timing generator
TGFC1, TGFC2, TGFCm, TGFCn, TGFCx, TGFCst Driver waveform generation circuit
V1, V2, Vx, Vst Voltage comparison circuit
VTM termination voltage
W1, W2, Wm, Wn, Wx Driver output signal
Wsd reference driver signal
Wsc, Wso selection signal

Claims (6)

An IC test apparatus in which a plurality of adjustment target pins of different types of hardware configurations are mixed, the adjustment target pins being grouped for each hardware configuration, and one pin for each group being a representative pin of the group a representative pin recording means for recording as a representative pin delay time measuring and recording means for measuring and recording the time delay with respect to the reference timing of the output signal of the representative pin of each group, each delay time the measured and recorded Based on the representative pin output timing adjusting means for adjusting the timing of each output signal of the representative pin based on the adjusted output signal of the representative pin for each group, the adjustment target pin of the corresponding group And an adjustment target pin output timing adjustment means for adjusting the timing of each output signal . The grouping of the adjustment target pins for each hardware configuration includes at least driver pins whose outputs are open ends and I / O pins whose outputs are terminated via a resistor at a termination voltage. The IC test apparatus according to claim 1. A driver waveform generating circuit for generating a driver signal, the inputs the driver signal generated by driver waveform generating circuit, and an adjustable variable delay circuit the delay time which the input driver signal is outputted, said variable delay A driver circuit that outputs a driver signal whose delay time is adjusted by the circuit as an output signal, a CPU that executes processing of variable delay amount data for changing the delay time of the variable delay circuit, and a contact washer a voltage comparison circuit which receives the output signal from the drive circuit Te, a determination strobe signal of logic comparator determines Pass / Fail by edge search in response to a signal from the voltage comparator circuit, a timing reference signal IC test equipment according to claim 1 or 2, characterized in that it comprises a timing generating circuit, the outputs of the reference driver signal consisting. A timing adjustment method for an output signal in an IC test apparatus in which a plurality of adjustment target pins of different types of hardware configurations are mixed, wherein the adjustment target pins are grouped according to the hardware configuration, one for each group number wherein the representative pin selection and recording step of recording by selecting a representative pin, the reference driver signal as an input, a reference timing measuring step of measuring the reference timing by the delay time measurement function of the oscilloscope, the delay time measurement function of the oscilloscope The delay time measurement / recording step for measuring and recording the delay time of each output signal of the representative pin with respect to the reference timing, and adjusting the timing of each output signal of the representative pin based on the measured and recorded delay times Representative pin output timing adjustment step and the group number To, on the basis of the output signal of the adjusted representative pin, the corresponding group number the adjusted pin output signal of the adjusted pin output timing adjusting step of adjusting the timing of the output signal, characterized in that it comprises of Timing adjustment method. In the adjustment target pin output timing adjustment step, at least for each group number, the output signal of the adjusted representative pin and the determination strobe signal are supplied to a logical comparator, and the delay time of the determination strobe signal is set. And a step for adjusting a determination strobe signal for each group number for performing timing adjustment of the determination strobe signal based on a determination result in the logical comparator, and corresponding to the adjusted determination strobe signal for each group number. In a state where the output signal of the adjustment target pin of the group number is supplied to the logical comparator, the delay time of the output signal of the adjustment target pin is changed, and based on the determination result in the logical comparator, the adjustment target Patent in that it comprises an adjustment target pin output delay time amount calculating step of calculating a delay time amount of pins of the output signal, the Timing adjustment method for the output signal according to claim 4,. The grouping of the adjustment target pins for each hardware configuration is to group at least a driver pin whose output is an open end, and an output into a termination voltage and an I / O pin terminated through a resistor. 6. The output signal timing adjustment method according to claim 4, wherein the output signal timing is adjusted.

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