JPS6385377A - Apparatus for evaluating semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten the measuring time of the timing characteristic of a memory tested, by giving delay times different from each other to test input during a time when one test pattern is carried out to respectively perform tests. CONSTITUTION:A test pattern is generated from a test pattern generator 12 on the basis of the timing from a timing generator 11 and inputted to a memory 15 tested as test input through a delay circuit part 21, a test input wave form format control part 13 and a test input signal drive part 14. Test output enters a digital comparator 17 through a level comparator 16 and is compared with a test output expected value to perform the judge of pass or fail and fail output is inputted to a counter part 22. Then, during a time when one test pattern is carried out, delay times different from each other are given and, at the point of time when the practice of the test pattern is finished, the content of a fail counter is checked to judge a timing value and the timing distribution of a fail bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) The present invention relates to a semiconductor memory evaluation device, and more particularly to a device for measuring various timing characteristics of a semiconductor memory.

(Prior Art) Conventionally, an evaluation device for measuring timing characteristics (access time tACC% write pulse width, etc.), which is an AC item, among the electrical characteristics of a semiconductor memory, has been
It is configured as shown in the figure. That is, 11 is a timing generator, 12 is a detonator turf generator, 13 is a test input waveform f-mat control section, and 14 is a test input signal drive (supply) section, and these are continuously connected. The output signal of the drive section J4 is supplied to a memory under test (for example, a semiconductor memory such as a static random access memory (SRAM)) 15. As a result, an arbitrary test output signal is output from the test memory 15,
This output signal is level-compared by a level comparator 16 and then led to a digital comparator 17, where it compares the expected output value output from the test/4 turf generator 12 with the strobe signal from the timing generator 11. Comparison results (test results) by being digitally compared with
is obtained. Note that control signals necessary for the above operations are provided from the test processor 18.

The above evaluation device measures the timing characteristics of the memory under test using arbitrary test timing and test/4 turns, and determines whether it is a good product or a defective product.
There are problems as described below.

That is, the test timing cannot be manipulated during execution of one test pattern, and the test timing must be set in advance. I feel embarrassed.

When measuring each timing characteristic of a memory, we use techniques such as the pie search method to search for timing efficiently. If it fails (if it fails), change the test timing and execute the test pattern again.'' This operation is repeated many times (usually it takes 10 tests/turns to measure one timing characteristic).
It is necessary to perform the process several times). However, with such evaluation equipment, the test pattern length is long due to the increased capacity of the test memory and improved functionality, and the measurement time is extremely long due to the increased number of timing characteristics items to be measured. turn into.

(Problems to be Solved by the Invention) The present invention solves the problem that, as described above, the measurement time becomes long by repeating the test/four turns many times to measure one timing characteristic of the memory under test. The present invention was developed to solve the above problems, and provides a semiconductor memory evaluation device that can measure one timing characteristic by executing one test/four turns, and can significantly shorten the time required to measure the timing characteristics of a test memory. The purpose is to

[Structure of the Invention] (Means for Solving Problems) A semiconductor memory evaluation device of the present invention includes a delay means between a test pattern generator and a test input signal driver, and
During the execution of the test pattern, there are multiple cycles in which tests are performed by giving different delay times to the test input, and the memory under test is determined based on whether or not the test output in each cycle is a fail output. It is characterized in that timing, which is a measurement item, is measured.

(Effect) By executing one test/four turns, the memory under test is
can measure the timing of two Therefore, measurement time can be shortened compared to conventional evaluation devices that measure one timing by executing a test pattern several times. In this case, as the test pattern length becomes longer and the number of timing measurement items increases due to larger capacity, improved functionality, etc. of the memory under test, the effect of shortening the measurement time becomes more significant.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In the semiconductor memory evaluation device shown in FIG. 1, a timing generator 11, a test pattern generator 12, a delay/counter section 20, a test input waveform controller 13,
The test input signal driver 14 is continuously connected. 15
is the memory under test, its test output signal is input to the level comparator 16, and the output of the level comparator 16 and the delayed output (test/4 turn signal) of the delay/counter section 20 are input to the digital comparator 17. input. The delay/counter section 20 operates in synchronization with the test pattern from the test pattern generator 12, and is set to have an alternative delay time from among different delay times.Delay circuit section 2
1, and a counter unit 22 that counts the number of times a fail output occurs for each delay time when the output of the digital comparator 17 associated with the memory test corresponding to each delay time setting is a fail output. The reeds are constructed as shown in FIG. 2, for example. That is, ~Dn is n delay circuits having the same performance and function, S.

~S is a switch circuit, C1 to Cn are n fail address counters (fail counters) having the same performance and the same function, and 23 is the switch circuit S, which controls switches to ~ and selects the counters C1 to Cn. This is a delay/counter selection circuit that selects a uniform counting operation. The n delay circuits ~Dn are continuously connected between the test pattern input terminal 24 and the delay test pattern input terminal 25, and the switch circuits S and ~Sn are respectively connected to the delay circuits, ~Dn is inserted in series on the output side. In this case, the switch circuits S, ~5n-1 each output the input from the previous stage delay circuit as the input of the subsequent stage delay circuit according to the switch control signal to the first output state or delay test pattern output terminal 25. The switch circuit Sn is controlled to output a second output state, and the switch circuit Sn is controlled to turn off (first output state)/on (second output state) according to the switch control signal. . In addition, the switches S, ~Sn and the counter C1
.about.Cn are selectively controlled by the delay/counter selection circuit 23. This delay/counter selection circuit 23 receives a test pattern from a test pattern input terminal 24, and selects one set of switches S, ~Sn, and counters C1 to Cn, for example, as the first number for each cycle of the test pattern. is configured to do so. In addition, 26 is the digital comparator (FIG. 1 17
) fail input terminal to which the fail output from ) is input, 2
Reference numeral 1 denotes a clock selection circuit that selects a basic clock necessary for the operation of the delay/counter section 20.

Furthermore, a test processor 19 is provided which generates control signals for comprehensively controlling the entire apparatus shown in FIG. It has a function of detecting the timing value as well as the timing distribution status of fail pits as the timing characteristics of the memory under test 15 based on the contents of each output of the counters C1 to Cn after execution of nine turns of reset).

Next, the operation of the evaluation apparatus shown in FIG. 1 will be explained. Test based on timing from timing generator 11/4
A test pattern is generated from the turn generator 12, and this test/4 turn is generated by the delay circuit section 2 of the delay/counter section 20.
1, the test input waveform 7 enters the frame controller 13, where it is converted into a predetermined frame test input signal, and then passes through the test input signal driver 14 to the memory under test 1.
5 test input. The test output signal of the memory under test 15 enters the level comparator 16, where it is converted into a binary value ('1" or @O") based on a predetermined reference level, and then enters the digital comparator 17. The digital comparator 17 receives the delay test pattern that has passed through the delay circuit section 2o, and compares the expected test output value included in this test pattern with the output (test output) from the level comparator 16. Then, a pass or fail determination is made, and when a fail determination is made, a fail output is generated and input to the counter section 22.

By the way, before executing the above test pattern, the type of clock to be applied to the delay/counter section 20 is selected by the clock selection circuit 27, and the delay time of the delay circuit of the delay circuit section 20 is set to ~Dn (basic delay time). td) is appropriately set according to the measurement timing item of the memory under test 15. And while performing one test ivy turn,
The delay/counter unit 20 is caused to perform the following operations. That is, in the first cycle, only the switch circuit S of the switch circuits S and -Sn is controlled to the second output state, and a delay circuit is connected to the test pattern input.

gives the delay time td. As a result of the memory test at this time, if a fail output occurs, the counter C4
A fail count operation is then performed. In the next cycle, only the switch circuit S2 is set to the second output state, and a delay time of 2td due to the delay circuit D2 is applied to the test pattern input. The result of the memory test at this time was
When a fail output occurs, a fail counting operation is performed by the counter C2. In the same way, the delay time (~ntd) is set up to n cycles and the count operation is performed when a fail output occurs, and this series of operations (1 to n cycles) is repeated until the test pattern is completed. make him return it. Therefore, when the execution of the four turns of death is completed, the fail counters C2 to Cr
If you check the contents of L, you can see the timing values that are measurement items (for example, counters C, C2, C.

If a count output is generated and counters C4 to Cn are in a reset state, the delay time 4td corresponding to counter C4 is regarded as a timing value) and the timing distribution of fail pits can be determined.

In the above embodiment, in order to know the timing distribution status of fail bits, a group of fail counters corresponding to each test pattern delay time is provided and the fail output is counted for each group, but it is possible to simply know the value of timing, which is a measurement item. If it is sufficient, for example, a flag register group is provided in place of the above-mentioned 7-hour counter group, and the contents of the flag register are controlled to be set/reset according to the age of fail output for each test pattern delay time. The timing value may be determined from the contents of the flag register group.

Further, in the above embodiment, a delay time is given to the test input signal, but the point is that a delay means is provided between the timing generator and the test input signal driver to give different delay times to the test input. Just do it.

[Effects of the Invention] As described above, according to the semiconductor device evaluation device of the present invention, it is possible to measure one timing of a memory under test by executing one test turn. The measurement time can be reduced compared to measuring one timing by executing the test pattern several times. In this case, as the test pattern length becomes longer due to the larger capacity of the test memory, improved functionality, etc., and the number of days in which the timing is measured increases, the effect of shortening the measurement time becomes more significant. If the counter is used to count υ in the case of a fail output, there is also the advantage that it becomes possible to obtain the timing distribution status of fail bits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the semiconductor memory evaluation device of the present invention, FIG. 2 is a block diagram showing an example of the delay-counter section in FIG. 1, and FIG. 1 is a block diagram showing a semiconductor memory evaluation device. FIG. DESCRIPTION OF SYMBOLS 11... Timing generator, 12... Test turn generator, 13... Test input waveform mat controller, 14... Test input signal driver, 16... Level comparator, 17... Digital comparator, 19... Test processor, 20... Delay/counter section, 21...
... Delay circuit section, 22... Counter section, 23... Delay/counter selection circuit, 21... Clock selection circuit,
D1-Dn...delay circuit, S, -Sn...switch circuit, C4-Cn...counter.

Claims (6)

[Claims] (1) Convert the test pattern to a test input waveform format and apply it as a test input to the memory under test, and compare the test output of this memory under test with the separately provided expected test output value to determine pass/fail of the test output. In a semiconductor memory evaluation device that measures the timing, which is a measurement item of the memory under test, based on this judgment output, tests are performed by giving different delay times to the test inputs during the execution of one test pattern. A semiconductor memory evaluation device having a plurality of cycles, and measuring the timing based on whether or not the test output for each cycle is a fail output. (2) The means for giving different delay times to the test inputs includes a unit delay time td for each cycle of the test pattern.
2. The semiconductor memory evaluation device according to claim 1, wherein a delay time that gradually changes in a fixed direction is applied to the test pattern. (3) The means for giving different delay times to the test inputs is such that n delay circuits having the same performance and function are continuously connected between the stages through respective switch circuits, and the switch circuits are connected in each cycle. 3. The semiconductor memory evaluation device according to claim 1, wherein the semiconductor memory evaluation device controls the number of delay circuits through which the test pattern passes. (4) The semiconductor memory evaluation device according to claim 3, wherein the selection circuit that controls the switch circuit operates in synchronization with the test pattern. (5) The means for measuring timing based on whether or not the test output is a fail output includes providing n fail counters that count fail outputs for each of the different delay times, and 2. The semiconductor memory evaluation device according to claim 1, wherein the timing distribution situation of fail bits is determined together with the timing value based on each content. (6) The invention further comprises a selection circuit that selectively controls the n fail counters so that they can perform counting operations, and the selection circuit operates in synchronization with the test pattern. The semiconductor memory evaluation device according to item 5.