JP2846383B2 - Integrated circuit test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit test apparatus for testing an integrated circuit device such as an LSI, and more particularly to an integrated circuit capable of measuring a response delay time of an integrated circuit at a high speed. It is intended to provide a circuit test device.

[Prior art] When testing whether or not an integrated circuit has the intended characteristics, a DC test for testing the DC characteristics of the integrated circuit and a functional test for checking whether the circuit operates normally are performed. It is.

In the functional test, a test pattern signal is given to the integrated circuit under test, and a test is performed to determine whether the response output is as expected in accordance with an expected value. There is a test that measures the time until a response signal is output, and determines whether the response is good by checking whether a delay time required for the response is within a predetermined time range.

The present invention relates to an improvement of a test apparatus which is operated when testing whether or not a response delay time of an integrated circuit falls within a prescribed time range. It is an object of the present invention to provide an integrated circuit test device that measures time and enables high-speed processing.

 FIG. 5 shows the configuration of a conventional integrated circuit test apparatus.

In the figure, reference numeral 10 denotes a pattern generator. The pattern generator 10 is generally a sequence controller 11, a control memory 12,
The control memory 12 and the pattern memory 13 are access-controlled by address information output from the sequence controller 11, timing data for generating a test pattern is read from the control memory 12, and the pattern memory 13 , The pattern data and the expected value pattern data are read.

The timing data read from control memory 12 is applied to timing generator 20. The timing generator 20 generates a timing pulse that defines the rising and falling timings of the actual waveform of the test pattern signal to be given to the integrated circuit under test 40 based on the timing data sent from the control memory 12. Pulse to waveform generator 30
Give to.

The waveform generator 30 generates a test pattern signal to be applied to each terminal of the integrated circuit under test 30 according to the timing pulse given from the timing generator 20 and the pattern data given from the pattern memory 13, and To a test pattern signal.

On the other hand, the timing pulse output from the timing generator 20 is also supplied to the comparator 50. The comparator 50 compares the expected value pattern data given from the pattern memory 13 with the response signal of the integrated circuit under test 40 at the timing of the timing pulse given from the timing generator 20. Is determined to be defective.

The test up to this point is a test for asking whether or not a normal operation is performed among the function tests described above.

A test for measuring the response delay time of the integrated circuit under test 40 is performed as shown in FIG.

The test pattern _DiN shown in FIG.
To the data input terminal. The test pattern _DiN is applied to the data input terminal, and the clock CLK shown in FIG.
0 clock input terminal.

FIG. 6C shows the response signal D _out of the integrated circuit under test 40.
The integrated circuit under test extends from the rising timing t _o of the illustrated clock CLK to the rising timing t of the response signal D _out.
A response delay time T _Pd of 40 is shown.

Conventionally, in order to measure the response delay time T _Pd , the timing generator 20 generates a comparison timing pulse CMP shown in FIG. 6E, gives the comparison timing pulse CMP to the comparator 50, and gives the comparison timing pulse CPM. Test pattern to which the integrated circuit under test 40 is input at the specified timing
It is determined whether or not the response signal D _out corresponding to _DiN has been output, by comparing with the expected value pattern.

In the comparator 50, the comparison operation by the comparison timing pulse CMP is performed once every one cycle of the clock CLK.
That comparison timing pulse CMP is provided to comparator 50 while extending the sequential delay time for each of example A pattern of the same pattern starting from the timing t ₀ of the rise of the clock CLK is generated, the integrated circuit under test in a comparator 50 Repeatedly extend the delay time of the comparison timing pulse CMP until the 40 response outputs match the expected value pattern,
When a match is detected, the delay time of the response signal D _out of the integrated circuit under test 40 is defined by associating the delay time of the response signal D _{out with} the delay time of the comparison timing pulse CMP.

"Problem to be Solved by the Invention" As described above, in order to measure the delay time of the response signal D _out of the integrated circuit under test 40, the delay time of the comparison timing pulse CMP is sequentially extended, and the comparator 50 repeats the operation. The response signal D at the supply timing of the comparison timing pulse CMP
This operation is repeated until _out matches the expected value.

In conventional test equipment, the comparison timing pulse CMP
It is necessary to rewrite the timing data stored in the control memory 12 in order to change the occurrence timing.

Therefore, a test pattern is generated for one test cycle,
Before entering the next pattern generation cycle, it is necessary to rewrite the timing data in the control memory. FIG. 7 shows this state. A period XX shown in the figure indicates a time required for rewriting the timing data in the control memory 12.

As described above, since the period XX for rewriting the timing data of the comparison timing pulse CMP is required for each generation cycle of the test pattern, there is a disadvantage that the test time becomes longer.

[Means for Solving the Problems] In the present invention, timing data for pattern generation is read from a control memory constituting the pattern generator, and the timing data is supplied to the timing generator. The timing signal and the pattern data output from the pattern memory are supplied to a waveform generator to generate a test pattern signal, and the test pattern signal is integrated under test. Give to the circuit,
The response signal of the integrated circuit under test is provided to the comparator, the comparator reads the response signal of the integrated circuit under test by the comparison timing pulse, compares the response signal with the expected value pattern, and sends the test pattern signal to the integrated circuit under test. In the integrated circuit test apparatus, a response delay time from when the response signal is given to when a response signal is obtained is measured by a delay time of a comparison timing pulse given from the timing generator to the comparator. A timing data storage for storing time, a comparison timing pulse generation cycle detecting means for detecting a generation cycle of the comparison timing pulse, and a timing data each time the comparison timing pulse generation cycle detection means detects the generation cycle of the comparison timing pulse. Gives the delay time stored in the memory to the timing generator. An integrated circuit test apparatus, comprising: It was done.

According to the configuration of the present invention, it is possible to sequentially extend the delay time of the comparison timing pulse without rewriting the timing data of the control memory. Therefore, the response delay time of the integrated circuit under test can be measured in a short time.

FIG. 1 shows an embodiment of the present invention. In the figure, 10 is a pattern generator, 20 is a timing generator, 30 is a waveform generator, 40 is an integrated circuit under test, and 50 is a comparator as described above.

In the present invention, the pattern generator 10 and the timing generator 20
The comparison timing pulse generation cycle detecting means 61 for detecting the generation cycle of the comparison timing pulse, the timing data storage 62 storing the delay time of the comparison timing pulse, and the comparison timing pulse generation cycle detection means 61 The increment means 63 increments the storage value of the timing data storage 62 every time the pulse generation cycle is detected, and the timing generator 20 every time the comparison timing pulse generation cycle detection means 61 detects the generation cycle of the comparison timing pulse. It is characterized by a structure provided with a timing data selector 64 for switching the applied timing data to the delay time stored in the timing data storage 62.

In this embodiment, the timing data storage unit 62 stores the initial delay time of the comparison timing pulse, and the coincidence detection circuit detects that the timing data corresponding to the initial delay time has been output from the control memory 12. Each time the comparison timing pulse generation cycle detection means 61 detects the generation cycle of the comparison timing pulse, a counter 63A for counting the number of detections and an adder 63B constitute an increment means 63. Is shown.

That is, timing data for generating a pattern is read from the control memory 12. The main part of the timing data read from the control memory 12 is directly applied to the timing generator 20 and is converted into timing pulses, and
Sent to

On the other hand, comparison timing data that specifies the generation timing of the comparison timing pulse sent to the comparator 50 is transmitted through the timing data selector 64 to the timing generator 20.
Given to.

The timing data selector 64 is normally switched to a state in which the comparison timing data read from the control memory 12 is directly input to the timing generator 20. Timing data selector every time
64 selects the comparison timing data stored in the timing data storage 62 and inputs the selected comparison timing data to the comparator 50.

The comparison timing pulse generation cycle detecting means 61 detects the generation cycle of the comparison timing pulse when the comparison timing data in the timing data read from the control memory 12 matches the initial delay time of the comparison timing pulse stored in the timing data storage 62. And outputs a cycle detection signal of the comparison timing pulse.

When the comparison timing pulse generation cycle detecting means 61 detects the generation cycle of the comparison timing pulse, first, the timing data selector 64 is switched and the timing data storage 62
Is selected and given to the timing generator 20. That is, in this embodiment, the addition output of the adder 63B constituting the increment means 63 is selected. At the time of the first detection of the generation cycle of the comparison timing pulse, the count value of the counter 63A is still 0, so the adder 63B uses the timing data corresponding to the initial delay time of the comparison timing pulse read from the control memory 12 as it is. It is taken and sent to the timing generator 20.

At the same time that the timing data selector 64 sends the addition data of the adder 63B to the timing data selector 64, the counter 63A counts the detection signal output from the comparison timing pulse generation cycle detecting means 61 and stores "1".

When the first test is completed and the comparison timing pulse generation cycle detecting means 61 detects the second generation cycle, the adder 63B stores the initial delay time value read from the control memory 12 in the counter 63A at this time. The comparison timing data obtained by adding 1 to the timing generator 20, for example, adding 1N seconds to the initial delay time is input to the timing generator 20.

Each time the generation cycle of the comparison timing pulse is detected in this way, the count value stored in the increment means 63 is incremented by one, and this count value is added to the initial delay time value by the adder 63B and the timing generator 20 Input sequentially.

This will be described with reference to FIGS. 2 and 3. In the example shown in the figure, the case where the timing data B of the comparison timing pulse is read when the address A is read in the control memory 12 is shown.

Each time the timing data B is read, the count value of the counter 63A increases by +1. The timing data supplied to the timing generator 20 is B for the first time, B + 1 for the second time,
The third time changes to B + 2 and the fourth time changes to B + 3. In this way, the timing data given to the comparator 50 is sequentially +
The delay time of the comparison timing pulse is gradually increased by, for example, 1 N seconds, and this operation is repeated until the comparator 50 outputs a coincidence detection signal.

This example shows a case where the comparator 50 can read the response output of the integrated circuit under test 40 by the comparison timing pulse in the fourth test cycle, and the read response signal matches the expected value.

Therefore, the timing data B + 3 applied to the timing generator 50 at this time corresponds to the response delay time of the integrated circuit under test 40.

FIG. 4 shows another embodiment of the present invention. In this example, the comparison timing pulse generation cycle detecting means 61 is composed of a pattern number storage 61A, a pattern counter 61B, and a coincidence detecting circuit 61C.
This shows the case where the configuration is made as follows.

Therefore, in this example, the number of occurrences of the pattern is detected by counting the signal output from the sequence controller 11, and each time the number of occurrences of the pattern reaches the pattern in which the timing data of the comparison timing pulse is written, the coincidence detection circuit 61C outputs It is configured to generate a cycle detection signal.

That is, the signal output from the sequence controller 11 is counted by the pattern counter 61B, and the number of pattern occurrences is counted.

When the number of pattern occurrences matches the number of patterns set in the pattern count storage 61A, the match detection circuit 61C outputs a match detection signal. That is, the number from the pattern at the beginning of the test cycle to the pattern in which the comparison timing data is written is set in the pattern count storage unit 61A, and each time the pattern count is reached, the generation cycle detection signal of the comparison timing pulse is sent from the match detection circuit 61C. Output.

The match detection circuit 61C outputs a cycle detection signal of the comparison timing pulse, so that the timing data selector
64 is switched and selected, and the timing data given from the increment means 63 is selected and output to the timing generator 20.

In this example, the increment means 63 presets data corresponding to the initial delay time of the comparison timing pulse set in the timing data storage 62 using a presettable counter in this example, and in this state, the comparison timing pulse generation cycle detecting means 61 , The increment means 63 adds 1 to the preset value. Therefore, at the time of the second cycle detection, the delayed data which is incremented by 1 is supplied to the timing data selector 64, and the delay time of the comparison timing pulse is sequentially extended.

[Effect of the Invention] As described above, according to the present invention, the comparator 50 can be used without rewriting the timing data stored in the control memory 12.
Since the configuration is such that the supply timing of the comparison timing pulse to be applied to the test is automatically and sequentially delayed for each test, the time required for rewriting can be reduced. Therefore, the response delay time of the integrated circuit can be measured in a short time, and high-speed processing can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining one embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of the main part of the present invention, and FIG. 4 is another embodiment of the present invention. FIG. 5 is a block diagram illustrating an example of the related art, and FIG. 5 is a block diagram illustrating the operation of the related art. 10: pattern generator, 20: timing generator, 30: waveform generator, 40: integrated circuit under test, 50: comparator, 61: comparison timing pulse generation cycle detection means, 62: timing data storage, 63: increment Means, 64: timing data selector.

Claims (3)

(57) [Claims] 1. A. Timing data for pattern generation is read from a control memory constituting a pattern generator, and the timing data is supplied to a timing generator, and the timing generator generates a real waveform of a test pattern signal. The timing signal is converted into a necessary timing signal, and the timing signal and the pattern data output from the pattern memory are supplied to a waveform generator to generate a test pattern signal. The test pattern signal is supplied to an integrated circuit under test, The response signal of the integrated circuit is provided to the comparator, the comparator reads the response signal of the integrated circuit under test by a comparison timing pulse, compares the response signal with an expected value pattern, and provides a test pattern signal to the integrated circuit under test. From the above timing generator to the response delay time from when the response signal is obtained until the response signal is obtained. B. a timing data storage device for storing an initial delay time of the comparison timing pulse, and C. a generation cycle of the comparison timing pulse. D. a comparison timing pulse generation cycle detecting means for detecting; D. each time the comparison timing pulse generation cycle detection means detects the generation cycle of the comparison timing pulse, the delay time stored in the timing data storage is given to the timing generator. A timing data selector, and E. increment means for incrementing the delay time of the timing data storage unit each time the timing data selector selects a set value of the delay time of the comparison timing pulse. Integrated circuit test equipment. 2. The control circuit according to claim 1, wherein said comparison timing pulse generation cycle detecting means includes a timing data storage, and the timing data stored in said timing data storage being read from said control memory. An integrated circuit test apparatus comprising a coincidence detector for detecting. 3. A pattern number storage for storing the number of patterns generated within a predetermined period, and a pattern for counting the number of test patterns applied to an integrated circuit. An integrated circuit test apparatus comprising: a counter; and a coincidence detector for detecting that the number of patterns stored in the pattern number storage unit matches the count value of the pattern counter.