JPH01136080A - Tester for integrated circuit element - Google Patents

Abstract

PURPOSE:To test a logical function and an operation speed simultaneously, by measuring a generation cycle of an input pattern generation trigger signal as generated by an coincidence output between an response output pattern for an input pattern of a device to be measured and an output expectation pattern. CONSTITUTION:A pattern generation circuit 11 reads out an input pattern for testing loaded through a bus B from a computer system (not illustrated) and an output expectation pattern synchronizing a signal from a timing generation circuit 2. The input pattern read out is applied to a device 2 to be measured and a response output thereof is inputted into a coincidence detection circuit 16. The output expectation pattern is also inputted into the detection circuit 16 and when both the outputs coincide, a trigger signal (d) is outputted from a trigger generation circuit 19 to operate a timing generation circuit 12. A counter 20 measures an output interval of the signal (d) and an output thereof is inputted into a decision circuit 23 through a register 21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device testing device for testing the logic function of an integrated circuit device. The present invention relates to an integrated circuit device testing device that enables testing of integrated circuit devices.

[Prior Art] A test device for testing the logic function of an integrated circuit element generally generates an input pattern to be applied to a device under test and an expected output pattern that is an expected value as a response output of this input pattern. The quality of the device under test is determined by comparing the response output when the input pattern is given to the device under test and the expected output pattern.

In conventional test equipment of this type, the cycle at which the input pattern is input to the device under test, that is, the test cycle is:
It is set by a program or the like to a constant value that takes into account the response speed of the device under test.

[Problems to be Solved by the Invention] Generally, there are variations in the operating speed of integrated circuit elements and the access time of memory. Therefore, when determining the test cycle for logic function tests, it is necessary to take this variation into consideration and set the cycle to a certain degree of margin. This results in an increase in time.

Furthermore, if the operating speed, access time, etc. of the device under test are significantly lower than standard values, a comparison with the expected output pattern is performed before a response output to the input pattern is obtained. As a result, in this case as well, the product is determined to be defective, so there is a problem in that it is difficult to determine whether it is a defect in logic function or operation speed.

Furthermore, when measuring the maximum operating speed or access time of the device under test and sorting the ranks based on the operating speed of the device under test, the conventional test equipment described above can change the test cycle to several stages depending on the test program. It is necessary to rank the products by repeating the same test multiple times while changing the number of products and finding the limit value between good products and defective products.

As a result, the test time becomes long, and although conventional integrated circuit device (LSI) test equipment is expensive, it has the drawback of low throughput.

The present invention has been made in view of these problems, and is a test for integrated circuit devices that can shorten the test time and simultaneously perform a logic function test and an operation speed measurement in -1 tests. The purpose is to provide equipment.

[Means for Solving the Problems] An integrated circuit device testing device according to the present invention includes a pattern generation circuit that generates an input pattern and an expected output pattern, and a pattern generation circuit that generates an input pattern and a device under test based on a trigger signal. a timing generation circuit that controls the timing of the input pattern; a comparison circuit that inputs the response output pattern of the device under test to the input pattern and the expected output pattern and compares both patterns; The present invention is characterized in that it includes a trigger signal generation circuit that generates a trigger signal, and a counter that measures the generation cycle of the trigger signal output from the trigger signal generation circuit.

[Operation] According to the present invention, immediately after obtaining a response output pattern for an input pattern, when the pattern comparison circuit obtains a match between this pattern and the expected output pattern,
Depending on the output 1. A trigger signal is generated. This trigger signal prompts the transmission of the next input pattern to the device under test, so the transmission period of the input pattern, that is, the test period, must be completely synchronized with the response time of the device under test or the delay characteristics of the internal elements. Become. Therefore, there is no waste in test time and the test time can be shortened.

Further, according to the present invention, since the period of the trigger signal is measured by a counter, the operating speed or access time of the device under test can be obtained as a quantitative value. Therefore, it is possible to determine the type of failure, malfunction, or operation speed failure.

In addition, selection for ranks of operating speeds can be performed in one test.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an LSI test device according to this embodiment. The test device 1 is connected via a bus B to a computer system (not shown). The test apparatus 1 is equipped with an external terminal T, and is configured so that a device under test 2 can be appropriately connected to this external terminal T to perform a test.

Next, the specific configuration of the test device 1 will be explained. A bus B from the computer system is connected to a pattern generation circuit 11, a timing generation circuit 12, and an expected value register 22. The pattern generation circuit 11 sequentially reads test input patterns and expected output patterns loaded in advance from the computer system via bus B at high speed.
Consists of high-speed buffer memory.

The ρ bit (,
&=m+n), an input pattern consisting of m bits is given to the input pulse modulation circuit 13, and an output expected pattern consisting of n bits among the p bits of pattern data is given to the expected waveform modulation circuit 14. It is given.

The timing generation circuit 12 reads pattern modulation information loaded from a computer system, such as phase information and pulse width information from a reference clock, in synchronization with a trigger signal to be described later. Information for pattern modulation from this timing generation circuit 12 is also given to an input pulse modulation circuit 13 and an expected waveform modulation circuit 14, respectively.

The input pulse modulation circuit 13 modulates the input pattern based on pattern modulation information and outputs an input pulse waveform. In this example, the input pattern is an input pulse waveform that is a serial pattern, but of course it may be a parallel pattern. The input pulse waveform is amplified by the driver 15 and applied to the input terminal of the device under test 2 via the external terminal T.

On the other hand, the expected value waveform modulation circuit 14 includes the pattern generation circuit 1
The expected output pattern given from 1 is modulated based on the pattern modulation information, and is given to one input of each of the n coincidence detection circuits 16 in the form of an n-bit parallel pattern.

Furthermore, the n-bit response output to the input pattern output from the output terminal of the device under test 2 is introduced to each of the n comparators 17 via the external terminal T.

These comparators 17 convert the response output of the device under test 2 into a logic level within the test apparatus 1 and apply it to the other input terminal of the minus number configuration circuit 16 .

- The number output circuit 16 detects the match or mismatch of each corresponding bit between the response output to the input pulse of the device under test 2 and the expected output pattern, and - when they match, "1"°
, and when they do not match, it outputs "0".The AND circuit 18 outputs "1" when all the outputs of these negative number generating circuits 16 are "1"'
In other words, only when all bits of the output of the device under test 2 and the expected output pattern match, "1°" is output.

The output of this AND circuit 18 is led to a trigger signal generation circuit 19. The trigger signal generation circuit 19 generates a trigger signal with a predetermined pulse width based on the output of the AND circuit 18, and is composed of, for example, a one-shot circuit.

The trigger signal generated by the trigger signal generation circuit 19 is supplied to the timing generation circuit 12 as a signal for timing determination, and is also supplied to the counter 20. The counter 20 measures the generation cycle of the trigger signal, and its measured value is stored in the measured value register 21.

The measured value register 21 compares a new measured value with an already stored measured value each time a trigger signal is generated, and stores the larger measured value. Therefore, the counter 20 is stored in the measurement value register 21 after the test using all input patterns is completed.
The maximum value of the measured values is retained. On the other hand, in the second expected value register 22, an expected value for the response time of the device under test 2 is stored in advance from the computer system via the bus B.

The expected value stored in the expected value register 22 and the measured value stored in the measured value register 21 are provided to the determination circuit 23. After the test for all input patterns is completed, the determination circuit 23 compares the expected value and the measured value to determine whether the operating speed of the device is good or bad.

Next, the operation of the test apparatus I configured as described above will be explained with reference to the timing chart shown in FIG.

FIGS. 2(a) to 2(d) show signal timings at points a to d in FIG. 1, respectively.

First, the pattern generation circuit 11 and the timing generation circuit 1
2, the first input pattern (a) and the expected output pattern (c) are respectively output as shown in A in the figure.

Device under test 2 for this first input pattern
When the response output (b) from
) are obtained, and the next input pattern (a) and expected output pattern (c) are then output.

At this time, the counter 20 also starts counting. If the response output (b) to the input pattern (a) that occurred at the point of mouth is obtained at point C, the next trigger signal (
d) occurs. The counter 20 outputs the measured value up to this point to the measured value register 21 and starts measuring the next trigger cycle. By repeating this, the maximum value of the trigger cycle indicating the operating speed is obtained in the measured value register 21 at the end of the logic function test.

In this manner, according to the test apparatus of this embodiment, the transmission cycle of the input pattern, that is, the test cycle, is synchronized with the operating speed of the device under test, so there is no wasted test time.
Since it is possible to quantitatively understand the operating speed with a single test, it is possible to analyze the cause of defects and sort them according to their rank.
This can be done in one test.

Note that the present invention is not limited to the embodiments described above. For example, in the above embodiment, the upper limit value of the counter 20 is not specifically defined, but when the device under test 2 outputs a pattern different from the expected output pattern for a certain input pattern, the logic function malfunctions), the trigger signal In order to prevent the test equipment from being stopped due to no occurrence of the error, an upper limit value is set on the counter, and when the measured value of the counter reaches this upper limit value, it is determined that the device under test is malfunctioning. It is also possible to determine this and generate a trigger signal for prompting the output of the next input pattern.

Furthermore, in the above embodiment, the expected value register and the judgment circuit are used to determine the pass/fail, but it is also possible, for example, to read the value of the measured value register by an external computer system and use the software of the computer system to determine the pass/fail. be.

[Effects of the Invention] As explained above, according to the present invention, the output of the device under test is constantly monitored, the response time or delay of the device under test is synchronized with the input pulse test period for each pattern, and further, By measuring the interval between synchronized trigger signals with a counter, the maximum operating speed or access time of the device under test can be obtained as a quantitative value, making it possible to constantly monitor variations that occur during the manufacturing process.
Furthermore, it is possible to obtain an extremely reliable test device that can also support quality assurance of final products. In addition, even when selecting ranks such as operating speed and access time, they can be set freely by processing the measured values obtained as quantitative values, so the number of tests is only one, and the test equipment is This has the effect of dramatically improving throughput.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an integrated circuit device testing apparatus according to an embodiment of the present invention, and FIGS. 2(a) to 2(d) are time chart diagrams showing signal timings at points a to d in FIG. 1, respectively. It is. DESCRIPTION OF SYMBOLS 1; Test equipment, 2; Device under test, 11; Pattern generation circuit, 12; Timing generation circuit, 13; Input pulse modulation circuit, 14; Expected waveform modulation circuit, 15; Driver, 16; - Number configuration circuit, 17 ;Comparator, L8:A
ND circuit, 19; trigger generation circuit, 20; counter circuit, 21; measured value register, 22; expected value register, 2
3; Judgment circuit a) Figure 2

Claims (1)

[Claims] a pattern generation circuit that generates an input pattern and an expected output pattern; a timing generation circuit that controls the timing of applying the input pattern to the device under test based on a trigger signal; and a response output pattern of the device under test to the input pattern. a comparison circuit that inputs and the expected output pattern and compares both patterns; a trigger signal generation circuit that generates the trigger signal based on a matching output from the pattern comparison circuit; and the trigger that is output from the trigger signal generation circuit. 1. A test device for integrated circuit devices, comprising: a counter for measuring a signal generation cycle.