JPH0439627B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit testing device for testing logic circuits such as semiconductor integrated circuits, and in particular to a logic circuit testing device for testing logic circuits such as semiconductor integrated circuits by setting the initial state of a plurality of logic circuits under test. Regarding circuit testing equipment.

<Background of the Invention> When performing a functional test of a logic circuit, a test pattern and an expected value pattern are generated from a pattern generator in a logic circuit testing device, and the test patterns are applied to the logic circuit under test. The quality of the logic circuit under test is determined by comparing the data output from the logic circuit under test with the initial value pattern.

A schematic configuration of this logic circuit test is shown in FIG.
In FIG. 1, a pattern generator 11 generates a test pattern D and an expected value pattern E. In FIG.
The test pattern D is waveform-shaped by the waveform shaping circuit 12 and applied to the logic circuit under test 13 . The expected value pattern E is delayed in the delay circuit 14 by a time corresponding to the operation delay time of the waveform shaping circuit 12 and the logic circuit under test 13. Logic circuit under test 13
The data from the delay circuit 14 and the expected value pattern from the delay circuit 14 are applied to the comparison circuit 15, and when a strobe signal is applied from the terminal 42, the two are compared and the comparison output is sent to the terminal 41.

When testing the functionality of a logic circuit under test, such as a microprocessor, by applying test patterns in this way, it is generally recommended to set the logic circuit under test to an initial state in advance and then apply the test patterns one after another. I have to. For this reason, for example, a reset signal is applied from the logic circuit testing apparatus to the logic circuit under test to bring it into an initial state before applying the test pattern.

However, some logic circuits under test do not have a special terminal, such as a reset terminal, for setting the internal state of the logic circuit to an initial state. Such a logic circuit under test is brought to an initial state by applying a special pattern to an input terminal a predetermined number of times to advance the internal state. In other words, this logic circuit under test is set to the initial state every time a special pattern for advancing the internal state is applied a predetermined number of times, for example 16 times, and this number of times is known according to the specifications of the logic circuit under test. Therefore, even if it does not have a reset terminal or the like, it can be set to the initial state by a signal from the logic circuit testing device, and a test can be started after being set to the initial state.

In this case, the number of times the above special pattern is applied to reach the initial state of the logic circuit under test depends on the state of use of the logic circuit under test before the application of the special pattern and the accidental state settings caused by turning on the power. It is indeterminate because it is different, and in the above example, it could be 0 to 15 times.

In order to perform a functional test of such a logic circuit using the conventional logic circuit testing apparatus shown in FIG _. , the expected value pattern indicating the initial state of the logic circuit under test.
E ₀ is repeatedly generated, and the special pattern D ₀ is applied to the logic circuit under test, and the comparison circuit 15 determines that the output data from the logic circuit under test matches the expected value pattern E ₀ indicating its initial state. Detected with
After that, the original test patterns D ₁ , D ₂ , D ₃ . . . are applied to start the test.

As a conventional example, there is Japanese Patent Application No. 57-206507 (Japanese Unexamined Patent Publication No. 59-97065). As mentioned in this example, the match signal from the comparison output is normally fed back to the pattern generator, which changes the expected value pattern E ₀ to the expected value pattern E1, E2, E3, etc.
It is configured to advance to... Also, in the original expected value patterns E1, E2, E3...
Passage or failure is determined, but at this time, the above-mentioned coincidence detection is ignored. However, when testing multiple such logic circuits under test at the same time, the number of times the special pattern D ₀ must be applied to obtain the initial state differs depending on the individual logic circuits under test, as described above. It is not possible to set the initial state of a plurality of these at the same time, and therefore it is not possible to test a plurality of them at the same time. In other words, when testing multiple logic circuits under test by applying test signals at the same time, the special pattern D ₀ is repeatedly applied in common to set the initial state. The test logic circuit deviates from its initial state because the special pattern D ₀ is repeatedly applied until other logic circuits under test reach their initial states. Therefore, it is not possible to test by giving a common test pattern to a plurality of logic circuits under test.

As described above, with the conventional logic circuit testing apparatus, it is difficult to simultaneously test a plurality of logic circuits to be tested whose initial state is obtained by repeatedly applying the above-mentioned special pattern.

<Object of the Invention> The present invention aims to eliminate such drawbacks and provide a logic circuit testing device capable of simultaneously testing a plurality of logic circuits.

<Summary of the Invention> According to the invention, there is provided a hold circuit for temporarily holding a test pattern, and a hold signal generation circuit for generating a hold instruction signal in the hold circuit when the logic circuit under test reaches an initial state. are provided corresponding to each logic circuit under test, and furthermore, an all match signal generating circuit is provided for generating a match signal when all the logic circuits under test reach an initial state.

When the logic circuit under test reaches the initial state by repeatedly applying the special pattern, it is compared with the expected value pattern indicating the initial state in the comparison circuit to generate a match signal, and this match signal drives the hold signal generation circuit. is used to generate a hold signal. This hold signal causes the hold circuit corresponding to the logic circuit under test that has reached its initial state to hold the special pattern. Therefore, the special pattern is fixedly applied to the logic circuit under test and is not applied repeatedly, so the logic circuit under test does not advance its internal state but maintains its initial state.

In this way, the hold circuits corresponding to the logic circuits under test that have reached the initial state operate to maintain the initial state, and the special pattern is repeatedly given to other logic circuits under test that have not yet reached the initial state. . Therefore, the logic circuit under test that reaches the initial state first will maintain its initial state until all other logic circuits under test reach the initial state, so when the last logic circuit under test reaches the initial state, all It is possible to detect that the logic circuit under test has reached the initial state, and thereby the all-match signal generation circuit generates a match signal.

This all-match signal releases the hold of the hold circuit, and a test pattern is applied from the pattern generator to each logic circuit under test.

As described above, according to the present invention, by adjusting the initial state setting of each logic circuit under test to the timing of the logic circuit under test that reaches its initial state latest, the internal states of all the logic circuits under test can be checked simultaneously. It can be set to an initial state, and therefore a plurality of logic circuits under test can be tested simultaneously in a common sequence thereafter. Furthermore, in this invention, if some of the logic circuits under test are defective and the initial state cannot be reached even after adding a special pattern, it is possible to detect which logic circuit under test is defective using the reading means. . Furthermore, in that case, for the detected defective logic circuit under test, a masking means is provided to prevent the output data from the logic circuit under test from affecting other logic circuits under test. Therefore, even if there is a defective logic circuit under test, the above-mentioned all-match signal is obtained from other logic circuits under test, and the test can be continued.

<Embodiment of the Invention> FIG. 2 shows the configuration of an embodiment of the invention. For simplicity, this example shows a case where two logic circuits under test are tested simultaneously. In the figure, numeral 11 is a pattern generator that generates a test pattern D and an expected value pattern E. Hold circuits 16 and 17 provide the test pattern given from the pattern generator 11 to the waveform shaping circuits 12 and 18, and also hold the test pattern at that time when a hold signal is applied. Waveform shaping circuit 12,1
8 shapes the test pattern into an appropriate waveform depending on the logic circuit under test, such as RZ or NRZ, and supplies it to the logic circuits under test 13 and 19.

15 and 20 are comparison circuits to which the output data from the logic circuits under test 13 and 19 and the expected value pattern delayed by the delay circuit 14 are applied, and when a strobe signal is applied from the terminal 42, the output data and the expected value pattern are applied. Compare with the value pattern and send the comparison result. 24 and 25 are flip-flops, and the comparison results sent from comparison circuits 15 and 20 are applied to set terminals via AND circuits 30 and 31. The other input terminals of the AND circuits 30 and 31 are supplied with mask signals from terminals 44 and 45.
It is applied to the circuit 26, and the output is sent to the hold circuit 1.
6 and 17 as a hold signal. 3
6 and 37 are flip-flops, and comparator circuit 1
The comparison results from 5 and 20 are AND circuits 30 and 31
is applied to the SET terminal via the SET terminal. The outputs of the flip-flops 36 and 37 are given to AND circuits 32 and 33, respectively, and the contents are read out from the terminals 47 and 33 by the read signal from the terminal 46, respectively.
48. flipflop 24,2
5, 36, and 37 are reset by the rising edge of the initial state test signal applied from the terminal 43.

The output signal of the AND circuit 26 is outputted from the terminal 41 and is also applied to the OR circuit 27 to indicate that a complete match has been achieved. The OR circuit 27
The output signal from the AND circuit 26 and the initial state test signal from the terminal 43 are transferred to the flip-flop 24,
25 reset terminal.

The operation of this embodiment will be explained with reference to FIGS. 2, 3, and 4. A test pattern D and an expected value pattern E are generated from a pattern generator at the cycle of the operating clock. As mentioned above, in order to advance the internal state of the logic circuit under test to the initial state before starting a normal test, the special pattern D ₀ and the expected value pattern E ₀ indicating the initial state are generated by the pattern generator 1.
It is generated repeatedly from 1. At the start of the operating period for setting this initial state, an initial state test signal 102 is applied from terminal 43 to flip-flop 36,
37, flip-flop 2 via OR circuit 27
4 and 25, respectively, and the flip-flops 24, 25, 36, and 37 are reset by the rise of these signals. Strobe signal 101 from terminal 42
At the timing, the output data of the logic circuits under test 13 and 19 are compared with the expected value E ₀ by the comparison circuits 15 and 20, and the comparison results are output. In this example, the logic circuit under test 13 has a special pattern D ₀ of 2
As a result of being applied twice, the initial state is reached, and the comparison output 103 becomes a high level.

As a result, flip-flop 24 is set,
Its Q output 105 becomes high level, and the output 10
6 is a low level. The hold circuit 16 is set to the hold state by this output 106, and the output 111 of the hold circuit 16 has a special pattern.
Hold D ₀ . Similarly, flip-flop 36 is also set and its output is transmitted to AND circuit 32.
Since the logic circuit under test 19 has not yet reached its initial state, the application of the special pattern D ₀ is repeated (112). Output 1
04 is a high level. Therefore, the flip-flop 25 is set, its Q output 107 goes high, and its output 108 goes low, giving a hold instruction to the hold circuit 17. Similarly, flip-flop 37 is also set and its output becomes high level and is transmitted to AND circuit 33.

This example shows the case of two logic circuits under test, and as a result, all the logic circuits under test have reached the initial state. Therefore, the Q output 105 of the flip-flop 24 and the Q output 107 of the flip-flop 25 are both at high level, and the AND circuit 26 outputs a signal indicating that all the logic circuits under test match the initial state (109). When this complete match signal is output, the flip-flops 24 and 25 are reset via the OR circuit 27. Therefore, the holds of the hold circuits 16 and 17 are released _, and the test patterns can be sequentially applied to the logic circuit under test, and as shown in FIG. 3, for example, the test patterns D ₁ , D ₂ . , E ₂ . . . are generated by the pattern generator 11, and a normal test is started.

As described above, according to the logic circuit testing device according to the present invention, even if there is a difference in the time it takes to reach the initial state among a plurality of logic circuits under test, the logic circuit under test that reaches the initial state the latest is the one that reaches the initial state. Since the other logic circuits under test wait while maintaining their initial states until the Tests can be performed in parallel by applying test patterns.

In addition, in this invention, if there is a logic circuit under test that does not reach the initial state even after applying a special pattern a predetermined number of times due to a defect, the defective logic circuit under test is detected, its influence is removed, and other logic circuits under test are The initial state of the test logic circuit can be set and the test can be continued. This operation will be explained using FIG. 4.
FIG. 4 shows a case where the logic circuit under test 19 is defective and does not return to its initial state even if the special pattern D ₀ is repeatedly applied.

Logic circuit under test 13 is the first special pattern
The initial state is reached by D ₀ , and the comparison circuit 15 sends out a match signal (103), but the logic circuit under test 19
is defective, so it does not reach the initial state and no match signal is generated (104). Therefore, the output (114) of flip-flop 36 is at a high level, and the output (115) of flip-flop 37 is at a low level.
Even after applying the special pattern D ₀ a predetermined number of times, the AND circuit 26 does not output an all-match signal (109), so the one-way initial state test is stopped, and in order to find out which logic circuit under test is defective, the terminal A read signal 116 is applied from 46. Read signal 1
16 opens the AND circuits 32 and 33, and the output signals 114 and 1 of the flip-flops 36 and 37
Signals 117 and 118 corresponding to No. 15 are read out. As a result, it is detected that the logic circuit under test 19 is defective.

Due to the presence of the logic circuit under test 19
A mask signal 119 is applied from the terminal 45 in order to avoid not being able to obtain an all-match signal from the AND circuit 26 and therefore not being able to test other normal logic circuits under test. This mask signal 119 closes the AND circuit to prevent the signal from the comparison circuit 20 from being transmitted to the subsequent stage, and
A high level is applied to the AND circuit 26 via the OR circuit 35. In this state, the initial state test signal 102 is applied again to set the initial states of the logic circuits under test other than the logic circuit under test 19. In FIG. 4, the first application of the special pattern D ₀ puts the logic circuit under test 13 into the initial state, and the all-match signal is sent to the AND circuit 2 regardless of the logic circuit under test 19.
Generated from 6. The flip-flop 24 is reset by the rise of this all-match signal, the hold of the hold circuit 16 is released, and the pattern generator 11 generates test patterns D ₁ , D ₂ . . . and expected value patterns E ₁ , E ₂ . A normal test is then performed.

Note that after the expected value patterns E1, E2, E3, . . . are generated and the test moves to applying the original test pattern, the same operation as in the conventional example is performed, and the original pass/fail test is performed. At this time, the above-mentioned coincidence detection is ignored, so the test pattern hold operation is not performed, and the original pass/fail test is not affected. As described above, according to the logic circuit testing device according to the present invention, all the plurality of logic circuits under test can be set to the initial state and tested simultaneously, and even if there is a faulty logic circuit under test, it can be tested. Tests can be performed with the effects removed.
In the above explanation, the case where there are two logic circuits under test has been described, but it is clear that the test can be performed in the same way even when there are three or more logic circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional logic circuit testing device, FIG. 2 is a block diagram showing the configuration of an embodiment of the logic circuit testing device according to the present invention, and FIG.
This figure and FIG. 4 are time charts for explaining the operation of the logic circuit testing apparatus shown in FIG. 2. 11: Pattern generator, 12, 18: Waveform shaping circuit, 13, 19: Logic circuit under test, 15, 2
0: comparison circuit, 16, 17: hold circuit, 1
4: Delay circuit, 24, 25, 36, 37: Flip-flop.

Claims (1)

[Claims] 1. Generate a test pattern and an expected value pattern from a pattern generator, apply the test pattern to a logic circuit under test, and compare data output from the logic circuit under test with the expected value pattern. In a logic circuit testing device that determines the acceptability of a logic circuit under test by B. Hold signal generation means for generating a signal to hold the logic circuit under test; B. Full match signal generation means for generating a signal indicating that all of the data from the plurality of logic circuits under test match the expected value pattern; C. To hold the test pattern applied to the logic circuit under test that matches the expected value pattern by the hold signal from the hold signal generating means until the full match signal generating means sends out the matching signal. D. A reading means for reading out the state of match or mismatch with the expected value pattern for each logic circuit under test; E. A masking means for masking the comparator output from a defective logic circuit under test. What is claimed is: 1. A logic circuit testing device comprising: