JPS59221679A - Testing device for logical circuit - Google Patents

Abstract

PURPOSE:To test simultaneously plural logical circuits by holding a test pattern when a logical circuit to be tested reaches an initialized state and releasing the holding state when all logical circuits reach the initialized state and taking the test. CONSTITUTION:The test pattern D from a pattern generator 11 is supplied to logical circuits 13 and 19 to be tested through holding circuits 16 and 17, and their outputs are compared by comparing circuits 15 and 20 with an expected value pattern E from a generator 11. When a coincidence signal is obtained, FFs 24 and 25 are set and a hold signal is supplied to the holding circuits 16 and 17. When both FFs 24 and 25 are set, an AND circuit 26 generates an output to reset the FFs 24 and 25, taking a normal test. Thus, plural logical circuits are tested simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit testing device for testing logic circuits such as semiconductor integrated circuits. Logic circuit testing equipment (related to this).

<Background of the Invention> When performing a functional test of a logic circuit, a test pattern and an expected value pattern are generated from a pattern generator in a logic circuit testing device, and the test pattern is marked on the logic circuit under test. The quality of the logic circuit under test is determined by comparing the data output from the logic circuit under test with the expected value pattern.

The schematic configuration of this logic circuit test is shown in FIG.

In FIG. 1, a pattern generator 11 generates a test pattern D and an expected value pattern E. In FIG.

The waveform of the test wave D is shaped by the waveform shaping circuit 12 and applied to the logic circuit under test 13. The expected value pattern E is delayed by a time corresponding to the operation delay time of the waveform shaping circuit 12 and the logic circuit under test 13 in the delay circuit 14&. Data of logic circuit under test 13 and delay circuit 14
The expected value pattern from is applied to the comparison circuit 15, and when a strobe signal is applied from the terminal 42, the two are compared and the comparison output is sent to the terminal 41.

When testing the functionality of a logic circuit under test, such as a microprocessor, by applying test patterns in this way, it is common practice to set the logic circuit under test to an initial state in advance and then apply the test patterns one after another. I'm trying to do it. For this reason, before applying the test pattern, the logic circuit testing device applies, for example, a reset signal to the logic circuit under test to bring it into an initial state.

However, some logic circuits under test do not have a special terminal, such as a reset terminal, for setting the internal state of the logic circuit to an initial state. In such a logic circuit under test, the input terminal is brought into an initial state by applying a special pattern for advancing the internal state a predetermined number of times. That is, in this logic circuit under test, a special pattern for advancing the internal state is applied a predetermined number of times, for example, 16 times [so that the initial state is reached every time IJ is applied, and this number of times is equal to Since the specifications of the circuit are already known, the initial state can be set from the signal from the logic circuit testing device without having a reset terminal or the like, and a test can be started with the initial state set.

In this case, how many times the above special pattern must be applied before the logic circuit under test reaches its initial state depends on the state of use of the logic circuit under test before the application of the special pattern and the power-up. This is uncertain because it varies depending on the state setting, and in the above example, the number may be 0 to 15 times.

In order to perform a functional test of such a logic circuit using the conventional logic circuit test equipment shown in Figure 1, a pattern generator 1 is required.
1, a special pattern Do for advancing the internal state of the logic circuit under test 13 and an expected value pattern E indicating the initial state of the logic circuit under test are repeatedly generated. The comparison circuit 15 detects that the output data from the logic circuit under test matches the expected value pattern EO that exceeds its initial state, and then the original test patterns Di, IJ2 . D3...
... is applied to start the test.

However, when testing multiple logic circuits under test at the same time (in this case, how many times the special pattern D is applied as described above), the number of each logic circuit under test will determine how many times the initial state can be obtained. Because of this difference, it is not possible to set the initial state of multiple logic circuits at the same time, and therefore it is not possible to test multiple logic circuits at the same time.In other words, test signals are applied to multiple logic circuits under test at the same time. When testing, the initial state is set by repeatedly applying the special pattern D. Therefore, the logic circuit under test that reaches the initial state first must wait until other logic circuits under test reach the initial state. Because the special pattern D is repeatedly applied during the test, the initial state deviates from the initial state. Common (You cannot test by giving this test pattern.

As described above, with the conventional logic circuit testing apparatus, it is difficult to simultaneously test a plurality of logic circuits under test whose initial states are obtained by repeatedly applying the above-mentioned special pattern.

<Objective of the Invention> The present invention aims to eliminate such drawbacks and provide a logic circuit testing device capable of simultaneously testing a plurality of logic circuits.

<Summary of the Invention> According to the present invention, there is provided a hold circuit for temporarily holding a test pattern, and a control circuit that generates a hold instruction signal for the hold circuit when the logic circuit under test reaches an initial state.
A hold signal generation circuit for each logic circuit under test Q
Correspondingly, an all match signal generating circuit is provided for generating a match signal when all logic circuits under test reach an initial state.

Tested by repeatedly applying a special vacuum.
When the logic circuit reaches the initial state, it is compared with an expected value pattern indicating the initial state in a comparison circuit to generate a match signal, and this match signal drives a hold signal generation circuit to generate a hold signal. This hold signal causes the hold circuit corresponding to the logic circuit under test that has reached its initial state to hold the special pattern. Therefore, the special pattern is fixedly applied to the logic circuit under test, and since [1j is not added repeatedly, the logic circuit under test does not advance its internal state and maintains its initial state.

In this way, the hold circuits corresponding to the logic circuits under test that descend from the initial state operate to maintain the initial state.
Descendants of other logic circuits under test that have not yet reached the initial state (have not yet reached the initial state) are given a special pattern repeatedly. Since the initial state is maintained until the initial state is reached, when the last logic circuit under test reaches the initial state Q, it is possible to detect that all the logic circuits under test have reached the initial state. A coincidence signal is generated from the coincidence signal generation N path.

The hold of the hold circuit is released by this all match signal, and a test pattern is applied from each logic circuit under test (this pattern generator).

In this way, the present invention is capable of setting the initial state of each logic circuit under test by adjusting the timing of the logic circuit under test that reaches the initial state latest. Since the internal state is set to the initial state at the same time, multiple logic circuits under test can be tested simultaneously in a common sequence. If there is a defect and the initial state cannot be reached even if a special pattern is added, it is possible to detect which logic circuit under test is defective using the reading means.Furthermore, in this case, the logic under test of the detected defect To prevent circuit defects, masking means is provided to prevent the output data from the logic circuit under test from affecting other logic circuits under test. The above-mentioned all-match signal is obtained from other logic circuits under test, and the test can be continued.

<Embodiments of the invention> FIG. 2 shows the configuration of an embodiment of this invention.

For simplicity, this example shows a case where two logic circuits under test are simultaneously tested. In the figure, 1-1 is a pattern generator which generates a test pattern D and an expected value pattern E. 16.17 is a hold circuit, and pattern generator 1
The test pattern given from 1 to the waveform shaping circuit 12, 1
8 (when the hold circuit is applied, the test pattern at that time is held. Waveform shaping circuit 1
2.18 shapes the test pattern into an appropriate waveform according to the logic circuit under test, such as t<z, NRz, etc., and provides the logic circuit under test 13.19.

15.20 is a comparison circuit, and the logic circuit under test 13.1
The output data from the terminal 9 and the expected value pattern delayed by the delay circuit 14G are applied, and when a strobe signal is applied from the terminal 42, the output data and the expected value pattern are compared and the comparison result is sent out. Reference numeral 25 is a solid flop, and the comparison results sent from comparison circuits 15 and 20 are applied to a set terminal via AND circuits 30 and 31. A mask signal from a terminal 44.45 is applied to other input terminals of the AND circuit 30.31. .

The Q outputs of the flip-flops 24 and 25 are respectively given to the AN'D circuit 26 via OR circuits 34 and 35.
The Q output is provided to the hold circuit 16.174 as a two hold signal. 36.37 is a flip-flop,
The comparison results from the comparison circuits 1b and 20 are sent to the AND circuit 30,
A set terminal is provided through 31. The outputs of the flip-flops 36 and 37 are respectively connected to an AND circuit 32.
334 are provided, and the contents thereof are read out to terminals 47 and 48 by a read signal from terminal 46, respectively. Flip-flop 24.25.36.37 is terminal 4
The rising edge of the initial state test signal applied from step 3 causes a rise of seven times.

The output signal of the AND circuit 26 is outputted from the Q terminal 41 and given to the 20R circuit 27 to indicate that a complete match has been achieved. (The JR circuit 27 is an AND circuit 26
and the initial state test signal from terminal 43 to the reset terminals of flip-flops 24 and 25.

The operation of this embodiment will be explained with reference to FIGS. 2, 3, and 4. A test pattern D and an expected value pattern E are generated from a pattern generator at the cycle of the operation clock. As mentioned above, when starting a normal test, the special pattern Do and the expected value pattern E indicating the initial state are used as a pattern generator to advance the internal state of the logic circuit under test to the initial state. 11. At the beginning of the operating period for setting this initial state, an initial state test signal 102 is generated from terminal 43 to flip-flops 36, 37, .
Flip-flop 24.254 via OR circuit 27
The rising edge of each signal resets the flip-flops 24, 25, 36, and 37. terminal 4
At the timing of the strobe signal 101 from 2, the output data of the logic circuit under test 13.19 is compared with the expected value Eo by the comparison circuit 15.20, and the comparison result is output. In this example, the logic circuit under test 1.3 is a special pattern D
As a result of being applied twice, the initial state is reached, and the comparison output 1θ3 becomes a high level.

As a result, the flip-flop is set, its Q output 105 goes to plane level, and its Q output 106 goes to low level. This Q output 106 G (b) V +' circuit 16 is set to the bold state Q (bold circuit 1).
The function 111 of No. 6 holds the special pattern J)o. Similarly, flip-flop 36 is also set, and its output is
The information is transmitted to the D circuit 32. The logic circuit under test 20 is still in its initial state! Since I haven't reached 1 yet, I will continue with the special pattern - DoQ.
The application is repeated (112), and in this example, when the special pattern is applied five times, it becomes the initial state, and the comparison circuit 2o
The output 104 of becomes high level. Therefore, the flip-flop 25 is set, its Q output 107 goes high, and its Q output 108 goes low, giving a hold instruction to the hold circuit 17. Similarly, flip-flop 37 is set and its output becomes high level, AND
The signal is transmitted to the circuit 33.

This example excludes the case of two logic circuits under test.
As a result, all logic circuits under test have reached their initial state. For this reason, the Q output of the flip-flop is 105
Both the Q output 107 of the flip-flop 25 and the Q output 107 of the flip-flop 25 are at the device level, and the AND circuit 26 outputs a signal indicating that all the logic circuits under test match the initial state (
109).

When this complete match signal is output (via the JR circuit 27, the flip-flops 24 and 25 are reset.

Therefore, the holds of the hold circuits 16 and 17 are released, and the test patterns can be sequentially applied to the logic circuit under test, as shown in FIG.
)2..., JtlJ waiting value pattern E□, E2・
. . . A wave is generated by the pattern generator 11 and a normal test is started.

According to this invention (this invention), even if there are differences in the time it takes to reach the initial state among multiple logic circuits under test, the logic circuit under test that reaches the initial state the latest Since the other logic circuits under test wait while maintaining their initial states until the It is possible to test logic circuits in parallel by applying test patterns simultaneously.

In addition, in this invention, if there is a logic circuit under test that does not reach the initial state even if a special pattern is applied a predetermined number of times due to a defect, the defective logic circuit under test is detected, its influence is removed, and other The initial state of the logic circuit under test can be set and the test can be continued. This operation will be explained using FIG. 4. In the fourth case, the logic circuit under test 19
is defective and the initial state cannot be achieved even if the special pattern Do is repeatedly applied.

The logic circuit under test 13 is the first special pattern D.

The initial state is reached and the comparison circuit 15 sends out a match signal (103), but since the logic circuit under test 19 is defective, it does not reach the initial state and no match signal is generated (104).
. Therefore, the output of the flip-flop 36 (114,)
is at a high level, and the output of flip-flop 37 (11
5) is at a low level. Special pattern D. is applied a predetermined number of times, the AND circuit 26 outputs the complete match signal
) is not output, the initial state test is stopped and a read signal 16 is applied from the terminal 46 in order to find out which logic circuit under test is defective. The read signal 116 opens the AND circuits 32.33 and outputs the output signals 114.37 of the flip-flops 36.37. Signals 117 and 118 corresponding to 115 are read out. As a result, it is detected that the logic circuit under test 19 is defective.

Due to the presence of the logic circuit under test 19, the AND circuit 2
In order to avoid not being able to obtain an all-match signal from 6 and therefore not being able to test other normal logic circuits under test,
A mask signal 119 is applied from the terminal 45. This mask signal 119 closes the AND circuit to prevent the signal from the comparator circuit 20 from being transmitted to the subsequent stage, and adds a high level F-1 to the AND circuit 26 via the OR circuit 35. In this state, the initial state test signal 1 is again
02 is applied to set the initial state of the logic circuit under test other than the logic circuit under test 19. In FIG. 4, the first application of the special pattern Do brings the logic circuit under test 13 into an initial state, and a complete match signal is generated from the AND circuit 26 regardless of the logic circuit under test 19. When this all match signal goes up, the flip-flop 24 is reset, the hold of the hold circuit 16 is released, and the test pattern L is sent from the pattern generator 11) 1, D2...
. . , expected value patterns E1, E2, . . . are generated and a normal test is executed.

As described above, according to the logic circuit testing device according to the present invention, it is possible to set all the plurality of logic circuits under test to the initial state and perform simultaneous Q-tests, and also to detect defective logic circuits under test. Even if there is, the test can be performed with that influence removed. In the above explanation, the logic circuit under test is 2
It is clear that the same test can be performed even in the case of three or more (although I have shown this in an elaborate manner).

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional logic circuit testing device, FIG. 2 is a block diagram showing the configuration of an embodiment of the logic circuit testing device according to the present invention, and FIGS. 3 and 4 2 is a time chart for explaining the operation of the logic circuit testing apparatus shown in FIG. 2. FIG. 11: Pattern generator 12. 18: Waveform shaping circuit 13. 19: Logic circuit under test 15. 20: Comparison circuit 16. 17: Hold circuit 14: Delay circuit

Claims (1)

[Claims] Generate a test pattern and an expected value pattern from a pattern generator, apply the test pattern to the logic circuit under test,
A. Data from the logic circuit under test is installed in a logic circuit testing device that determines the acceptability of the logic circuit under test by comparing the data output from the logic circuit under test with an expected value pattern. B. hold signal generating means for generating a signal to hold the test pattern applied to the logic circuit under test when the expected value pattern matches the expected value pattern; An all-match signal generating means that generates a signal indicating that the value pattern matches, and a hold signal from the above-mentioned hold signal generating means until the all-match signal generating means C9 sends out a matching signal. A hold circuit holds the test pattern given to the logic circuit under test that matches the value pattern, and a gamma circuit that reads out the state of match or mismatch with the expected value pattern for each logic circuit under test in D1. a reading means; and a masking means for removing data from a defective logic circuit under test so as not to affect the testing of other logic circuits under test; A logic circuit testing device characterized in that it is capable of simultaneously testing logic circuits.