JPH05281307A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor circuit on which operation verifying work can be easily performed in a short time. CONSTITUTION:A varying point detection circuit 2 generates a rise and fall detecting signals 11 and 15 upon detecting the varying point of the output signal 10 of a circuit 1 to be measured and a reference pulse generation circuit 3a (3b) generates a reference pulse signal 12 (16) having the pulse width equal to the output deciding time during the normal operation of the circuit 1 at the moment the signal 11 (15) is inputted. A pulse width comparator circuit 5a (5b) compares the signal 12 (16) with the output signal 10 (inverted output signal 17) and outputs an 'L'-level H-side detecting signal 13 (L-side detecting signal 18) to an OR circuit 6 during the normal output deciding time of the circuit 1 or 'H'-level H-side detecting signal 13 (L-side detecting signal 18) in the other case by regarding the case as an abnormal case. The circuit 6 outputs the OR of both signals to the outside as a discriminating signal 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly to a technique suitable for verifying the operation of a logic LSI or the like.

[0002]

2. Description of the Related Art For example, in a semiconductor circuit such as a flip-flop or a memory, data retention control is performed by a clock or a control signal. Retention may not be performed. At this time, the output of the flip-flop, the memory, or the like may include noise from a peripheral logic circuit or a case where the expected value is output but the data is inverted within the fixed time of the output. For defective noise,
For example, as in the technique disclosed in Japanese Patent Laid-Open No. 63-231281, there is a method in which a narrow noise detection circuit is provided inside the LSI and the noise generated within the output fixed time is detected. Further, in the case of inspecting the logic operation failure within the fixed time such as the case where the data is inverted, the inspection is performed by the following method.

When examining the outputs of the logic circuits 21 and 22 in FIG. 5, the logic circuit 22 is directly connected to the output pin 23, but since the logic circuit 21 is an internal logic circuit, the output signal is output to the output pin 24. Connect the signal. The output pins 23 and 24 output in this way are used to detect a defective logic operation. Here, it is assumed that the logic circuits 21 and 22 have malfunctions and have outputs as shown by the waveform 25 in FIG.
This logic circuit operates as the waveform 26 shown by the broken line in FIG. 6 as a normal output signal. Two methods of detecting this output are shown below. One is to detect a defect by comparing the pulse width t10 of the output waveform of the logic circuit with the regular pulse width t11 using a waveform measuring device such as an oscilloscope. The second is that some timings t12 and t1 are within the pulse width of the normal operation as the determination timing 28 in FIG.
3 ,. ． ． , T14, the defect is extracted by the method of determining the output signal.

[0004]

The above-mentioned conventional technique has been used to inspect the output abnormality of the circuit which outputs the output signal having the specified pulse width or more. However, in these conventional techniques, the output of the logic circuit to be inspected needs to be observed at a waveform or to be tested at some timings. Therefore, the number of logic circuits to be inspected is extremely high. In the case of, there is a problem that work time and test time become long.

An object of the present invention is to provide a semiconductor circuit capable of easily performing operation verification work in a short time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the semiconductor circuit of the present invention operates in synchronization with a clock or a regular control signal and outputs an output signal having a specified pulse width or more, and a change in the output waveform of the circuit under measurement. A first circuit that detects a point and outputs a change point detection signal; and a second circuit that triggers the change point detection signal to output a reference pulse signal having a specified pulse width,
A third circuit for comparing the pulse widths of the output signal of the circuit under test and the reference pulse signal is provided.

[0009]

The first circuit detects a change point of the output signal of the circuit to be measured which is the measurement target, that is, a change in the logical value of the output signal and a change due to noise. The second circuit outputs a reference pulse signal having a prescribed pulse width expected for the output signal of the circuit under measurement, at the same timing as the change point of the output of the circuit under measurement, triggered by the change point detection signal. The third circuit inputs the reference pulse signal and the output signal of the circuit under measurement at the same timing, and outputs the detection signal when the output signal of the circuit under measurement changes while the reference pulse signal having the specified pulse width is input. Output.

With this, by a simple operation of checking the presence or absence of the detection signal from the third circuit, the output signal of each circuit under test in the semiconductor circuit is complicated by using a special device provided outside. It is possible to verify the operation without requiring special observation work, and it is possible to realize the verification work easily and quickly.

[0011]

First Embodiment A semiconductor circuit which is an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of the semiconductor circuit of this embodiment.

The semiconductor circuit of this embodiment is a semiconductor integrated circuit that operates in synchronization with a clock or a regular control signal, and FIG. 1 focuses on one of the specific circuits under test. is there. That is, an additional circuit A surrounded by a broken line in the drawing is connected to the circuit under test 1 including a logic circuit that performs a desired logical operation. In addition, in the case of the present embodiment, the additional circuit A operates in positive logic, and the operation cycle is t2. The additional circuit A includes a change point detection circuit 2, a reference pulse generation circuit 3a, a reference pulse generation circuit 3b, a pulse width comparison circuit 5a, a pulse width comparison circuit 5b, and an OR circuit 6.

The change point detection circuit 2 detects the rising and falling edges of the output signal 10 of the circuit under test 1, and outputs the rising edge detection signal 11 to the reference pulse generating circuits 3a and 3b in the subsequent stage.
And the fall detection signal 15 is output. The reference pulse generation circuits 3a and 3b are circuits that generate a reference pulse signal 12 and a reference pulse signal 16 having a pulse width t2 and a pulse width t3, respectively, by using the rising detection signal 11 and the falling detection signal 15 as a trigger. The values of the pulse widths t2 and t3 of the reference pulse signals 12 and 16 are the same as those of the output signal 1 when the circuit under test 1 is designed or used.
It is a minimum definite time of 0. The pulse width comparison circuit 5a determines the pulse width of the reference pulse signal 12 and the output signal 1 of the circuit under test 1.
When the pulse width of the output signal 10 is narrow, the H side detection signal 13 is output. The pulse width comparison circuit 5b compares the pulse width of the reference pulse signal 16 with the pulse width of the output signal 10 of the circuit under test 1 inverted by the inverter 4, and when the pulse width of the inverted output signal 10 is narrow, The L-side detection signal 18 is output. The H-side detection signal 13 and the L-side detection signal 18 are input to the OR circuit 6, and the determination signal 14 as the logical sum of them is output.

An example of the operation of the semiconductor circuit of this embodiment will be described below.

The output signal of the preceding logic circuit (not shown) operated by a regular signal is input to the circuit under test 1 as an input signal group 19, and the output signal 10 is output. Part of this output signal 10 is the change point detection circuit 2 of the additional circuit A,
It becomes an input signal to the pulse width comparison circuit 5a and the inverter 4. The change point detection circuit 2 outputs the output signal 10 of the circuit under measurement 1
The rising edge detection signal 11 and the falling edge detection signal 15 are output. The rising edge detection signal 11 is the reference pulse generation circuit 3a.
And outputs the reference pulse signal 12. The reference pulse signal 12 is input to the pulse width comparison circuit 5a.
The output signal 10 of the circuit under test 1 is simultaneously input to the pulse width comparison circuit 5a, and the reference pulse signal 12 and the pulse width of the output signal 10 on the logical value H side are compared. The comparison result is input to the OR circuit 6 as the H-side detection signal 13.

Fall detection signal 15 of change point detection circuit 2
Is input to the reference pulse generation circuit 3b and outputs the reference pulse signal 16 to the pulse width comparison circuit 5b. At the same time, the pulse width comparison circuit 5b outputs the output signal 10 of the circuit under test 1
The inverted output signal 17 obtained by inverting the signal is input by the inverter 4, and the pulse widths of the reference pulse signal 16 and the output signal 10 on the logical value L side are compared. The comparison result is output to the L-side detection signal 18. The H-side detection signal 13 and the L-side detection signal 18 are input to the OR circuit 6, and the determination signal 14 as a logical sum is output.

Here, consider a case where the input signal group 19 is input to the circuit under test 1 and the output signal 10 outputs a waveform having an irregular pulse width as shown by the waveform 10 in FIG. At this time, the change point detection circuit 2 detects the change point of the output signal 10 and outputs the rising detection signal 11 and the falling detection signal 15 having the waveforms and timings 11 and 15 in FIG. Using the pulse of the rising edge detection signal 11 of FIG. 2 as a trigger, the reference pulse generator circuit 3a outputs the reference pulse signal 12 having the waveform of the pulse width t2 shown in the waveform 12 of FIG. 2 to the pulse width comparison circuit 5a. .. The pulse width comparison circuit 5a compares the reference pulse signal 12 having the pulse width t2 with the output signal 10 having the pulse width t1, and the pulse width of the output signal 10 is the reference pulse signal 1
At time 9 when it is found to be narrower than 2, the H-side detection signal 13 that has reached the “H” level as shown by the waveform 13 in FIG. 2 is output to the OR circuit 6.

Similarly, when the pulse of the falling edge detection signal 15 having the waveform of 15 in FIG. 2 is used as a trigger, the reference pulse signal 16 having the pulse width t3 shown in the waveform of 16 in FIG. It is output to the width comparison circuit 5b. By the pulse width comparison circuit 5b, the reference pulse signal 16
Is compared with the pulse width t4 of the inverted output signal 17 obtained by inverting the output signal 10, but the pulse width of the inverted output signal 17 is wider than the pulse width t3 of the reference pulse signal 16. As shown by the waveform 18 in FIG. 2, the L-side detection signal 18 is maintained at the “L” level, which indicates a state in which no abnormality has been detected.

The H-side detection signal 13 and the L-side detection signal 18 output from the two pulse width comparison circuits 5a and 5b are
The OR circuit 6 takes the logical sum and outputs it as the determination signal 14. In this example, the output determination signal 14
2 becomes the “H” level as shown by the waveform 14 in FIG. 2, and it is determined that the output signal 10 of the circuit under test 1 is abnormal. By observing the determination signal 14, the circuit under test 1
The abnormality of the output signal 10 can be detected easily and quickly without requiring a complicated work such as taking out the output signal 10 itself to observe it.

[0021]

Second Embodiment A semiconductor circuit which is another embodiment of the present invention will be described with reference to FIGS.

In this example, an input signal 49 composed of normal data and a clock 50 in a semiconductor integrated circuit are provided.
A case is shown in which the flip-flop 31 that performs an operation of outputting the output signal 40 to the post-stage circuit 37 by inputting and is provided with the additional circuit B that verifies the operation of the flip-flop 31. Additional circuit B surrounded by a broken line in FIG.
Operates with positive logic.

Change point detection circuit 32 constituting the additional circuit B
Is the output signal 40 input from the flip-flop 31.
Rising and falling edges are detected, rising edge detection signal 4
1 and the fall detection signal 45 to the reference pulse generation circuit 3
3a and the reference pulse generating circuit 33b. In this case, each of the reference pulse generation circuits 33a and 33b has
The clock 50 is also input at the same time, and the period t20 of the clock 50 is changed to the reference pulse signal 42 by the circuit provided inside.
The pulse generator circuit (not shown) is set so that the pulse width of the reference pulse signal 46 is obtained. Reference pulse signal 4
2 and 46 are pulse width comparison circuits 35a and pulse width comparison circuits 3 as input triggers for the rising edge detection signal 41 and the falling edge detection signal 45 from the change point detection circuit 2.
The reference pulse signals 42 and 46 are output to 5b, respectively.

The output signal 40 of the flip-flop 31 is directly input to the pulse width comparison circuit 35a, and the inverted output signal 4 obtained by inverting the output signal 40 of the flip-flop 31 by the inverter 34 is input to the pulse width comparison circuit 35b.
7 is input.

The pulse width comparison circuits 35a and 35b compare the pulse widths of the reference pulse signal 42 and the reference pulse signal 46 with the pulse widths of the output signal 40 and the inverted output signal 47, respectively. When the pulse width of the signal 47 is narrower than the reference pulse signal 42 and the reference pulse signal 46, respectively, the H-side detection signal 43 and the L-side detection signal 48 at the “H” level are supplied to the subsequent OR circuit 36.
Otherwise, the operation of maintaining the H-side detection signal 43 and the L-side detection signal 48 at the "L" level is performed. The OR circuit performs an operation of taking the logical sum of the H-side detection signal 43 and the L-side detection signal 48 and outputting the result as the determination signal 44 to the outside.

An example of the operation of the semiconductor circuit of this embodiment will be described below.

The flip-flop 31 has a clock 50.
And the input signal 49 are input, and the output signal 40 is output to the post-stage circuit 37. A part of the output signal 40 is input to the pulse width comparison circuit 35b as an inverted output signal 47 via the change point detection circuit 32 of the additional circuit B, the pulse width comparison circuit 35a, and the inverter 34. Change point detection circuit 3
2 outputs the rising detection signal 41 and the falling detection signal 45 of the output signal 40 to the reference pulse generating circuits 33a and 33b. The reference pulse generation circuits 33a and 33b are
The pulse width t2 of the clock 50 is triggered by the input of the rising edge detection signal 41 and the falling edge detection signal 45, respectively.
The reference pulse signal 42 and the reference pulse signal 46 having a pulse width equal to 0 are supplied to the pulse width comparison circuits 35a and 35b.
Output to.

The pulse width comparison circuit 35a compares the pulse widths of the output signal 40 of the flip-flop 31 and the reference pulse signal 42, and when the pulse width of the output signal 40 is narrower than the reference pulse signal 42, the H side detection signal 43 is output. OR circuit 36
Output to.

The pulse width comparison circuit 35b compares the pulse widths of the inverted output signal 47 of the flip-flop 31 and the reference pulse signal 46, and when the pulse width of the inverted output signal 47 is narrower than the reference pulse signal 46, the L side detection signal. OR 48
Output to the circuit 36. The OR circuit 36 uses the H-side detection signal 4
3 and the L-side detection signal 48 are ORed to obtain the determination signal 4
Output as 4.

Here, the input signal 49 shown by the waveform 49 in FIG. 4 is taken in by the flip-flop 31 in synchronization with the clock 50, and delayed by the circuit delay time t21, and the output signal 40 becomes 40 in FIG. Consider a case where the output is made in a state where the pulse width is not normal as shown in the waveform.

This output signal 40 is output to the change point detection circuit 32.
Then, the change point is detected and the rising and falling detection signals 41 and 45 of FIG. 4 are output.

The reference pulse generating circuit 33a is the same as 41 in FIG.
Using the pulse of the rising edge detection signal 41 of the waveform as a trigger, the reference pulse signal 42 having the pulse width set based on the clock 50 is output to the pulse width comparison circuit 35a.
The pulse width of the reference pulse signal 42 is t20.
The waveform of 42 in FIG. The pulse width comparison circuit 35a compares the reference pulse signal 42 having the pulse width t20 with the pulse width t22, and at the time 39 when the pulse width of the output signal 40 is found to be narrow, the H side shown in the waveform 43 of FIG. The detection signal 43 is output to the OR circuit 36.

Similarly, the reference pulse generation circuit 33b triggers the pulse of the falling edge detection signal 45 shown by the waveform 45 of FIG. 4 as a trigger to output the reference pulse signal 46 set by the clock 50 to the pulse width comparison circuit 35b. Output. The reference pulse signal 46 has a pulse width t20 as shown by the waveform 46 in FIG. Pulse width comparison circuit 35b
Thus, the reference pulse signal 46 having the pulse width t20,
The inverted output signal 47 having the pulse width t23 obtained by inverting the output signal 40 is compared. In this case, the reference pulse signal 46
Since the pulse width t23 of the inverted output signal 47 is wider than the pulse width t20 of the L side detection signal 48 of FIG.
As shown in the waveform of No. 8, the "L" level indicating no abnormality is maintained. Two pulse width comparison circuits 35a, 35
The H-side detection signal 43 and the L-side detection signal 48 output from b are ORed by the OR circuit 36, and in this case, output as the "H" level determination signal 44 (waveform 44 in FIG. 4). ). By observing the determination signal 44, the output signal 40 of the flip-flop 31 can be quickly output without performing a complicated work such as directly extracting the output signal 40 of the flip-flop 31 to the outside and observing the output signal 40.
It is possible to detect abnormalities.

The additional circuit A in the first embodiment described above is used.
The determination signal 14 and the determination signal 44 of the additional circuit B according to the second embodiment may be logically summed and output to the outside, so that several circuits to be measured may be collectively diagnosed. .

[0035]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the semiconductor circuit of the present invention, it is possible to verify that the specified pulse width is output based on the output of the third circuit without drawing out the output of the circuit under test to the outside.

In addition, in the case where noise is added from the peripheral logic circuit or the case where the expected value is output but the data is inverted within the specified pulse of the output, it is complicated to observe the waveform of the output of the circuit under test. It can be verified without any work. As a result, the abnormality can be detected only by monitoring the output of the third circuit in both the inspection and the use, so that the abnormality of the semiconductor circuit can be detected easily and quickly.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of a semiconductor circuit that is an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the operation.

FIG. 3 is a block diagram showing an example of a configuration of a semiconductor circuit that is another embodiment of the present invention.

FIG. 4 is a diagram showing an example of the operation.

FIG. 5 is a block diagram showing an example of a configuration of a conventional semiconductor circuit.

FIG. 6 is a diagram showing an example of the operation of a conventional inspection technique.

[Explanation of symbols]

 1 circuit under measurement 2 change point detection circuit (first circuit) 3a reference pulse generation circuit (second circuit) 3b reference pulse generation circuit (second circuit) 4 inverter 5a pulse width comparison circuit (third circuit) 5b Pulse width comparison circuit (third circuit) 6 OR circuit 10 Output signal 11 Rise detection signal 12 Reference pulse signal 13 H side detection signal 14 Judgment signal 15 Fall detection signal 16 Reference pulse signal 17 Inverted output signal 18 L side detection Signal 19 Input signal group 31 Flip-flop (circuit under test) 32 Change point detection circuit (first circuit) 33a Reference pulse generation circuit (second circuit) 33b Reference pulse generation circuit (second circuit) 34 Inverter 35a pulse Width comparison circuit (third circuit) 35b Pulse width comparison circuit (third circuit) 36 OR circuit 37 Rear stage circuit 40 Output signal 1 rising edge detection signal 42 reference pulse signal 43 H-side detection signal 44 the determination signal 45 falling detection signal 46 reference pulse signal 47 inverted output signal 48 L-side detection signal 49 input signal 50 clock A addition circuit B addition circuit

Claims (1)

[Claims] 1. A circuit under test which operates in synchronization with a clock or a regular control signal and outputs an output signal having a prescribed pulse width or more, and a change point detection by detecting a change point of an output waveform of the circuit under test. A first circuit for outputting a signal, a second circuit for outputting a reference pulse signal having a specified pulse width by using the change point detection signal as a trigger, the output signal of the circuit under measurement, and a pulse of the reference pulse signal And a third circuit for comparing widths.