JPH0587888A - Inspecting device for integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate the analysis of the contents in the case where the test result for an integrated circuit is judged as fail and shorten the time for the analysis. CONSTITUTION:A comparator circuit 1 compares an output signal 101 supplied from an integrated circuit, high side judgment level 102 and a low side judgment level 103, and sends the comparison result 104 into a comparison judging circuit 3. The comparison judging circuit 3 compares the comparison result 104 of the comparator circuit 1 and the expected value pattern 105 of a pattern generating circuit 2, and outputs the judgment result 107 into a counter circuit 4 and a fail memory 5. The counter circuit 4 counts the number of times of the output of the expected value pattern 105 from the pattern generating circuit 2, and the judgment result 107 of the comparison judging circuit 3 is counted for each assortment item. The fail memory 5 memorizes the judgment result 107 of the comparison judging circuit 3 successively into the address 106 supplied from the pattern generating circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection device for an integrated circuit, and more particularly to an inspection device for inspecting an output pattern output from the integrated circuit when an inspection signal is input.

[0002]

2. Description of the Related Art Conventionally, in this type of inspection apparatus, when an inspection signal is input to an integrated circuit, the level of the output signal from the integrated circuit is set to a preset high level judgment level (VOH) and low level. Side determination level (VOL) is compared with each other to determine whether the level of the output signal from the integrated circuit is higher than the determination level on the high level side or lower than the determination level on the low level side. The judgment result is compared and judged with a preset expected value pattern to judge the pass / fail of the test for the integrated circuit.

In such a conventional integrated circuit inspection apparatus, the test results for the integrated circuit are classified into two types, pass or fail. Therefore, even if it is judged as fail, the content of the fail is not well understood. There is a drawback.

Further, in order to analyze the content of the failure, it is necessary to create another test pattern or observe the output waveform of the integrated circuit with an oscilloscope or the like.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the prior art, and when the test result for an integrated circuit is judged to be fail, the content thereof can be easily analyzed. It is an object of the present invention to provide an integrated circuit inspection device capable of reducing the time required for the analysis.

[0006]

According to the present invention, there is provided an inspection apparatus, wherein when an inspection signal is input to an integrated circuit to be inspected, an output signal output from the integrated circuit is preset with a first reference value and the first reference value. An integrated circuit testing device having first and second comparing means for respectively comparing with a second reference value having a higher level than a value, which is preset with a comparison result of the first and second comparing means. And a determination means for determining whether the output signal is in the middle of the first and second reference values when a defect of the output signal is detected by comparing And a counting means for counting the results for each of the determination results.

In another inspection apparatus according to the present invention, when an inspection signal is input to an integrated circuit to be inspected, an output signal output from the integrated circuit is set to a preset first reference value and the first reference value. An integrated circuit testing device having first and second comparing means for respectively comparing with a second reference value having a higher level than a value, which is preset with a comparison result of the first and second comparing means. When a defect of the output signal is detected by comparing the output signal with the first pattern,
And a determination means for determining whether or not it is in the middle of the second reference value, and a storage means for sequentially storing the determination result of the determination means.

[0008]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a comparator circuit 1 is an output signal 101 from an integrated circuit (not shown) which is an object to be measured.
And the preset high-side determination level 102 and low-side determination level 103 are compared with each other, and the comparison result 104 is sent to the comparison / determination circuit 3.

The pattern generation circuit 2 generates an expected value pattern 105 to be output from the integrated circuit which is the object to be measured when the inspection signal is input, and outputs it to the comparison / determination circuit 3 and the counter circuit 4. The pattern generation circuit 2 also generates an address 106 for storing the determination result of the comparison / determination circuit 3 in the fail memory 5 and outputs it to the fail memory 5.

The comparison / determination circuit 3 compares the comparison result 104 from the comparator circuit 1 with the expected value pattern 105 from the pattern generation circuit 2, and the test result for the integrated circuit is passed, and the output of the integrated circuit is inverted. Fail,
The output level of the integrated circuit is classified into three, that is, a failure due to an intermediate level between the high side determination level 102 and the low side determination level 103. The comparison / determination circuit 3 outputs the determination result 107 to the counter circuit 4 and the fail memory 5.

The counter circuit 4 counts the number of times the expected value pattern 105 is output from the pattern generation circuit 2 and counts each classification item from the judgment result 107 of the comparison judgment circuit 3. The fail memory 5 stores the judgment result 107 of the comparison judgment circuit 3 at the address indicated by the address 106 from the pattern generation circuit 2.

FIG. 2 is a diagram showing the high side determination level 102 and the low side determination level 103 of FIG. In the figure, the high side determination level 102 is set to a level lower than the high output level of the integrated circuit, and the low side determination level 103 is set to a level higher than the low output level of the integrated circuit. Therefore, the low output level of the integrated circuit <low side determination level 103 <high side determination level 102 <high output level of the integrated circuit.

The operation of one embodiment of the present invention will be described with reference to FIGS. 1 and 2. When testing the integrated circuit, first, a preset inspection signal is input to the integrated circuit, and the output signal 101 of the integrated circuit at that time is input to the comparator circuit 1.

The comparator circuit 1 compares the output signal 101 from the integrated circuit with the high side judgment level 102 and the low side judgment level 103, respectively, and as a result, the high side judgment level 102.
The low side determination level 103 is divided into high / low.

The comparison / determination circuit 3 compares the respective high / low sections for the high-side determination level 102 and the low-side determination level 103 with the expected value pattern 105 from the pattern generation circuit 2. For example, when the expected value pattern 105 is low and the comparator circuit 1 determines that the output signal 101 of the integrated circuit is lower than the low side determination level 103, the comparison and determination circuit 3 passes the determination result. Further, in the comparator circuit 1, the output signal 101 of the integrated circuit is the low side determination level 10
If it is determined that the level is higher than 3, the comparison and determination circuit 3 sets the determination result to fail.

When the comparator circuit 1 determines that the output signal 101 of the integrated circuit is higher than the high-side determination level 102 when it is determined that this is a failure, it is classified as a failure due to the inversion of the output of the integrated circuit, In the comparator circuit 1, the output signal 101 of the integrated circuit is the high side judgment level 10
If the level is lower than 2, the output level of the integrated circuit is high side determination level 102 and low side determination level 103.
It is classified as a failure due to becoming an intermediate level.

At this time, the counter circuit 4 counts the number of times the expected value pattern 105 is output from the pattern generating circuit 2, that is, the number of times the comparison and determination circuit 3 makes a determination. At the same time, the counter circuit 4 counts the number of times the comparison determination circuit 3 classifies as a failure due to the inversion of the output of the integrated circuit,
The number of times the output level of the integrated circuit is classified as a failure due to the intermediate level between the high-side determination level 102 and the low-side determination level 103 is counted. This makes it possible to read the value of the counter circuit 4 after the test of the integrated circuit and analyze the content of the failure when it is determined that the failure has occurred.

On the other hand, the fail memory 5 receives the judgment result of the comparison judgment circuit 3 at the address 106 from the pattern generation circuit 2.
Store 107 sequentially. This makes it possible to read the value stored in the fail memory 5 after the test of the integrated circuit and analyze the content of the fail when it is determined to be fail. For example, when the object to be measured is a memory integrated circuit, a multi-bit fail memory 5 is used, the pattern generation circuit 2 generates an address 106 which is the same as the address of the memory integrated circuit, and the comparison judgment circuit 3 generates the address 106. The determination result 107 is stored in sequence. This makes it possible to easily analyze the content of the memory integrated circuit when it is determined that the memory integrated circuit has failed.

Here, each of the circuits described above is provided for each output pin of the integrated circuit, and the above-described operation is independently performed for each output pin. As a result, after the test of the integrated circuit is completed, the contents of the counter circuit 4 and the fail memory 5 for each output pin can be read and the contents of the fail can be displayed.

In this way, the comparator circuit 1 compares the output signal 101 from the integrated circuit with the high side judgment level 102 and the low side judgment level 103, and the comparison judgment circuit 3 compares the comparison result with the pattern generation circuit 2. The expected result pattern 105 of the comparison decision circuit 3 is compared with the expected result pattern 105 of the comparison decision circuit 3 and the decision result 107 of the comparison decision circuit 3 is obtained from the address 106 from the pattern generation circuit 2.
By sequentially storing in the fail memory 5 in accordance with the above, it is possible to analyze the content of the fail when the test result of the integrated circuit is fail in one test. Therefore, when the test result for the integrated circuit is determined to be fail, the content can be easily analyzed and the time for the analysis can be shortened.

In the embodiment of the present invention, the comparison / determination circuit 3 is used.
The determination result 107 of is counted by the counter circuit 4, and
Although the data is sequentially stored in the fail memory 5, only one of them may be stored and the invention is not limited to this.

[0023]

As described above, according to the present invention, when the inspection signal is input to the integrated circuit to be inspected, the output signal output from the integrated circuit is preset with the first and second reference values. When a defect in the output signal of the integrated circuit is detected by comparing the comparison result with a preset pattern, the output signal is between the first and second reference values. By counting the determination result for each determination result or storing the determination results sequentially, when the test result for the integrated circuit is determined to be fail, the content can be easily analyzed. It is possible,
There is an effect that the time for the analysis can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a high-side determination level and a low-side determination level of FIG.

[Explanation of symbols]

 1 comparator 2 pattern generation circuit 3 comparison judgment circuit 4 counter circuit 5 fail memory

Claims (2)

[Claims] 1. An output signal output from an integrated circuit to be inspected when an inspection signal is input to the integrated circuit to be inspected, has a preset first reference value and a first reference value having a level higher than the first reference value. An integrated circuit testing device having first and second comparing means for respectively comparing with a reference value of 2, wherein the first
And when the comparison result of the second comparing means is compared with a preset pattern to detect a defect in the output signal, whether the output signal is in the middle of the first and second reference values. An inspection apparatus comprising: a determination unit that determines whether or not the determination result and a counting unit that counts the determination result of the determination unit for each determination result. 2. An output signal output from an integrated circuit to be inspected when the inspection signal is input to the integrated circuit to be inspected is a preset first reference value and a first level higher than the first reference value. An integrated circuit testing device having first and second comparing means for respectively comparing with a reference value of 2, wherein the first
And when the comparison result of the second comparing means is compared with a preset pattern to detect a defect in the output signal, whether the output signal is in the middle of the first and second reference values. An inspection apparatus comprising: a determination unit that determines whether or not a determination result and a storage unit that sequentially stores determination results of the determination unit.