JPH04205899A - Semiconductor manufacturing device - Google Patents

Semiconductor manufacturing device

Info

Publication number
JPH04205899A
JPH04205899A JP2336133A JP33613390A JPH04205899A JP H04205899 A JPH04205899 A JP H04205899A JP 2336133 A JP2336133 A JP 2336133A JP 33613390 A JP33613390 A JP 33613390A JP H04205899 A JPH04205899 A JP H04205899A
Authority
JP
Japan
Prior art keywords
product
defective
test
semiconductor manufacturing
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2336133A
Other languages
Japanese (ja)
Inventor
Tetsuo Kato
哲夫 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2336133A priority Critical patent/JPH04205899A/en
Publication of JPH04205899A publication Critical patent/JPH04205899A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the yield of a memory by providing a changing means which changes measuring conditions and analyzing means which discriminates the possibility of changing a defective product to an acceptable product when a redundancy circuit is used. CONSTITUTION:A measuring means is controlled by means of a control circuit 2. When this semiconductor manufacturing device is started, an analyzing means 1 discriminates whether or not a defective product can be changed to an acceptable product. When it is discriminated that a defective product can be changed to an acceptable product, tests are repeatedly executed under stricter test conditions. At the time of discriminating a product as defective, the product is regarded as a defective product when the discrimination is made on the results of the first test and the results of the preceding test is utilized when the discrimination is made on the results of the second and after second tests. Therefore, the quality of a memory can be secured sufficiently even when the memory has no testing margin.

Description

【発明の詳細な説明】 [産業上の利用分野コ この発明は半導体製造装置、特に半導体記憶素子(以下
メモリーと呼ぶ)を測定するテスターに関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a tester for measuring semiconductor manufacturing equipment, particularly semiconductor storage elements (hereinafter referred to as memories).

[従来の技術] メモリーは集積度の向上と共に冗長回路の必要性かます
ます大きくなっている。第3図は従来のメモリーを測定
し、冗長回路を使用するか否かを決めるテストフローチ
ャートである。ステップ1はテストA、ステップ2は冗
長回路を使用して良品に変更可能かを判定する解析部分
て、テストAは測定項目である。
[Prior Art] As the degree of integration of memories increases, the need for redundant circuits increases. FIG. 3 is a test flowchart for measuring a conventional memory and determining whether to use redundant circuitry. Step 1 is test A, step 2 is an analysis part that uses a redundant circuit to determine whether it can be changed to a non-defective product, and test A is a measurement item.

従来、測定項目は測定条件及び測定内容は予め決められ
ており、不変である。
Conventionally, the measurement conditions and measurement contents of measurement items are determined in advance and remain unchanged.

次に動作について説明する。測定されるメモリーに対し
て、テストAを実施する(ステップ1)。その結果をも
とに解析を行い、メモリーに予め備えられている冗長回
路を用いて良品に変更可能か否かを判定する(ステップ
2)。判定結果によって、良品であれば不良の状態をコ
ート化する(ステップ3.ステップ4)。
Next, the operation will be explained. Test A is performed on the memory to be measured (step 1). An analysis is performed based on the results, and it is determined whether the product can be changed to a non-defective product using a redundant circuit previously provided in the memory (step 2). Based on the determination result, if the product is good, the defective state is coated (step 3, step 4).

[発明が解決しようとする課題] 従来の半導体製造装置のテスターはそのテスト条件が固
定されていたので、テスト条件のわずかな変動によって
不良となるメモリーに対して、1度だけのテストで判定
を下すのは不十分であるという問題点かった。
[Problem to be solved by the invention] Conventional testers for semiconductor manufacturing equipment have fixed test conditions, so it is difficult to judge memory that becomes defective due to slight variations in test conditions with only one test. The problem was that it wasn't enough.

この発明はF記のような問題点を解消するためになされ
たものて、テストマージンのないメモリーに対して、十
分な保証をする半導体製造装置を得ることを目的とする
This invention has been made to solve the problems described in F, and aims to provide a semiconductor manufacturing apparatus that provides sufficient guarantees for memories without test margins.

[課題を解決するための手段] この発明に係る半導体製造装置は、測定条件を変更する
変更手段と、冗長回路の使用によって良品に変更可能の
可否を判定する解析手段とを設けたものである。
[Means for Solving the Problems] A semiconductor manufacturing apparatus according to the present invention is provided with a changing means for changing measurement conditions and an analysis means for determining whether or not a non-defective product can be changed by using a redundant circuit. .

[作用] この発明における変更手段は、解析手段の結果より測定
条件を変更する。
[Operation] The changing means in this invention changes the measurement conditions based on the results of the analysis means.

[実施例] 以下、この発明の一実施例を図について説明する。[Example] An embodiment of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例を示す半導体製造装置のテ
スターのブロック図である。図において、(1)は冗長
回路の使用によって良品に変更可能の可否を判定する解
析手段、(2)は制御回路、(2I)は判定手段、(2
2)は変更手段で、解析手段(1)か測定条件を変更す
る変更手段により構成される。(3)は測定手段て、変
更手段(22)によって制御を行うものである。
FIG. 1 is a block diagram of a tester for semiconductor manufacturing equipment showing an embodiment of the present invention. In the figure, (1) is an analysis means for determining whether or not it can be changed to a non-defective product by using a redundant circuit, (2) is a control circuit, (2I) is a determination means, (2
2) is a changing means, which is constituted by the analyzing means (1) or a changing means for changing the measurement conditions. (3) is a measuring means that is controlled by a changing means (22).

次に動作について説明する。Next, the operation will be explained.

測定手段(3)は制御回路(2)により第2図のフロー
チャートに示す如く制御かなされる。図において、スタ
ートするとステップ2Aて解析手段(1)を用いて良品
になるかどうかの判断をする。
The measuring means (3) is controlled by the control circuit (2) as shown in the flowchart of FIG. In the figure, when the process starts, in step 2A, the analysis means (1) is used to determine whether or not the product will be of good quality.

良品になる場合はステップ4Aてテスト条件を厳しくし
、ステップIAでテストを繰り返し実行する。
If the product is non-defective, the test conditions are made stricter in step 4A, and the test is repeated in step IA.

ステップ2Aで良品にならないと判定した場合、それが
1回目のテストの結果であれば不良品とし、2回目以降
のテストであれば、1つ前のテスト結果を利用すること
にする。
If it is determined in step 2A that the product will not be non-defective, if it is the result of the first test, it will be determined to be a defective product, and if it is the second or later test, the result of the previous test will be used.

[発明の効果] 以上のようにこの発明によれば、冗長回路のすべてを使
用することによってメモリーの歩留りの向上を図ること
かてきるという効果かある。
[Effects of the Invention] As described above, according to the present invention, the yield of memory can be improved by using all of the redundant circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す半導体製造装置のテ
スターのブロック図、第2図は第1図のデスタ−の制御
手段を示すフローチャート図、第3図は従来の半導体製
造装置のテスターの測定方法を示すフローチャート図で
ある。 図において、(1)は解析手段、(2)は制御回路、(
21)は判定手段、(22)は変更手段、(3)は測定
手段を示す。 代理人  大  岩  増  雄 第2図 第3図
FIG. 1 is a block diagram of a tester for semiconductor manufacturing equipment showing an embodiment of the present invention, FIG. 2 is a flowchart showing control means for the tester shown in FIG. 1, and FIG. 3 is a block diagram of a tester for a conventional semiconductor manufacturing equipment. FIG. 2 is a flowchart showing a measuring method. In the figure, (1) is the analysis means, (2) is the control circuit, (
21) is a determining means, (22) is a changing means, and (3) is a measuring means. Agent Masuo Oiwa Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims]  半導体記憶素子を測定する半導体製造装置のテスター
、このテスターによって測定する測定手段、この測定手
段によって測定される各測定項目の不良状態を解析し、
冗長回路の使用によって良品に変更可能の可否を判定す
る解析手段、この解析手段が良品に変更可能と判断した
結果、測定条件を変更する変更手段を備えたことを特徴
とする半導体製造装置。
A tester for semiconductor manufacturing equipment that measures semiconductor memory elements, a measuring means to be measured by this tester, and a failure state of each measurement item measured by this measuring means,
A semiconductor manufacturing apparatus comprising: an analysis means for determining whether or not a product can be changed to a non-defective product by using a redundant circuit; and a change means for changing measurement conditions when the analysis means determines that the product can be changed to a non-defective product.
JP2336133A 1990-11-29 1990-11-29 Semiconductor manufacturing device Pending JPH04205899A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2336133A JPH04205899A (en) 1990-11-29 1990-11-29 Semiconductor manufacturing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2336133A JPH04205899A (en) 1990-11-29 1990-11-29 Semiconductor manufacturing device

Publications (1)

Publication Number Publication Date
JPH04205899A true JPH04205899A (en) 1992-07-28

Family

ID=18296041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2336133A Pending JPH04205899A (en) 1990-11-29 1990-11-29 Semiconductor manufacturing device

Country Status (1)

Country Link
JP (1) JPH04205899A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250124A (en) * 2006-03-17 2007-09-27 Fujitsu Ltd Test method, test device and test program, for semiconductor device
JP2012078276A (en) * 2010-10-05 2012-04-19 Hioki Ee Corp Circuit board inspection device and circuit board inspection method
JP2012078277A (en) * 2010-10-05 2012-04-19 Hioki Ee Corp Circuit board inspection device and circuit board inspection method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250124A (en) * 2006-03-17 2007-09-27 Fujitsu Ltd Test method, test device and test program, for semiconductor device
JP2012078276A (en) * 2010-10-05 2012-04-19 Hioki Ee Corp Circuit board inspection device and circuit board inspection method
JP2012078277A (en) * 2010-10-05 2012-04-19 Hioki Ee Corp Circuit board inspection device and circuit board inspection method

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