JP2527623Y2 - IC test equipment - Google Patents

Description

[Detailed description of the invention] "Industrial application field" This invention supplies a test signal to the IC device under test, and when the output of the IC device at that time assumes the high level as the expected value, it is higher than the reference high level. The present invention relates to an IC test apparatus for detecting whether or not a low level is an expected value when a low level is an expected value.

[Prior Art] FIG. 3 shows a part of a conventional IC test apparatus, that is, a part for determining the output of an IC element under test. The output of the IC under test 11 is compared with the reference high level by the high level comparator 12, and the high level comparator 12 outputs a low level when the IC element output is higher than the reference high level, and outputs a low level when the IC element output is lower than the reference high level. Output level. Also, the output of the IC under test 11 is compared with the reference low level by the low level comparator 13, and the low level comparator 13 outputs a low level when the IC element output is lower than the reference low level, and outputs a low level when the IC element output is higher than the reference low level. Output high level.

The output of the high-level comparator 12 and the output of the low-level comparator 13 are respectively latched by the high-level latch circuit 15 and the low-level latch circuit 16 by a common strobe from the terminal 14. The logical product of the output of the high-level latch circuit 15 and a signal (high-level expected value) EXPH indicating that the high level from the terminal 17 is the expected value is obtained by the high-level AND circuit 18. The output of the low-level latch circuit 16 is obtained by a level-and-circuit 21 having a low logical product with a signal (low-level expected value) EXPL indicating that the low level from the terminal 19 is set as the expected value. The inverted signal of the high-level expected value is also input to the low-level AND circuit 21, and the inverted signal of the low-level expected value is also input to the high-level AND circuit 18.

The output of the high-level latch circuit 15 is inverted by the inverter 22a and supplied to the OR circuit 23, and the output of the low-level latch circuit 16 is inverted by the inverter 22b and supplied to the OR circuit 23. The logical product of the output of the OR circuit 23, the high-level expected value EXPH, and the low-level expected value EXPL is obtained by the Z-mode failure detection AND circuit 24.

If the output of the IC element 11 is below the reference high level when the high level is the expected value, the output of the high level AND circuit 18 becomes high level “1”, a high level fault HFAIL is output, and a low level is expected. When the value is set to the value, if the output of the IC element 11 is equal to or higher than the reference low level, the output of the low level AND circuit 21 becomes high level “1”, and a low level fault LFAIL is output. When the expected value is between the reference high level and the reference low level (referred to as Z mode), both the high-level expected value EXPH and the low-level expected value EXPL are set to the high level “1”, and the IC element When the output 11 is equal to or higher than the reference high level or equal to or lower than the reference low level, the output of the Z-mode failure detection AND circuit 24 becomes high level “1” and the Z-mode failure ZFAIL
Is output.

Switching of the output waveform of the IC under test 11 during one test cycle with the conventional IC testing apparatus shown in FIG.
That is, to test whether the change from the low level to the high level or the change from the high level to the low level is performed correctly, for example, as shown in FIG. 4A, the output of the IC under test 11 is output during one test cycle. When the level changes from the low level to the high level, the strobe timing of the terminal 14 is selected in the low level section to check whether or not the output of the IC element is at the low level (lower than the reference low level). 4 As shown in FIG. B, the strobe timing is shifted to the high-level section of the IC element output to check whether or not the IC element output is at the high level (above the reference high level). That is, it was necessary to perform the test twice.

In order to test whether or not the output waveform of the IC element is correctly switched during one test cycle in one test, conventionally, as shown in FIG. 5, a high-level comparator 12 and a low-level comparator 12 are used. The output side of the level comparator 13 is duplicated. That is, the same parts as those shown in FIG.
As shown in the figure, the timing of strobe 1
Select the low-level section of the element output, select the timing of strobe 2 at terminal 14 'to the high-level section of the IC element output, and switch the output waveform from each output of AND circuits 18, 21, 18', and 21 '. To see if it is done correctly. However, the apparatus shown in FIG. 5 has a drawback that the circuit is duplicated and the scale of hardware is increased.

According to the present invention, the high-level latch circuit that latches the output of the high-level comparator is latched by the high-level strobe, and the low-level latch circuit that latches the output of the low-level comparator is The latch is performed by the low-level strobe, that is, the high-level latch circuit and the low-level latch circuit can be latched by different strobes. In addition, the OR of the output of the high-level latch circuit and the output of the low-level latch circuit is obtained by the second OR circuit. When the switching of the output waveform during one test cycle is tested, the selector selects the second OR circuit. The output is switched and provided to the Z-mode failure detection AND circuit.

"Embodiment" FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. 3 are denoted by the same reference numerals. In the present invention, the high-level latch circuit 15 is latched by the high-level strobe from the terminal 25, and the low-level latch circuit 16 is latched by the low-level strobe from the terminal 26. It is possible to latch at the timing shown in FIG. Further, the output of the high level latch circuit 15 and the output of the low level latch circuit 16 are supplied to the second OR circuit 27, and one of the output of the first OR circuit 23 and the output of the second OR circuit 27 is selected by the selector 28. Then, it is supplied to the Z-mode failure detection AND circuit 24. When the inverted signal MODE of the signal indicating the Z mode is "0" (in the Z mode), the selector 28 outputs the first signal.
When the output of the OR circuit 23 is selected and the signal MODE is “1” (Z
(Other than the mode), the output of the second OR circuit 27 is selected.

Also in this configuration, when the high level is the expected value and the output of the IC element 11 is equal to or lower than the reference high level, the high level AND circuit 18 outputs a high level fault HFAIL,
If the output of the IC element 11 is equal to or higher than the reference low level when the low level is the expected value, the low level AND circuit 21 outputs a low level fault LFAIL. In these, the selector 28 selects the output of the second OR circuit 27 and outputs "1". However, since either the high-level expected value EXPH or the low-level expected value EXPL is "0", Z The output of the mode failure detection AND circuit 24 remains "0". When the Z mode, that is, when it is expected to be between the reference high level and the reference low level, the output of the first OR circuit 23 is selected by the selector 28, and the high level expected value EXPH and the low level expected value
Both EXPL are set to "1". Therefore, when the output of the IC element 11 is equal to or higher than the reference high level or equal to or lower than the reference low level, the Z-mode failure ZFAIL is output from the Z-mode failure detection AND circuit 24. In detecting these defects, strobes with the same timing are generally applied to the terminals 25 and 26.

Further, in this configuration, in order to test whether or not the output waveform of the IC element 11 has been correctly switched during one test cycle, the selector 28 selects the second OR circuit 27, and
The high-level expected value EXPH and the low-level expected value EXPL are both set to “1”, and the timing of the high-level strobe at the terminal 25 is selected in the high-level section of the output of the IC element 11 as shown in FIG. The timing of the low-level strobe at pin 26 is
It is selected in the low level section of the output of the IC element 11. Therefore, if the output of the IC element 11 is equal to or higher than the reference low level in this example before the waveform switching, the output of the low-level latch circuit 16 becomes "1" and the output of the Z-mode failure detection AND circuit 24 becomes "1". If the output of the IC element 11 is equal to or lower than the reference high level after the waveform switching, the output of the high-level latch circuit 15 becomes "1", and the output of the Z-mode failure detection AND circuit 24 becomes "1". . That is, if the output waveform of the IC element 11 is not properly switched, “1” is output from the Z-mode failure detection AND circuit 24.

"Effects of the invention" As described above, according to the invention, the conventional device shown in FIG. 3 is slightly modified and a small number of circuits are added, thereby achieving high level failure and low level Defective and Z-mode deficiencies can be detected, and waveform switching within one test cycle can be checked by one test.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an essential part of an embodiment of an IC test apparatus according to the present invention, FIG. 2 is a view showing an operation example at the time of a waveform switching check, and FIG. 3 is a part of a conventional IC test apparatus. FIG. 4 is a diagram showing an example of an operation of performing a waveform switching check by the apparatus of FIG. 3, FIG. 5 is a block diagram showing a part of another conventional IC test apparatus, and FIG. Fifth
It is a figure which shows the example of an operation | movement which performs a waveform switching check by the apparatus of a figure.

Claims (1)

(57) [Scope of request for utility model registration] 1. A high-level comparator for comparing an output of an IC device under test supplied with a test signal with a reference high level, and a low-level comparator for comparing an output of the IC device under test with a reference low level. A high-level latch circuit for latching the output of the high-level comparator with a high-level strobe, a low-level latch circuit for latching the output of the low-level comparator with a low-level strobe, and the high-level latch circuit And a high-level AND circuit which takes the logical product of the output of the high-level expected value and the inverted low-level expected value, and the output of the low-level latch circuit and the inverted low-level expected value and the high-level expected value A low-level AND circuit for performing an AND operation with a first OR circuit; and a first OR circuit for performing an OR operation on an inverted output of the output of the high-level latch circuit and an inverted output of the output of the low-level latch circuit A second OR circuit that performs an OR operation on the output of the high-level latch circuit and the output of the low-level latch circuit; and selects one of the output of the first OR circuit and the output of the second OR circuit. An IC test apparatus comprising: a selector; and a Z-mode failure detection AND circuit that takes a logical product of an output of the selector, the high-level expected value, and the low-level expected value.