JPS63159772A - Semiconductor testing device - Google Patents

Abstract

PURPOSE:To perform stable inspection under operation conditions exceeding a prescribed value by supplying a reference device with an input applied voltage from a buffer circuit and a source voltage from a correcting circuit with values suitable to function displaying respectively. CONSTITUTION:The buffer circuit 21 supplies the reference device 8 with the input applied voltage for function testing which is applied from a pin data selector 7 to a semiconductor device 3 to be measured after varying it to a suitable value with which the function can be displayed. Further, the correcting circuit 22 varies the source voltage to an operating voltage suitable to the displaying of the function. Then, a capacitor 22d serves as a decoupling capacitor for operating the device 8 stably, so the device 8 operates normally at the same time with the device 3 to be tested and data for confirming the normal operation of the device 3, i.e. an expected value for the function test can be outputted normal, thereby inspecting stably whether or not the device 3 is normal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor testing device for performing funxilan tests on increasingly diverse semiconductor devices.

[Conventional technology]

FIG. 2 is a block diagram showing each function of a conventional semiconductor testing device (hereinafter referred to as a tester). The disk 1 stores a test program created in advance to test the semiconductor device under test (MUT) 3, and the tester processor 2 reads a desired test program from the disk 1 and executes the test program. Power supply required to operate MUT 3 ft based on 4. Timing generator5. Address pattern generator6. The pin data selector 7 and the comparator 9a in the data comparator 9 are set to 1) 1), and the MUT
Test whether 3 is good or bad. The expected value used to check whether the output data of the MUT 3 is normal is the output data of the reference device 8, which is the same device as the MUT 3 and is mounted inside the tester 10.

Next, the operation will be explained. The MUT 3 is operated by the tester processor 2 based on a test program created in advance on the disk drive 1, and its functions are tested. The test procedure is as follows.

First, voltage conditions (input applied voltage, power supply voltage) and timing conditions (change times of address signals, clock signals, etc.) necessary for operating the MUT 3 are set. That is, the voltage applied to the MUT 3 is set by the power supply 4, and the change time of each signal in the test cycle is set by the timing generator 5. Then, the test data for the MUT test generated by the address pattern generator 6 is passed through the data selector 7 to the input bin of the MUT 3 (
address bin, clock bin). At this time, the same conditions for operating the MUT 3 are also applied to the reference device 8 inside the tester IO. the result,
The output value of the reference device 8 becomes an expected value for testing whether the output data of the MUT 3 is normal or not, and the expected value and the output data of the MUT 3 are compared by a comparator 9a in the data comparator 9. This allows MUT
The 0-piece method that can identify whether or not 3 has been manufactured normally is generally the Goulzon device or King device (herein referred to as the reference device).
This is said to be a comparative inspection method.

[Problem that the invention seeks to solve]

Conventional semiconductor test equipment is configured as described above.
For example, when testing under severe operating conditions that exceed the standard values of the MUT in order to guarantee product specifications, the reference device is also operated under the same conditions as the MUT, so there may be fluctuations due to changes in the tester over time, accuracy in repeatability, etc. There is a possibility that the reference device malfunctions due to this, and there is a problem that it becomes difficult to stably obtain expected values for testing the MUT.

This invention was made to solve the above-mentioned problems, and even when the MUT is tested under operating conditions exceeding its standard values, the reference device can be operated stably and normally, and the MUT can be stably operated. The purpose of the present invention is to obtain a semiconductor testing device that can be used for inspection.

[Means for solving problems]

A semiconductor testing apparatus according to the present invention is provided with a buffer circuit and a correction circuit for applying an input voltage and a power supply voltage to a reference device at respective values suitable for the performance of the device.

[Effect]

In this invention, for the reference device,
The input applied voltage is supplied by the buffer circuit, and the power supply voltage is supplied by the correction circuit at values suitable for the performance of the device, so the reference device can operate stably and normally regardless of the MUT test conditions. , it is possible to stably obtain an expected value that serves as a reference for the output data of the MUT, and it is possible to perform an inspection with good accuracy <MUT.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor testing device according to an embodiment of the present invention. In the figure, the same symbols as in Figure 2 indicate the same things,
21 changes the function test input voltage applied from the bin data selector 7 to the MUT 3 to a value suitable for the reference device 8 to perform its function (a so-called typical value), and applies it to the device 8. This is a simple buffer gate manufactured in the same technology as the reference device 8, such as MOS, CMO3, F, CL, etc. 22 is a correction circuit that sets the power supply voltage to a typical operating voltage of the reference device 8, 22a is a fixed power supply, 22b is a variable resistor, 22c
is a fixed resistor, 22d is a decoupling capacitor, 2
2e is GND. Further, the reference device 8 used in this embodiment is the same as the MUT 3 as in the conventional device, but under certain conditions, for example, when the input applied voltage/power supply voltage is a typical value for the device, it does not function normally. This is a good product that has been proven to work in advance. however,
Here, the means for confirming whether the product is good or not does not matter. For example, in an actual device that uses the reference device 8 (=MUT3), or by other memory testers with high functionality, it is simply determined that the normal operation of the reference device 8 is near the typical voltage conditions (nearby means that the tester 10 is It is sufficient if the voltage range is guaranteed within the voltage level accuracy guaranteed in the product specifications. In general, a semiconductor device has a certain range of operating conditions for achieving its functions, but each type has conditions that make it easier to realize operations that satisfy its functions.

These conditions are referred to here as typical conditions.

In the semiconductor test equipment having such a configuration, the procedure for operating and testing the MUT 3 and the reference device 8 is the same as that of the conventional equipment, but the input voltage applied to the reference device 8 by the buffer circuit 21 is a typical value. The power supply voltage becomes a typical operating power supply voltage of the reference device 8 depending on the correction circuit 22, that is, the ratio of the variable resistor 22b and the fixed resistor 22c from the fixed power supply 22a, and furthermore, the capacitor 22d Since it serves as a decoupling capacitor for stable operation, the reference device 8 operates normally at the same time as the MUT3 to be tested, and provides data to confirm the normal operation of the MUT3, that is, the expected value in the function test. It is possible to output normally, and the quality of the MUT 3 can be stably inspected.

In the above embodiment, the reference device 8, the buffer circuit 21, and the correction circuit 22 are mounted inside the tester 10, but this is mounted on the same measurement board as the MUT 3, so that the stable A normal output signal may be taken into the tester 10.

〔Effect of the invention〕

As described above, according to the semiconductor testing apparatus of the present invention, since the buffer circuit and the correction circuit are provided to give the input applied voltage and the power supply voltage to the reference device at typical values, it is possible to correspond to the output data of the MUT. The reference device that outputs the expected value can be stably operated, and the quality of the MUT can be improved by stably inspecting the quality of the MUT.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a semiconductor testing device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional semiconductor testing device. In the figure, ■... Disk, 2... Tester processor, 3... Semiconductor device under test (MUT), 4...
・Power supply, 5... Timing generator, 6...
・Address pattern generator, 7... Pin data selector, 8... Reference device, 9... Data comparison H19a... Comparator, 1o... Semiconductor test bag W (tester), 21... Buffer Circuit, 22...
Correction circuit, 22a... fixed power supply, 22b... variable resistor, 22c... fixed resistor, 22d... capacitor,
22e...GND. Note that the same reference numerals in the figures indicate the same or equivalent parts. Procedural Dispute (Sho 61-314419) February 1982, Commissioner of the Japan Patent Office, 82, 1, Indication of Case Patent Application No. 61-314419 2, Title of Invention Semiconductor Testing Device 3, Amendment Relationship with the case of a person who does
1) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Postal code 532 Address Shin-Osaka Yachiyo Building 5, 4-1-45 Miyahara, Yodoyo-ku, Osaka City Drawings subject to amendment (Fig. 2) 6. Amendment Content TI) Figure 2 is corrected as shown in the attached sheet. that's all

Claims (1)

[Claims] (1) A semiconductor device under test that has a logic operation function and a data storage function, and a device that is the same as the semiconductor device under test and that has data for determining whether the output data of the semiconductor device under test is normal. Run the output reference device based on the test program on the disk,
In a semiconductor testing device that tests the quality of the semiconductor device under test by comparing the output data of both, the input voltage applied to the reference device and the power supply voltage are set to values suitable for the device to perform its functions. What is claimed is: 1. A semiconductor testing device characterized by comprising a buffer circuit and a correction circuit.